CN115692533A - TOPCon battery and preparation method thereof - Google Patents
TOPCon battery and preparation method thereof Download PDFInfo
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- CN115692533A CN115692533A CN202211430889.8A CN202211430889A CN115692533A CN 115692533 A CN115692533 A CN 115692533A CN 202211430889 A CN202211430889 A CN 202211430889A CN 115692533 A CN115692533 A CN 115692533A
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Abstract
The invention relates to the technical field of TOPCon battery manufacturing, in particular to a TOPCon battery and a preparation method thereof. During preparation, a plurality of groups of film layers are arranged on the back surface of the cell, wherein the tunneling oxide layer is isolated from the first doped crystalline silicon layer and the second doped crystalline silicon layer by using the first silicon nitride, so that the first doped crystalline silicon layer can be matched with the ultrathin tunneling oxide layer by using low doping concentration. The second doped crystalline silicon layer is doped with high concentration to reduce the transmission resistance of the polycrystalline silicon. The first silicon nitride protective layer may also provide H-passivation during polysilicon thermal processing, tunneling through dangling bonds of the oxide cross-section. And the second silicon nitride and the dielectric layer compounded on the second silicon nitride form an anti-reflection and anti-reflection structure, so that the current of the battery is improved. Meanwhile, the two films can also be used as a slurry barrier layer to prevent slurry from burning through the back passivation structure.
Description
Technical Field
The invention relates to the technical field of TOPCon battery manufacturing, in particular to a TOPCon battery and a preparation method thereof.
Background
The TOPCon (tunneling oxidation passivation contact) cell is a high-efficiency solar cell, and a passivation contact structure is formed by arranging an ultrathin tunneling oxidation layer and a doped polycrystalline silicon thin layer on the back of a device, so that minority carrier hole recombination can be effectively blocked, and the open-circuit voltage and the short-circuit current of the cell are improved.
The existing TOPCon cell production technology usually prepares an ultra-thin tunneling oxide layer of 0.8-2nm on the back of a silicon wafer, then deposits a doped polysilicon layer with the thickness of 60-160nm on the SiOx surface, and finally deposits silicon nitride on the doped polysilicon layer. The structure provides good surface passivation and field passivation for the back of the silicon chip, the ultrathin oxide layer can enable electrons to tunnel into the polycrystalline silicon layer and simultaneously block the transport of holes, and the recombination current is reduced. The doped polysilicon layer lateral transfer characteristics reduce the series resistance. The two characteristics jointly improve the open-circuit voltage, the filling factor and the conversion efficiency of the battery.
The back side of the TOPcon cell is a pyramid-based structure, and the polished structure usually uses an ultra-thin silicon oxide layer as a tunneling layer. Because the increase of the thickness of the silicon oxide tunneling layer can cause the reduction of the filling factor of the battery and influence the conversion efficiency of the battery, the tunneling layer on the back of the TOPcon battery is better when the thickness is thinner, but the process window of the thin oxide layer is narrow and is not easy to match with the process of the doped crystalline silicon layer in large-scale production, the battery filling and the voltage switching fluctuation are easily caused, and the discreteness of the battery efficiency is large. The two are difficult to match, specifically, in order to reduce the lateral transmission resistance of the polysilicon, heavily doping phosphorus to the doped crystalline silicon is needed, but the heavily doping easily causes excessive phosphorus to diffuse into the tunneling oxide layer to damage the tunneling effect in the subsequent thermal treatment of polysilicon conversion. The doped crystalline silicon layer absorbs light more severely, and the thicker the doped crystalline silicon layer, the greater the current loss. When the doped crystalline silicon layer is too thin, the doped crystalline silicon layer is easy to burn through in the process of back slurry sintering.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a TOPCon battery and a preparation method thereof.
The technical scheme for realizing the purpose of the invention is as follows: a TOPCon battery is provided with a tunneling oxide layer, a first doped crystalline silicon layer, at least one layer of first silicon nitride, a second doped crystalline silicon layer, at least one layer of second silicon nitride and a dielectric layer from top to bottom, wherein the thickness of the first doped crystalline silicon layer is 5-40 nm, the first silicon nitride is a silicon nitride layer, the second silicon nitride is a laminated layer of the silicon nitride layer and a Si silicon oxynitride layer, and the dielectric layer is one of an aluminum oxide antireflection film, a silicon oxynitride antireflection film and a magnesium fluoride antireflection film.
The thickness of the tunneling oxide layer is 0.8-1.2 nm.
The first doped crystalline silicon layer in the technical scheme is 20nm, and the activated impurity Concentration is 0.8E + 19-1.2E +20Concentration/cm 3 。
The thickness of the first silicon nitride is 5-20 nm.
According to the technical scheme, the thickness of the first silicon nitride is 10nm.
According to the technical scheme, the thickness of the second doped crystalline silicon layer is 20-80 nm.
According to the technical scheme, the thickness of the second silicon nitride is 60-95 nm.
According to the technical scheme, the thickness of the second silicon nitride is 75nm.
According to the technical scheme, the dielectric layer is made of silicon oxynitride, and the thickness of the dielectric layer is 5-20 nm.
A preparation method of a TOPCon battery comprises the following steps:
step one, using a plate type PECVD linear plasma structure, using oxygen as glow gas to grow an oxide layer at 200-300 ℃, and growing a tunneling oxide layer by using a plasma method;
depositing a first doped crystalline silicon layer by using PVD (physical vapor deposition), taking mixed phosphine gas as a doping source, taking a silicon target material with the purity of more than 2N as a sputtering source, wherein the process temperature is 150-300 ℃, and the power of the first layer of doped crystalline silicon is selected to be 2000-20000W;
depositing first silicon nitride by PVD, taking a silicon target material as a sputtering source, and introducing silane, nitrogen and hydrogen as process gases;
depositing a second doped crystalline silicon layer by using PVD (physical vapor deposition), wherein mixed phosphine gas is used as a doping source, a silicon target material with the purity of more than 2N is used as a sputtering source, and the process temperature is 150-300 ℃;
and fifthly, depositing the silicon nitride layer and the Si silicon oxynitride layer by adopting PECVD to form laminated second silicon nitride.
After the technical scheme is adopted, the invention has the following positive effects:
the back of the cell is provided with a plurality of groups of film layers, wherein the tunneling oxide layer is isolated from the first doped crystalline silicon layer and the second doped crystalline silicon layer by using the first silicon nitride, so that the first doped crystalline silicon layer can be matched with the ultrathin tunneling oxide layer by using low doping concentration. The second doped crystalline silicon layer is doped with high concentration to reduce the transmission resistance of the polycrystalline silicon. The first silicon nitride protective layer may also provide H-passivation during polysilicon thermal processing, tunneling through dangling bonds of the oxide cross-section. And the second silicon nitride and the dielectric layer compounded on the second silicon nitride form an anti-reflection and anti-reflection structure, so that the current of the battery is improved. Meanwhile, the two films can also be used as slurry barrier layers to prevent slurry from burning through the back passivation structure.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
In the figure: tunneling oxide layer 1, first doped crystalline silicon layer 2, first silicon nitride 3, second doped crystalline silicon layer 4, second silicon nitride 5 and dielectric layer 6.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The TOPCon cell provided by the invention is provided with a tunneling oxide layer 1, a first doped crystalline silicon layer 2, at least one first silicon nitride layer 3, a second doped crystalline silicon layer 4, at least one second silicon nitride layer 5 and a dielectric layer 6 from top to bottom, wherein the thickness of the first doped crystalline silicon layer 2 is 5-40 nm, the first silicon nitride layer 3 is a silicon nitride layer, the second silicon nitride layer 5 is a laminated layer of the silicon nitride layer and a Si silicon oxynitride layer, and the dielectric layer 6 is one of an aluminum oxide antireflection film, a silicon oxynitride antireflection film and a magnesium fluoride antireflection film.
The thickness of the tunneling oxide layer 1 is 0.8-1.2 nm.
The first doped crystalline silicon layer 2 is 20nm, and the activated impurity Concentration is 0.8E + 19-1.2E +20Concentration/cm 3 。
The thickness of the first silicon nitride 3 is 5-20 nm.
The thickness of the first silicon nitride 3 is 10nm.
The thickness of the second doped crystalline silicon layer 4 is 20-80 nm.
The thickness of the second silicon nitride 5 is 60 to 95nm.
The second silicon nitride 5 has a thickness of 75nm.
The dielectric layer 6 is silicon oxynitride with a thickness of 5-20 nm.
A preparation method of a TOPCon battery comprises the following steps:
step one, using a plate type PECVD linear plasma structure, using oxygen as glow gas to grow an oxide layer at 200-300 ℃, and adopting a plasma method to grow a tunneling oxide layer 1; adopting a plasma method to grow a tunneling layer to replace a SiO2 tunneling layer grown by traditional thermal oxidation; the linear plasma process can uniformly grow an oxide layer on the surface of a silicon wafer to realize the uniformity of the ultrathin oxide layer, and the process temperature is low and is similar to the process temperature of the subsequent amorphous silicon deposition, so that the process temperature rise and constant temperature time are reduced, and the large-scale mass production of the silicon-doped tunneling layer deposited by the plasma and the silicon-doped layer in one process is possible.
Depositing a first doped crystalline silicon layer 2 by PVD (physical vapor deposition), taking mixed phosphine gas as a doping source, taking a silicon target with purity of more than 2N as a sputtering source, wherein the process temperature is 150-300 ℃, the power of the first layer of doped crystalline silicon is selected to be 2000-20000W, the lower the power, the better the process effect, and the better the power of the layer is smaller than that of a subsequent film layer;
depositing first silicon nitride 3 by PVD, taking a silicon target material as a sputtering source, and introducing silane, nitrogen and hydrogen as process gases; the first silicon nitride layer 3 prevents the second doped silicon layer 4 from affecting the first doped silicon layer 2 and the tunnel oxide layer 1 during annealing, and provides hydrogen passivation during annealing.
Depositing a second doped crystalline silicon layer 4 by using PVD (physical vapor deposition), wherein mixed phosphine gas is used as a doping source, a silicon target with the purity of more than 2N is used as a sputtering source, and the process temperature is 150-300 ℃; after the above procedures are finished, the silicon wafer is placed in a furnace tube for advancing and retreating to carry out heat treatment, the peak process temperature is recommended to be 840-860 ℃, and the crystallization of the doped crystalline silicon is finished.
And fifthly, depositing a silicon nitride layer and a Si silicon oxynitride layer by adopting PECVD (plasma enhanced chemical vapor deposition) to form a second laminated silicon nitride 5. The preferable growth process of the SiNx-SiONx (silicon nitride layer and Si silicon oxynitride layer) lamination is as follows: depositing a silicon nitride layer and a Si silicon oxynitride layer by PECVD (plasma enhanced chemical vapor deposition) to form a laminated layer, wherein the silicon nitride layer and the Si silicon oxynitride layer are made into a gradual change film or a multilayer film according to the flow ratio of silane/ammonia gas/nitrogen gas/oxygen gas, and the refractive index of each layer is gradually reduced from inside to outside; the second silicon nitride layer may be formed together with silicon oxynitride as a dielectric layer.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A topocon battery, comprising: the anti-reflection silicon nitride film is provided with a tunneling oxide layer (1), a first doped crystalline silicon layer (2), at least one layer of first silicon nitride (3), a second doped crystalline silicon layer (4), at least one layer of second silicon nitride (5) and a dielectric layer (6) from top to bottom, wherein the thickness of the first doped crystalline silicon layer (2) is 5-40 nm, the first silicon nitride (3) is a silicon nitride layer, the second silicon nitride (5) is a laminated layer of the silicon nitride layer and a Si silicon oxynitride layer, and the dielectric layer (6) is one of an aluminum oxide anti-reflection film, a silicon oxynitride anti-reflection film and a magnesium fluoride anti-reflection film.
2. A topocon battery as claimed in claim 1 wherein: the thickness of the tunneling oxide layer (1) is 0.8-1.2 nm.
3. A topocon battery as claimed in claim 1 wherein: the first doped crystalline silicon layer (2) is 20nm, and the activated impurity concentration is 0.8E + 19-1.2E +20Concentration/cm 3 。
4. A topocon battery as claimed in claim 1 wherein: the thickness of the first silicon nitride (3) is 5-20 nm.
5. A TOPCon battery as in claim 4, wherein: the thickness of the first silicon nitride (3) is 10nm.
6. A topocon battery as claimed in claim 1 wherein: the thickness of the second doped crystalline silicon layer (4) is 20-80 nm.
7. A TOPCon battery as in claim 1, wherein: the thickness of the second silicon nitride (5) is 60-95 nm.
8. A TOPCon battery as in claim 7, wherein: the second silicon nitride (5) has a thickness of 75nm.
9. A TOPCon battery as in claim 1, wherein: the dielectric layer (6) is silicon oxynitride with the thickness of 5-20 nm.
10. A method for preparing a TOPCon battery as claimed in any one of claims 1 to 9, comprising the steps of:
step one, using a plate type PECVD linear plasma structure, using oxygen as glow gas to grow an oxide layer at 200-300 ℃, and growing a tunneling oxide layer (1) by using a plasma method;
depositing a first doped crystalline silicon layer (2) by using PVD (physical vapor deposition), taking mixed phosphine gas as a doping source, taking a silicon target material with the purity of more than 2N as a sputtering source, wherein the process temperature is 150-300 ℃, and the power of the first layer of doped crystalline silicon is selected to be 2000-20000W;
depositing first silicon nitride (3) by using PVD (physical vapor deposition), taking a silicon target as a sputtering source, and introducing silane, nitrogen and hydrogen as process gases;
depositing a second doped crystalline silicon layer (4) by using PVD (physical vapor deposition), taking mixed phosphine gas as a doping source, taking a silicon target material with the purity of more than 2N as a sputtering source, and controlling the process temperature to be 150-300 ℃;
and fifthly, depositing a silicon nitride layer and a Si silicon oxynitride layer by adopting PECVD (plasma enhanced chemical vapor deposition) to form a second laminated silicon nitride (5).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7442002B1 (en) | 2023-04-21 | 2024-03-01 | 晶科能源（海▲寧▼）有限公司 | Solar cells and their manufacturing methods, photovoltaic modules |
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| CN112349816A (en) * | 2020-11-19 | 2021-02-09 | 江苏大学 | Preparation method of high-efficiency low-cost N-type TOPCon battery based on PECVD technology |
| CN112951927A (en) * | 2019-12-09 | 2021-06-11 | 苏州阿特斯阳光电力科技有限公司 | Preparation method of solar cell |
| CN113972302A (en) * | 2021-10-26 | 2022-01-25 | 通威太阳能(眉山)有限公司 | TOPCon battery, preparation method thereof and electrical equipment |
| CN114597267A (en) * | 2022-05-07 | 2022-06-07 | 正泰新能科技有限公司 | TOPCon battery and preparation method thereof |
| CN115132852A (en) * | 2022-06-17 | 2022-09-30 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | N-type TOPCon solar cell and manufacturing method thereof |
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- 2022-11-15 CN CN202211430889.8A patent/CN115692533A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112951927A (en) * | 2019-12-09 | 2021-06-11 | 苏州阿特斯阳光电力科技有限公司 | Preparation method of solar cell |
| CN112349816A (en) * | 2020-11-19 | 2021-02-09 | 江苏大学 | Preparation method of high-efficiency low-cost N-type TOPCon battery based on PECVD technology |
| CN113972302A (en) * | 2021-10-26 | 2022-01-25 | 通威太阳能(眉山)有限公司 | TOPCon battery, preparation method thereof and electrical equipment |
| CN114597267A (en) * | 2022-05-07 | 2022-06-07 | 正泰新能科技有限公司 | TOPCon battery and preparation method thereof |
| CN115132852A (en) * | 2022-06-17 | 2022-09-30 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | N-type TOPCon solar cell and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7442002B1 (en) | 2023-04-21 | 2024-03-01 | 晶科能源（海▲寧▼）有限公司 | Solar cells and their manufacturing methods, photovoltaic modules |
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