CN115691384A - Display panel and display device - Google Patents
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- CN115691384A CN115691384A CN202211296494.3A CN202211296494A CN115691384A CN 115691384 A CN115691384 A CN 115691384A CN 202211296494 A CN202211296494 A CN 202211296494A CN 115691384 A CN115691384 A CN 115691384A
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Abstract
The invention discloses a display panel and a display device.A first display area in the display panel comprises a first data line, the first data line is connected with first sub-pixels, a second display area comprises a second data line, the second data line is connected with second sub-pixels, and the set number of the first sub-pixels is less than that of the second sub-pixels; the non-display area is provided with a driving signal adjusting unit, the first driving signal adjusting unit is electrically connected with the first data line, the second driving signal adjusting unit is electrically connected with the second data line, the number of the first data lines electrically connected with the first driving signal adjusting unit is larger than that of the second data lines electrically connected with the second driving signal adjusting unit, so that the number of the data lines respectively connected with the first driving signal adjusting unit in the first display area and the second driving signal adjusting unit in the second display area is different, the occupied area of the driving signal adjusting unit is reduced, and the frame is reduced.
Description
Technical Field
The invention relates to the technical field of display panels, in particular to a display panel and a display device.
Background
With the rapid development of display technology, in addition to the traditional functions of information display, the shape of the display is gradually improved in order to better adapt to the overall structure and the use requirements of the environment, and accordingly, a special-shaped display is generated. Because peripheral circuits and wires of different display areas exist, a frame with a certain width inevitably exists on the periphery of the display areas, but the design of the narrow frame is particularly important for the display requirements of a special-shaped display, so that the screen occupation ratio of the screen is improved to a certain extent.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for reducing the frame width of the display panel.
In a first aspect, the present invention provides a display panel, comprising a display area and a non-display area located at one side of the display area;
the display area comprises a first display area and a second display area, the first display area comprises at least one first data line, the first data line is connected with at least one first sub-pixel, the second display area comprises at least one second data line, the second data line is connected with at least one second sub-pixel, and the set number of the first sub-pixels is smaller than that of the second sub-pixels;
the non-display area is provided with a driving signal adjusting unit, the driving signal adjusting unit at least comprises a first driving signal adjusting unit and a second driving signal adjusting unit, the first driving signal adjusting unit is electrically connected with the first data line, the second driving signal adjusting unit is electrically connected with the second data line, and the number of the first data lines electrically connected with the first driving signal adjusting unit is larger than the number of the second data lines electrically connected with the second driving signal adjusting unit.
In a second aspect, the present invention provides a display device comprising the display panel of any one of the first aspects.
The technical scheme of the embodiment of the invention is that the display panel comprises a display area and a non-display area positioned on one side of the display area; the display area comprises a first display area and a second display area, the first display area comprises at least one first data line, and the number of first sub-pixels connected to the first data line is smaller than the number of second sub-pixels connected to the second data line; the non-display area is provided with a driving signal adjusting unit, the driving signal adjusting unit at least comprises a first driving signal adjusting unit and a second driving signal adjusting unit, the first driving signal adjusting unit is electrically connected with the first data line, and the second driving signal adjusting unit is electrically connected with the second data line, so that the number of the first data lines electrically connected with the first driving signal adjusting unit in the first display area is larger than the number of the second data lines electrically connected with the second driving signal adjusting unit in the second display area, the occupied area of the driving signal adjusting unit is reduced, and the narrow frame design of the display panel is realized.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a non-display area according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another non-display area according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another non-display area according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention
Fig. 8 is a timing diagram of driving a display panel according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 11 is a timing diagram illustrating a driving sequence of another display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 1 and fig. 2, a display panel 100 includes a display area 101 and a non-display area 102 located on one side of the display area 101; the display area comprises a first display area 103 and a second display area 104, the first display area 103 comprises at least one first data line 105, the first data line 105 is connected with at least one first sub-pixel 106, the second display area 104 comprises at least one second data line 107, the second data line 107 is connected with at least one second sub-pixel 108, and the set number of the first sub-pixels 106 is smaller than that of the second sub-pixels 108; the non-display area 102 is provided with a driving signal adjusting unit 109, the driving signal adjusting unit 109 at least includes a first driving signal adjusting unit 1091 and a second driving signal adjusting unit 1092, the first driving signal adjusting unit 1091 is electrically connected to the first data lines 105, the second driving signal adjusting unit 1092 is electrically connected to the second data lines 107, and the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 is greater than the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092.
The display panel 100 includes a display area 101 and a non-display area 102, the display area 101 may have a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels arranged in an array, the non-display area 102 may have a driving chip, a gate driving circuit, a source driving circuit, a demultiplexing circuit, a timing control circuit, and the like, and the normal display effect of the display panel 100 is further achieved through the mutual cooperation between the parts in the display area 101 and the non-display area 102. The display area 101 includes a first display area 103 and a second display area 104, the first display area 103 includes a plurality of first data lines 105, the second display area 104 includes a plurality of second data lines 107, since the first display area 103 belongs to a special-shaped display area, there are a plurality of first data lines 105 with different lengths, and the length of the first data lines 105 is smaller than that of the second data lines 107, so that the number of first sub-pixels 106 connected to the first data lines 105 is smaller than that of second sub-pixels 108 connected to the second data lines 107, in the prior art, due to the presence of the special-shaped first display area 103, the occupied area of fan-out corresponding to the first data lines 105 in the first display area 103 is increased, and thus the occupied area of the non-display area 102 is increased, which is not favorable for the narrow frame design of the display panel 100, therefore, considering that the number of sub-pixels connected to the first data lines 105 and the second data lines 107 is different, in order to ensure the overall display effect of the display panel 100, a driving signal adjusting unit 109 is disposed in the non-display area 102, and the number of the driving signal adjusting units 109 including the first data lines 105 connected to the first data lines 107 is smaller than the second data lines 1092, and the second data lines 1092 connected to the first data lines 107; the number of the first sub-pixels 106 connected to the second data line 107 is large, and the load is large; the number of the first data lines 105 electrically connected with the first driving signal adjusting unit 1091 is controlled to be greater than the number of the second data lines 107 electrically connected with the second driving signal adjusting unit 1092, the display difference between the first display area 103 and the second display area 104 is balanced, and meanwhile, the number of the branches of the driving signal adjusting unit 109 is reasonably set, so that the data lines are connected with the fan-out wires through the driving signal adjusting unit 109, because the number of the first data lines 105 connected with the first driving signal adjusting unit 1091 in the first display area 103 is greater, the number of the fan-out wires corresponding to the moment is smaller, the normal display effect of the first display area 103 is ensured, meanwhile, the occupied area of the fan-out wires in the non-display area 102 is reduced, and the requirement of the narrow frame of the display panel 100 is met.
According to the embodiment of the invention, the first driving signal adjusting unit correspondingly connected with the first data line in the first display area and the second driving signal adjusting unit correspondingly connected with the second data line in the second display area are arranged, so that the number of the first data lines electrically connected with the first driving signal adjusting unit is controlled to be larger than the number of the second data lines electrically connected with the second driving signal adjusting unit, the fan-out area of the corresponding fan-out wiring in the first display area is reduced, the occupied area of the non-display area is further reduced, and the narrow frame design of the display panel is realized.
Optionally, with continued reference to fig. 2, the driving signal adjusting unit 109 is a multiplexing circuit 110, the multiplexing circuit 110 includes a first multiplexing circuit 1101 and a second multiplexing circuit 1102, the first driving signal adjusting unit 1091 is the first multiplexing circuit 1101, the second driving signal adjusting unit 1092 is the second multiplexing circuit 1102, the first multiplexing circuit 1101 includes a plurality of first output terminals 111, the second multiplexing circuit 1102 includes a plurality of second output terminals 112, the first output terminals 111 are electrically connected to the first data lines 105, and the second output terminals 112 are electrically connected to the second data lines 107; the set number of the first output terminals 111 is larger than the set number of the second output terminals 112.
The driving signal adjusting unit 109 is a multiplexing circuit 110, that is, a demultiplexing circuit, and decomposes the total data signal output by the driving chip into a plurality of data signals, and transmits the data signals to a plurality of corresponding data lines. The first driving signal adjusting unit 1091 is a first multiplexing circuit 1101, the first multiplexing circuit 1101 is provided with a plurality of first output ends 111, and the first output ends 111 are electrically connected to the first data lines 105 respectively and used for transmitting data signals to the first data lines 105; the second driving signal adjusting unit 1092 is a second multiplexing circuit 1102, the second multiplexing circuit 1102 is provided with a plurality of second output ends 112, and the second output ends 112 are respectively and electrically connected to the second data lines 107, and are used for transmitting data signals to the second data lines 107; because the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 is greater than the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092, that is, the number of the corresponding first output ends 111 is greater than the number of the second output ends 112, for example, as shown in fig. 2, three first output ends 111 are provided, and two second output ends 112 are provided, through the arrangement of the first multiplexing circuit 1101 and the second multiplexing circuit 1102, the occupied area of the fan-out traces in the non-display area 102 is reduced, and further, the narrow frame design of the display panel 100 is favorably realized.
Optionally, fig. 3 is a schematic structural diagram of a non-display area according to an embodiment of the present invention, as shown in fig. 3, the non-display area 102 includes a timing control unit 113, the first multiplexing circuit 1101 includes at least one first gate control terminal 114, the second multiplexing circuit 1102 includes at least one second gate control terminal 115, and the timing control unit 113 is electrically connected to the first gate control terminal 114 and the second gate control terminal 115, respectively.
The timing control unit 113 is disposed in the non-display area 102, since the first multiplexing circuit 1101 is connected to the plurality of first data lines 105, the second multiplexing circuit 1102 is connected to the plurality of second data lines 107, in order to ensure normal display of the first display area 103 and the second display area 104 in the display panel 100, the plurality of first output terminals 111 in the first multiplexing circuit 1101 and the plurality of second output terminals 112 in the second multiplexing circuit 1102 are controlled to be conducted in a time-sharing manner, the first multiplexing circuit 1101 is disposed, the first gating control terminal 114 is disposed, the second multiplexing circuit 1102 is disposed, the second gating control terminal 115 is disposed, the timing control unit 113 is electrically connected to the first gating control terminal 114 and the second gating control terminal 115, the timing control unit 113 controls the first gating control terminal 114 in the first multiplexing circuit 1101 to be conducted in a time-sharing manner, the data signals are further influenced to be transmitted to the first data lines 105 in a time-sharing manner, the display effect of the first display area 103 and the second gating control terminal 115 in the second multiplexing circuit 1102 are ensured to be conducted in a time-sharing manner, and the display effect of the second data signals 107 in the second multiplexing circuit 104 is ensured.
Optionally, with continued reference to fig. 3, the timing control unit 113 includes at least one first timing control line 1131 and at least one second timing control line 1132; the set number of the first timing control lines 1131 is larger than the set number of the second timing control lines 1132; the set number of the first gate control terminals 114 is the same as the set number of the first timing control lines 1131, and the set number of the second gate control terminals 115 is the same as the set number of the second timing control lines 1132; the first gate control terminal 114 is electrically connected to the first timing control line 1131; the second gate control terminal 115 is electrically connected to the second timing control line 1132.
The timing control unit 113 is provided with a first timing control line 1131, the first timing control line 1131 is electrically connected to the first gating control end 114, the set number of the first gating control ends 114 is the same as the set number of the first timing control line 1131, and the timing control signal output by the first timing control line 1131 controls the on or off of the first gating control end 114, thereby affecting the transmission of the data signal on the first data line 105; the timing control unit 113 is further provided with a second timing control line 1132, the second timing control line 1132 is electrically connected to the second gate control end 115, the set number of the second gate control ends 115 is the same as the set number of the second timing control line 1132, and the timing control signal output by the second timing control line 1132 controls the on or off of the second gate control end 115, thereby affecting the data signal transmission on the second data line 107; the number of the first timing control lines 1131 is greater than the number of the second timing control lines 1132, so that the number of the first data lines 105 controlled by the first timing control lines 1131 is greater than the number of the second data lines 107 controlled by the second timing control lines 1132, the time for transmitting data signals in the data lines is controlled in a time-sharing manner through the timing control lines, different gating control ends of the same multiplexing circuit 110 connected by different timing control lines are ensured, the data lines correspondingly connected are further controlled to receive the data signals, and the display effect of the display panel 100 is ensured.
Optionally, fig. 4 is a schematic structural diagram of another non-display area provided in the embodiment of the present invention, fig. 5 is a schematic structural diagram of another non-display area provided in the embodiment of the present invention, the non-display area 102 further includes a driving unit 116, the driving unit 116 includes a first driving signal line 1161 and a second driving signal line 1162, the first driving signal line 1161 is connected to the first data line 105 through a first multiplexing circuit 1101, and the second driving signal line 1162 is connected to the second data line 107 through a second multiplexing circuit 1102.
The driving unit 116 may be a driving chip and may be configured to output a data signal transmitted to a data line, the first driving signal line 1161 and the second driving signal line 1162 may be fan-out traces, fig. 4 is a schematic structural diagram of a part of the non-display area 102 corresponding to the first display area 103, fig. 5 is a schematic structural diagram of a part of the non-display area 102 corresponding to the second display area 104, the first display area 103 is correspondingly disposed on the first driving signal line 1161, the second display area 104 is correspondingly disposed on the second driving signal line 1162, and the first driving signal line 1161 is connected to the first data line 105 through a first multiplexing circuit 1101 and is configured to transmit a data signal to the first data line 105 in the first display area 103, so that the data signal in the first data line 105 is normally transmitted to each first sub-pixel 106; the second driving signal line 1162 is connected to the second data line 107 through the second multiplexing circuit 1102 and is used for transmitting data signals to the second data line 107 in the second display region 104, so that the data signals in the second data line 107 are normally transmitted to each of the second sub-pixels 108; one driving signal line can be electrically connected with a plurality of data lines, so that the number of the driving signal lines in the non-display area 102 is reduced, the occupied area of the non-display area 102 is reduced, and the narrow frame design of the display panel 100 is facilitated.
Optionally, fig. 6 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, fig. 7 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and fig. 8 is a timing diagram of driving a display panel provided in the embodiment of the present invention, as shown in fig. 6, fig. 7 and fig. 8, the first multiplexing circuit 1101 at least includes a first thin film transistor 117, and the second multiplexing circuit 1102 at least includes a second thin film transistor 118; a first terminal of the first thin film transistor 117 is a first output terminal 111, a second terminal of the first thin film transistor 117 is a first gate control terminal 114, and a third terminal of the first thin film transistor 117 is electrically connected to the first driving signal line 1161; the first terminal of the second thin film transistor 118 is the second output terminal 112, the second terminal of the second thin film transistor 118 is the second gate control terminal 115, and the third terminal of the second thin film transistor 118 is electrically connected to the second driving signal line 1162.
The multiplexing circuits 110 realize normal transmission or interruption of data signals by arranging thin film transistors, and because the first display area 103 is a special-shaped display area, the number of first data lines 105 electrically connected with the same first multiplexing circuit 1101 is more than that of second data lines 107 electrically connected with the same second multiplexing circuit 1102, so as to ensure that each data line performs column-by-column data signal transmission, the number of first thin film transistors 117 arranged in the same first multiplexing circuit 1101 is more than that of second thin film transistors 118 arranged in the same second multiplexing circuit 1102; a plurality of first thin film transistors 117 are disposed in the corresponding first multiplexing circuit 1101, first ends of the first thin film transistors 117 are electrically connected to the first data lines 105 in a one-to-one correspondence, second ends of the first thin film transistors 117 are electrically connected to the first timing control line 1131 in a one-to-one correspondence, and third ends of the first thin film transistors 117 are electrically connected to the first driving signal line 1161 in the driving unit 116 at the same time, for example, the first thin film transistors 117 and the second thin film transistors 118 are both N-type thin film transistors (NMOS), when a second end of one first thin film transistor 117 receives a conducting high level signal output by the first timing control line 1131, a path is formed between the first end and the third end of the first thin film transistor 117, and at this time, a data signal is transmitted on the first data line 105 connected to the first end of the first thin film transistor 117, and then the data signal is written into the first sub-pixel 106 electrically connected to the first data line 105, thereby achieving a display effect of the first display area 103. A plurality of second thin film transistors 118 are disposed in the corresponding second multiplexing circuit 1102, a first end of each second thin film transistor 118 is electrically connected to the second data line 107 in a one-to-one correspondence manner, a second end of each second thin film transistor 118 is electrically connected to the second timing control line 1132 in a one-to-one correspondence manner, a third end of each second thin film transistor 118 is electrically connected to the second driving signal line 1162 in the driving unit 116, when the second end of a certain second thin film transistor 118 receives the on high level signal output by the second timing control line 1132, a path is formed between the first end and the third end of the second thin film transistor 118, and at this time, the second data line 107 connected to the first end of the second thin film transistor 118 performs data signal transmission, and then writes the data signal into the second sub-pixel 108 electrically connected to the second data line 107, thereby achieving the display effect of the second display region 104. The types of the first thin film transistor 117 and the second thin film transistor 118 may be the same or different, and may be selected according to actual design requirements, and the embodiment of the present invention is not limited in particular.
Optionally, fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention, fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 11 is a timing diagram of driving of another display panel according to an embodiment of the present invention, as shown in fig. 6, fig. 7, fig. 8, fig. 9, fig. 10, and fig. 11, the first thin film transistor 117 and the second thin film transistor 118 are at least one of an N-type thin film transistor and a P-type thin film transistor.
The first thin film transistor 117 and the second thin film transistor 118 function as switches, and further affect the transmission effect of the driving signal output by the driving unit 116, and the first thin film transistor 117 and the second thin film transistor 118 may be N-type thin film transistors (NMOS) and are turned on when receiving a high level signal and turned off when receiving a low level signal; or the first thin film transistor 117 and the second thin film transistor 118 may be P-type thin film transistors (PMOS), which are turned on when receiving a low level signal, and turned off when receiving a high level signal, the first thin film transistor 117 and the second thin film transistor 118 are illustrated as N-type thin film transistors in fig. 6, 7, and 8, the first thin film transistor 117 and the second thin film transistor 118 are illustrated as P-type thin film transistors in fig. 9, 10, and 11, and the type selection in the first thin film transistor 117 and the second thin film transistor 118 may be selected according to actual design requirements, which is not limited in the embodiment of the present invention.
Optionally, with continued reference to fig. 6, 7, 8, 9, 10, and 11, the signal timings of the first timing control signal CK1 output by the first timing control line 1131 and the second timing control signal CK2 output by the second timing control line 1132 are different, and the on time of the on level of the first timing control signal CK1 is shorter than the on time of the on level of the second timing control signal CK 2.
Since the first timing control line 1131 is connected to the first data line 105 on which the first sub-pixel 106 is mounted, the second timing control line 1132 is connected to the second data line 107 on which the second sub-pixel 108 is mounted, and since the number of sub-pixels mounted on different data lines is different, in order to ensure that the lighting effects of the sub-pixels in different display regions 101 are consistent, the time for receiving the data signal by the data line with the larger number of mounted sub-pixels can be correspondingly increased, that is, the on time of the on level of the timing signal line output timing control signal is increased, since the number of the first sub-pixels 106 on the first data line 105 is smaller than the number of the second sub-pixels 108 on the second data line 107, the first data line 105 is connected to the first timing control line 1131, the second data line 107 is connected to the second timing control line 1132, the on time CK of the on level of the first timing control signal CK1 is controlled to be smaller than the on time of the on level of the second timing control signal CK2, and the difference between the first data line 105 and the second sub-pixel 108 is reduced, thereby ensuring that the overall display panel 100 has the display effect.
Alternatively, with continued reference to fig. 6, 7, 8, 9, 10, and 11, the on times of the on levels of each of the first timing control signals CK1 do not overlap, and the on times of the on levels of each of the second timing control signals CK2 do not overlap.
Different data lines are correspondingly connected with different timing signal lines, the first data lines 105 correspond to the first timing control lines 1131 one by one, the second data lines 107 correspond to the second timing control lines 1132 one by one, the first data lines 105 in the first display area 103 receive the first timing control signals CK1 output by the first timing control lines 1131, and the turn-on time of the turn-on level of each first timing control signal CK1 is controlled not to be overlapped, illustratively, three first timing control lines 1131 are provided, and the first timing control lines 1131 are controlled to be sequentially turned on and respectively output the first timing control signals CK1-1, CK1-2 and CK1-3, so that the first data lines 105 connected with the first timing control lines 1131 sequentially provide the data signals to the first sub-pixels 106, thereby realizing the display of the first display area 103; the second data line 107 in the second display area 104 receives the second timing control signal CK2 output by the second timing control line 1132, and controls the on time of the on level of each second timing control signal CK2 not to overlap, for example, six second timing control lines 1132 are provided, and the second timing control lines 1132 are sequentially conducted and respectively output the second timing control signals CK2-1, CK2-2, CK2-3, CK2-4, CK2-5, and CK2-6, so that the second data line 107 connected to the second timing control lines 1132 sequentially provides the data signals to the second sub-pixel 108, thereby realizing the display of the second display area 104, and the normal display effect of the display panel 100 is ensured by performing time-sharing conduction without overlapping of the on times of the on levels of the timing control signals.
Optionally, with continued reference to fig. 6, 7, 8, 9, 10, and 11, the first timing control signal CK1 output by the first timing control line 1131 and the second timing control signal CK2 output by the second timing control line 1132 are within the same timing cycle CKV.
In order to ensure the display uniformity of the first display region 103 and the second display region 104, the first timing control line 1131 of the first display region 103 and the second timing control line 1132 of the second display region 104 can be controlled to respectively provide a data signal to the first subpixel 106 connected to the first data line 105 in the first display region 103 and a data signal to the second subpixel 108 connected to the second data line 107 in the second display region 104 in the same timing cycle CKV, so as to ensure that the first subpixel 106 in the first display region 103 and the second subpixel 108 in the second display region 104 complete a display in the same timing cycle, thereby ensuring the overall display effect of the display panel.
Alternatively, with continued reference to fig. 1, 2, and 3, the first multiplexing circuits 1101 are disposed in a stair-like arrangement in the non-display area 102.
In order to reduce the occupied area of the non-display area 102 and further realize the narrow frame of the display panel 100, the first multiplexing circuit 1101 may be arranged in a step shape, and meanwhile, each metal wire in the first multiplexing circuit 1101 may also extend in a step shape, so that the space of the first display area 103 in the abnormal shape is reasonably utilized, the frame of the display panel 100 is reduced, and the screen occupation ratio is improved.
Optionally, with continued reference to fig. 2 and 3, the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 is N times the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092, where N is a positive integer greater than or equal to 2.
As the number of the first sub-pixels 106 mounted on the first data lines 105 is smaller than the number of the second sub-pixels 108 mounted on the second data lines 107, in order to ensure the narrow frame design requirement of the display panel 100 and the display effect of the display panel 100, the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 may be controlled to be larger than the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092, for example, as shown in fig. 3, when the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 is 2 times larger than the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092, the number of the first data lines 105 electrically connected to the first driving signal adjusting unit 1091 is 6, the number of the second data lines 107 electrically connected to the second driving signal adjusting unit 1092 is 3, and when compared with the prior art, the width of the routing lines of the driving signal adjusting unit 109 in the display panel 100 is L, the width of the driving signal adjusting unit 1092 is 3, and the number of the second data lines 107 electrically connected to the first data lines is not limited by the specific design requirement of the first data lines 1091 and the second data lines 1092.
Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 12, the display device 200 includes the display panel 100 according to the embodiment.
It should be noted that, since the display device provided in the present embodiment has the same or corresponding advantages of the display panel 100 of the foregoing embodiment, no further description is provided herein. The display device 200 provided in the embodiment of the present invention may be a mobile phone shown in fig. 12, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A display panel is characterized by comprising a display area and a non-display area positioned on one side of the display area;
the display area comprises a first display area and a second display area, the first display area comprises at least one first data line, the first data line is connected with at least one first sub-pixel, the second display area comprises at least one second data line, the second data line is connected with at least one second sub-pixel, and the set number of the first sub-pixels is smaller than that of the second sub-pixels;
the non-display area is provided with a driving signal adjusting unit, the driving signal adjusting unit at least comprises a first driving signal adjusting unit and a second driving signal adjusting unit, the first driving signal adjusting unit is electrically connected with the first data lines, the second driving signal adjusting unit is electrically connected with the second data lines, and the number of the first data lines electrically connected with the first driving signal adjusting unit is larger than the number of the second data lines electrically connected with the second driving signal adjusting unit.
2. The display panel according to claim 1,
the driving signal adjusting unit is a multiplexing circuit, the multiplexing circuit includes a first multiplexing circuit and a second multiplexing circuit, the first driving signal adjusting unit is the first multiplexing circuit, the second driving signal adjusting unit is the second multiplexing circuit, the first multiplexing circuit includes a plurality of first output ends, the second multiplexing circuit includes a plurality of second output ends,
the first output end is electrically connected with the first data line, and the second output end is electrically connected with the second data line;
the set number of the first output ends is greater than the set number of the second output ends.
3. The display panel according to claim 2, wherein the non-display area includes a timing control unit, the first multiplexing circuit includes at least one first gate control terminal, the second multiplexing circuit includes at least one second gate control terminal, and the timing control unit is electrically connected to the first gate control terminal and the second gate control terminal, respectively.
4. The display panel according to claim 3, wherein the timing control unit comprises at least one first timing control line and at least one second timing control line; the set number of the first timing control lines is greater than the set number of the second timing control lines;
the set number of the first gating control ends is the same as that of the first timing control lines, and the set number of the second gating control ends is the same as that of the second timing control lines;
the first gating control end is electrically connected with the first timing control line; the second gating control end is electrically connected with the second timing control line.
5. The display panel according to claim 3, wherein the non-display region further comprises a driving unit, the driving unit comprising a first driving signal line and a second driving signal line, the first driving signal line being connected to the first data line via the first multiplexing circuit, the second driving signal line being connected to the second data line via the second multiplexing circuit.
6. The display panel according to claim 5, wherein the first multiplexing circuit includes at least a first thin film transistor, and wherein the second multiplexing circuit includes at least a second thin film transistor;
the first end of the first thin film transistor is the first output end, the second end of the first thin film transistor is the first gating control end, and the third end of the first thin film transistor is electrically connected with a first driving signal line;
the first end of the second thin film transistor is a second output end, the second end of the second thin film transistor is a second gating control end, and the third end of the second thin film transistor is electrically connected with a second driving signal line.
7. The display panel according to claim 6, wherein the first thin film transistor and the second thin film transistor are at least one of an N-type thin film transistor or a P-type thin film transistor.
8. The display panel according to claim 4, wherein a signal timing of a first timing control signal output by the first timing control line and a signal timing of a second timing control signal output by the second timing control line are different, and an on time of an on level of the first timing control signal is shorter than an on time of an on level of the second timing control signal.
9. The display panel according to claim 8, wherein the turn-on time of the turn-on level of each of the first timing control signals does not overlap, and the turn-on time of the turn-on level of each of the second timing control signals does not overlap.
10. The display panel according to claim 8, wherein a first timing control signal output by the first timing control line and a second timing control signal output by the second timing control line are in a same timing cycle.
11. The display panel according to claim 2, wherein the first multiplexing circuits are disposed in the non-display region in a step-like arrangement.
12. The display panel according to claim 2, wherein the number of the first data lines to which the first driving signal adjusting unit is electrically connected is N times the number of the second data lines to which the second driving signal adjusting unit is electrically connected, wherein N is a positive integer greater than or equal to 2.
13. A display device, comprising: the display panel of any one of claims 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211296494.3A CN115691384A (en) | 2022-10-21 | 2022-10-21 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211296494.3A CN115691384A (en) | 2022-10-21 | 2022-10-21 | Display panel and display device |
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| CN115691384A true CN115691384A (en) | 2023-02-03 |
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| CN202211296494.3A Pending CN115691384A (en) | 2022-10-21 | 2022-10-21 | Display panel and display device |
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