KR20210077209A - Foldable display device - Google Patents

Abstract

The present invention provides a foldable display device comprising: a display panel including a plurality of display areas separated by folding lines; a plurality of data integrated circuits outputting data voltages to the display area; and a mux circuit for selectively applying the data voltages output from the plurality of data integrated circuits to the plurality of display areas. According to the present invention, the boundary between the display areas may be minimized.

Description

FOLDABLE DISPLAY DEVICE

The present invention relates to a foldable display device, and to a foldable display device capable of being divided and driven into a plurality of display areas.

Display devices used for computer monitors, TVs, mobile phones, etc. include an electroluminescence display device that emits light by itself, and a liquid crystal display (LCD) that requires a separate light source.

A display device is being applied to a personal portable device as well as a computer monitor and TV, and research on a display device having a large display area and reduced volume and weight is being conducted.

Recently, a foldable display device that can be freely folded and unfolded by forming a display unit and wiring on a flexible substrate is attracting attention as a next-generation display device.

A foldable display device includes a display panel having flexibility to be foldable and a plurality of data integrated circuits (D-ICs) for driving the display panel. When the foldable display device is folded, a plurality of display areas may be divided by folding, and the plurality of divided display areas may be respectively driven by different data integrated circuits. However, when a plurality of divided display areas as a whole outputs one image, a problem arises in that a certain boundary is recognized at the boundary between the divided display areas.

Accordingly, the inventors of the present invention have recognized the need for a structure and method capable of eliminating boundaries between display areas in a foldable display device.

Accordingly, the inventors of the present invention have invented a foldable display that does not create a boundary between display areas separated by a folding line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a foldable display capable of minimizing a difference in luminance at a boundary between separated display areas.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A foldable display according to an embodiment of the present invention includes a display panel including a plurality of display regions separated by a folding line, and a data voltage applied to the display region. A boundary between the display areas may be minimized by including a plurality of data integrated circuits outputting the plurality of data integrated circuits and a MUX circuit selectively applying data voltages output from the plurality of data integrated circuits to the plurality of display areas.

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, a data voltage output from the first data integrated circuit is output to a second folding region intersecting it, and a data voltage output from the second data integrated circuit is output to a first folding region intersecting the same, thereby generating a folding line. It is possible to alleviate the boundary lines that may occur in the surroundings.

In addition, the present invention improves the display quality of the image so that the boundary line is not recognized in the unfolded state, so that one image can be perfectly implemented.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a view for explaining a foldable display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a MUX circuit of a foldable display device according to an exemplary embodiment of the present invention.
3A is a circuit diagram for explaining driving of a MUX circuit when a foldable display device according to an exemplary embodiment is in a folded state.
3B is a circuit diagram for explaining driving of a MUX circuit when the foldable display device according to an exemplary embodiment is in an unfolded state.
4 is a circuit diagram illustrating a MUX circuit of a foldable display device according to another exemplary embodiment of the present invention.
5A is a circuit diagram for explaining driving of a MUX circuit when a foldable display device according to another exemplary embodiment is in a folded state.
5B to 5D are circuit diagrams for explaining driving of a MUX circuit when a foldable display device according to another exemplary embodiment is in an unfolded state.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'include', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, the present invention will be described with reference to the drawings.

1 is a view for explaining a foldable display device according to an embodiment of the present invention.

Referring to FIG. 1 , a foldable display 100 according to an exemplary embodiment of the present specification includes a display panel 110 , a gate driving circuit 120 , a data integrated circuit 130 , a printed circuit board 140 , and a MUX. circuit 150 .

In the display panel 110 , the display panel 110 includes a display area AA that is folded by a folding line FL and a non-display area NA surrounding the display area AA.

In addition, the display area AA may be folded by the folding line FL. Accordingly, the display area may be divided into a first display area AA1 and a second display area AA2 divided by the folding line FL. That is, the boundary between the first display area AA1 and the second display area AA2 may correspond to the folding line FL.

In addition, the display area AA extends to both sides of the folding areas FA1 and FA2 and the folding areas FA1 and FA2 that are folded to a specific radius of curvature when folded, and the non-folding areas NFA1 and NFA2 maintain a flat state. ) can be distinguished. That is, the non-folding areas NFA1 and NFA2 may be defined with the folding areas FA1 and FA2 interposed therebetween.

Specifically, as shown in FIG. 1 , the first display area AA1 extends to one side of the first folding area FA1 and the first folding area FA1 that are folded to a specific radius of curvature to maintain a flat state. It may be divided into a first non-folding area NFA1. In addition, the second display area AA2 extends to the other side of the second folding area FA2 and the second folding area FA2 that are folded with a specific radius of curvature, and the second non-folding area NFA2 maintains a flat state. can be divided into

Meanwhile, in FIG. 1 , the first display area AA1 and the second display area AA2 have the same size, but the size of the first display area AA1 and the second display area AA2 is not limited thereto. It may be configured differently according to need.

In the display area AA, a plurality of gate lines GL and a plurality of data lines NFDL and FDL that are intersected in a matrix form are disposed. In addition, a plurality of pixels PX may be defined by a plurality of gate lines GL and data lines NFDL and FDL. Each of the plurality of pixels PX includes at least one thin film transistor.

In addition, the above-described data lines NFDL and FDL include the folding data line FDL connected to the first folding area FA1 and the second folding area FA2, and the first non-folding area NFA1 and the second non-folding area. It may be divided into a non-folding data line NFDL connected to the area NFA2.

In addition, when the foldable display 100 according to the exemplary embodiment of the present specification is an organic light emitting diode display, current is applied to the organic light emitting diodes provided in the plurality of pixels PX to combine the emitted electrons and holes excitons are created by Then, the exciton emits light to realize the grayscale of the organic light emitting diode display.

In this regard, the foldable display device 100 according to an exemplary embodiment of the present specification is not limited to an organic light emitting display device, and may be a display device of various types such as a liquid crystal display device.

Although not shown, touch electrodes for sensing a touch may be disposed on or inside the display panel 110 in a matrix form according to design needs. Accordingly, the foldable display device according to an embodiment of the present invention may sense a touch applied to the display panel 110 using a touch electrode.

The above-described touch sensing of the foldable display 100 is a self-capacitive method of detecting the self-capacitance of the touch electrode or a change in the mutual capacitance of the receiving touch electrode and the transmitting touch electrode. Through , it may be based on a mutual-capacitive method of sensing a touch.

The gate driving circuit 120 sequentially supplies a gate voltage to the gate line GL.

The gate driving circuit 120 may be positioned on only one side of the display panel 110 or on both sides of the display panel 110 according to a driving method. In addition, the gate driving circuit 120 may be implemented as a GIP (Gate In Panel) type and integrated in the display panel 110 .

Specifically, in FIG. 1 , the gate driving circuit 120 may be disposed on both sides of the display area AA in the X-axis direction on the display panel 110 and may extend in the Y-axis direction. In other words, since the folding line FL extends in the Y-axis direction, the gate driving circuit 120 may extend in a direction parallel to the folding line FL. However, the folding line FL only needs to be parallel to the gate driving circuit 120 , and the position thereof is not limited to the center.

Meanwhile, the gate driving circuit 120 may include a shift register, a level shifter, and the like.

Referring to FIG. 1 , the data integrated circuit 130 supplies a data voltage to a plurality of pixels disposed in a display area through data lines NFDL and FDL.

And. The data integrated circuit 130 may include a first data integrated circuit 131 and a second data integrated circuit 132 for driving the first display area AA1 and the second display area AA2 .

Specifically, the first data integrated circuit 131 outputs a data voltage to the first non-folding area NFA1 through the non-folding data line NFDL, and connects the connection line CL and the folding data line FDL to the first non-folding area NFA1. Through this, the data voltage is selectively output to the first folding area FA1 and the second folding area FA2. In addition, the second data integrated circuit 132 outputs a data voltage to the second non-folding area NFA2 through the non-folding data line NFDL, and through the connection line CL and the folding data line FDL. , selectively output the data voltage to the first folding area FA1 and the second folding area FA2 .

The data integrated circuit 130 may be disposed on one side or both sides of the display panel 110 with respect to the Y-axis direction, and may extend in the X-axis direction. In other words, since the folding line FL extends in the Y-axis direction, the data integrated circuit 130 may extend in a direction perpendicular to the folding line FL.

However, in FIG. 1 , only the data integrated circuit 130 is divided into the first data integrated circuit 131 and the second data integrated circuit 132 , that is, divided into two. may be separated into a plurality of two or more.

In addition, each of the first data integrated circuit 131 and each of the second data integrated circuit 132 may include a timing controller, a data driver, and a power supply. Specifically, the first data integrated circuit 131 includes a first timing controller, a first data driver, and a first power supply, and the second data integrated circuit 132 includes a second timing controller, a second data driver, and a second power supply. Includes 2 power supply.

The timing controller generates image data by converting an image signal applied to an external host system according to a data signal format that can be processed by the data driver based on the timing signal.

To this end, the timing controller receives various timing signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable (DE) signal, and a reference clock signal (CLK) together with the image signal. Receive from an external host system.

The timing controller supplies a data control signal to the data driver, a gate control signal to the gate driving circuit 120 , and supplies a power control signal to the power supply.

Specifically, the timing controller includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), and the like to control the data driver. and outputs various data control signals (DCS).

Here, the source start pulse controls the data sampling start timing of one or more data circuits constituting the data driver. The source sampling clock is a clock signal that controls the sampling timing of data in each data circuit. The source output enable signal controls the output timing of the data driver.

In addition, the timing controller controls the gate driving circuit 120 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output Enable; GOE). Various gate control signals (GCS) including, etc. are output.

Here, the gate start pulse controls the operation start timing of one or more gate circuits constituting the gate driving circuit 120 . The gate shift clock is a clock signal commonly input to one or more gate circuits and controls the shift timing of the scan signal (gate pulse). The gate output enable signal specifies timing information of one or more gate circuits.

The data driver converts the image data received from the timing controller into an analog data voltage and outputs the converted image data.

In addition, the data driver may include a logic unit including various circuits such as a level shifter and a latch unit, a gamma voltage unit, a digital analog converter (DAC), an output buffer, and the like.

The power supply unit supplies power to the timing control unit and the data driver based on a power control signal received from the timing control unit.

That is, the first power supply unit supplies driving power to the first timing control unit and the first data driver, and the second power supply unit supplies driving power to the second timing control unit and the second data driver.

Meanwhile, the above-described data integrated circuit 130 is disposed on a base film made of an insulating material. That is, in FIG. 1 , the data integrated circuit 130 is illustrated as being mounted in a chip on film (COF) method, but the present invention is not limited thereto, and the driving IC 132 is a chip on glass (COG), a tape carrier package (TCP) It may be mounted in such a way.

A control unit such as an IC chip or a circuit unit may be mounted on the printed circuit board 140 . Also, a memory, a processor, etc. may be mounted on the printed circuit board 140 . The printed circuit board 140 is configured to transmit a signal for driving the display panel 110 from an external controller to the data integrated circuit 130 .

The mux circuit 150 may change a connection relationship between the plurality of folding data lines FDL and the plurality of connection lines CL. That is, the MUX circuit 150 may selectively apply the data voltage applied to each of the plurality of connection lines CL from the data integrated circuit 130 to the plurality of folding data lines FDL. In other words, the data voltage output from the multiplexer circuit 150 and the data integrated circuit 130 may be selectively applied to the plurality of display areas AA.

Accordingly, the MUX circuit 150 may be connected to the plurality of connection lines CL and may be connected to the plurality of folding data lines FDL. In addition, the MUX circuit 150 may include a plurality of transistors, and each transistor may be connected to any one of the plurality of connection lines CL and the plurality of folding data lines FDL.

Hereinafter, a detailed configuration and connection relationship of the MUX circuit 150 will be specifically reviewed.

FIG. 2 is a circuit diagram illustrating a MUX circuit of a foldable display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2 , each of the plurality of pixels PX of the foldable display according to an exemplary embodiment includes a red sub-pixel R emitting red light and a green sub-pixel G emitting green light. and a blue sub-pixel B that emits blue light. In addition, the plurality of red sub-pixels R are arranged in the same column, the plurality of green sub-pixels G are arranged in the same column, and the plurality of blue sub-pixels B are arranged in the same column.

In addition, the folding data line FDL may be composed of a first folding data line FDL1 to a sixth folding data line FDL6 . The first folding data line FDL1 , the second folding data line FDL2 , and the third folding data line FDL3 may be connected to the first folding area FA1 , and the fourth folding data line FDL4 and the fifth folding data line FDL3 may be connected to the first folding area FA1 . The folding data line FDL5 and the sixth folding data line FDL6 may be connected to the second folding area FA2 .

In addition, each of the red sub-pixels R may be connected to one folding data line, each of the green sub-pixels G may be connected to one folding data line, and each of the blue sub-pixels B may be connected to one folding data line. can be connected to the line.

Specifically, the plurality of red sub-pixels R disposed in the first folding area FA1 may be connected to the first folding data line FDL1 , and the plurality of red sub-pixels disposed in the second folding area FA2 . (R) may be connected to the fourth folding data line FDL4.

In addition, the plurality of green sub-pixels G disposed in the first folding area FA1 may be connected to the second folding data line FDL2 and the plurality of green sub-pixels G disposed in the second folding area FA2 ( FA2 ). G) may be connected to the fourth folding data line FDL4 .

In addition, the plurality of blue sub-pixels B disposed in the first folding area FA1 may be connected to the third folding data line FDL3 and the plurality of blue sub-pixels B disposed in the second folding area FA2 . B) may be connected to the sixth folding data line FDL6 .

Meanwhile, the connection line CL may include the first connection line CL1 to the sixth connection line CL6 . The first connection line CL1 , the second connection line CL2 , and the third connection line CL3 may be connected to the first data integrated circuit 131 , and the fourth connection line CL4 and the fifth connection line CL3 may be connected to each other. CL5 and the sixth connection line CL6 may be connected to the second data integrated circuit 132 .

In addition, the mux circuit 150 of the foldable display according to an embodiment of the present invention includes a plurality of transistors controlled by the first selection signal SA and a plurality of transistors controlled by the second selection signal SB. may include.

Specifically, the plurality of transistors controlled by the first selection signal SA include a TA1 transistor TA1, a TA2 transistor TA2, a TA3 transistor TA3, a TA4 transistor TA4, a TA5 transistor TA5, and a TA6 transistor. (TA6).

More specifically, in the TA1 transistor TA1 , the first selection signal SA is applied to the gate electrode, the first folding data line FDL1 is connected to the first electrode, and the first connection line FDL1 is connected to the second electrode. CL1) is connected. Accordingly, when the first selection signal SA is at the turn-on level, the TA1 transistor TA1 is turned on, so that the first folding data line FDL1 and the first connection line CL1 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the first connection line CL1 may be applied to the first folding data line FDL1 .

In the TA2 transistor TA2 , the first selection signal SA is applied to the gate electrode, the second folding data line FDL2 is connected to the first electrode, and the second connection line CL2 is connected to the second electrode. . Accordingly, when the first selection signal SA is at the turn-on level, the TA2 transistor TA2 is turned on, so that the second folding data line FDL2 and the second connection line CL2 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the second connection line CL2 may be applied to the second folding data line FDL2 .

In the TA3 transistor TA3 , the first selection signal SA is applied to the gate electrode, the third folding data line FDL3 is connected to the first electrode, and the third connection line CL3 is connected to the second electrode. . Accordingly, when the first selection signal SA is at the turn-on level, the TA3 transistor TA3 is turned on, so that the third folding data line FDL3 and the third connection line CL3 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the third connection line CL3 may be applied to the third folding data line FDL3 .

In the TA4 transistor TA4 , the first selection signal SA is applied to the gate electrode, the fourth folding data line FDL4 is connected to the first electrode, and the fourth connection line CL4 is connected to the second electrode. . Accordingly, when the first selection signal SA is at the turn-on level, the TA4 transistor TA4 is turned on, so that the fourth folding data line FDL4 and the fourth connection line CL4 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fourth connection line CL4 may be applied to the fourth folding data line FDL4 .

In the TA5 transistor TA5 , the first selection signal SA is applied to the gate electrode, the fifth folding data line FDL5 is connected to the first electrode, and the fifth connection line CL5 is connected to the second electrode. . Accordingly, when the first selection signal SA is at the turn-on level, the TA5 transistor TA5 is turned on, so that the fifth folding data line FDL5 and the fifth connection line CL5 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fifth connection line CL5 may be applied to the fifth folding data line FDL5 .

In the TA6 transistor TA6 , the first selection signal SA is applied to the gate electrode, the sixth folding data line FDL6 is connected to the first electrode, and the sixth connection line CL6 is connected to the second electrode. . Accordingly, when the first selection signal SA is at the turn-on level, the TA6 transistor TA6 is turned on, so that the sixth folding data line FDL6 and the sixth connection line CL6 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the sixth connection line CL6 may be applied to the sixth folding data line FDL6 .

Specifically, the plurality of transistors controlled by the second selection signal SB include a TB1 transistor TB1, a TB2 transistor TB2, a TB3 transistor TB3, a TB4 transistor TB4, a TB5 transistor TB5, and a TB6 transistor. (TB6).

More specifically, in the TB1 transistor TB1 , the second selection signal SB is applied to the gate electrode, the first folding data line FDL1 is connected to the first electrode, and the fourth connection line (FDL1) is connected to the second electrode. CL4) is connected. Accordingly, when the second selection signal SB is at the turn-on level, the TB1 transistor TB1 is turned on, so that the first folding data line FDL1 and the fourth connection line CL4 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fourth connection line CL4 may be applied to the first folding data line FDL1 .

In the TB2 transistor TB2 , the second selection signal SB is applied to the gate electrode, the second folding data line FDL2 is connected to the first electrode, and the fifth connection line CL5 is connected to the second electrode. . Accordingly, when the second selection signal SB is at the turn-on level, the TB2 transistor TB2 is turned on, so that the second folding data line FDL2 and the fifth connection line CL5 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fifth connection line CL5 may be applied to the second folding data line FDL2 .

In the TB3 transistor TB3 , the second selection signal SB is applied to the gate electrode, the third folding data line FDL3 is connected to the first electrode, and the sixth connection line CL6 is connected to the second electrode. . Accordingly, when the second selection signal SB is at the turn-on level, the TB3 transistor TB3 is turned on, so that the third folding data line FDL3 and the sixth connection line CL6 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the sixth connection line CL6 may be applied to the third folding data line FDL3 .

In the TB4 transistor TB4 , the second selection signal SB is applied to the gate electrode, the fourth folding data line FDL4 is connected to the first electrode, and the first connection line CL1 is connected to the second electrode. . Accordingly, when the second selection signal SB is at the turn-on level, the TB4 transistor TB4 is turned on, so that the fourth folding data line FDL4 and the first connection line CL1 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the first connection line CL1 may be applied to the fourth folding data line FDL4 .

In the TB5 transistor TB5 , the second selection signal SB is applied to the gate electrode, the fifth folding data line FDL5 is connected to the first electrode, and the second connection line CL2 is connected to the second electrode. . Accordingly, when the second selection signal SB is at the turn-on level, the TB5 transistor TB5 is turned on, so that the fifth folding data line FDL5 and the second connection line CL2 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the second connection line CL2 may be applied to the fifth folding data line FDL5 .

In the TB6 transistor TB6 , the second selection signal SB is applied to the gate electrode, the sixth folding data line FDL6 is connected to the first electrode, and the third connection line CL3 is connected to the second electrode. . Accordingly, when the second selection signal SB is at the turn-on level, the TB6 transistor TB6 is turned on, so that the sixth folding data line FDL6 and the third connection line CL3 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the third connection line CL3 may be applied to the sixth folding data line FDL6 .

3A is a circuit diagram for explaining driving of a MUX circuit when a foldable display device according to an exemplary embodiment is in a folded state.

When the foldable display device according to an exemplary embodiment is in a folded state, the display panel 110 may be half driven. When the display panel 110 is half driven, the image displayed on the area displayed on the first display area AA1 and the image displayed on the second display area AA2 are different from each other.

Accordingly, when the display panel 110 is half driven, the first folding area FA1 is driven by the first data integrated circuit 131 , and the second folding area FA2 is driven by the second data integrated circuit 132 . ) can be driven by

To this end, the first selection signal SA is set to the turn-on level, and the second selection signal SB is set to the turn-off level.

Accordingly, the TA1 transistor TA1, the TA2 transistor TA2, the TA3 transistor TA3, the TA4 transistor TA4, the TA5 transistor TA5, and the TA6 transistor TA6 are all turned on, and the TB1 transistor TB1 and the TB2 transistor are turned on. TB2, TB3 transistor TB3, TB4 transistor TB4, TB5 transistor TB5, and TB6 transistor TB6 are all turned off.

Accordingly, the first folding data line FDL1 and the first connection line CL1 are electrically connected, the second folding data line FDL2 and the second connection line CL2 are electrically connected, and the third folding data The line FDL3 and the third connection line CL3 are electrically connected, the fourth folding data line FDL4 and the fourth connection line CL4 are electrically connected, and the fifth folding data line FDL5 and the second connection line CL4 are electrically connected. The fifth connection line CL5 is electrically connected, and the sixth folding data line FDL6 and the sixth connection line CL6 are electrically connected.

Accordingly, the data voltages output from the first data integrated circuit 131 are the plurality of red sub-pixels R, the plurality of green sub-pixels G, and the plurality of blue sub-pixels AA1 disposed in the first display area AA1 . B) can be applied to each. In addition, the data voltages output from the second data integrated circuit 132 are the plurality of red sub-pixels R, the plurality of green sub-pixels G, and the plurality of blue sub-pixels AA2 disposed in the second display area AA2 . B) can be applied to each.

3B is a circuit diagram for explaining driving of a MUX circuit when the foldable display device according to an exemplary embodiment is in an unfolded state.

When the foldable display device according to an exemplary embodiment is in an unfolded state, the display panel 110 may be fully driven. When the display panel 110 is fully driven, the image displayed on the area displayed on the first display area AA1 and the image displayed on the second display area AA2 form one image as a whole.

Accordingly, when the display panel 110 is fully driven, the second folding area FA2 is driven by the first data integrated circuit 131 , and the first folding area FA1 is driven by the second data integrated circuit 132 . ) can be driven by

To this end, the first selection signal SA is set to the turn-off level, and the second selection signal SB is set to the turn-on level.

Accordingly, the TA1 transistor TA1, the TA2 transistor TA2, the TA3 transistor TA3, the TA4 transistor TA4, the TA5 transistor TA5, and the TA6 transistor TA6 are all turned off, and the TB1 transistors TB1 and TB2 are turned off. Transistor TB2, TB3 transistor TB3, TB4 transistor TB4, TB5 transistor TB5, and TB6 transistor TB6 are all turned on.

Accordingly, the first folding data line FDL1 and the fourth connection line CL4 are electrically connected, the second folding data line FDL2 and the fifth connection line CL5 are electrically connected, and the third folding data The line FDL3 and the sixth connection line CL6 are electrically connected, the fourth folding data line FDL4 and the first connection line CL1 are electrically connected, and the fifth folding data line FDL5 and the first connection line CL1 are electrically connected. The second connection line CL2 is electrically connected, and the sixth folding data line FDL6 and the third connection line CL3 are electrically connected.

Accordingly, the data voltages output from the first data integrated circuit 131 are a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels disposed in the second folding area FA2. B) can be applied to each. In addition, the data voltage output from the second data integrated circuit 132 is a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels arranged in the first folding area FA1. B) can be applied to each.

As described above, when the display panel 110 is fully driven, the image displayed on the area displayed on the first display area AA1 and the image displayed on the second display area AA2 are one image as a whole. , the boundary between the first display area AA1 and the second display area AA2 should not be recognized.

However, since the first data integrated circuit 131 and the second data integrated circuit 132 are driven separately, the data voltage output from the first data integrated circuit 131 and the data voltage output from the second data integrated circuit 132 are separately driven. Data voltages may be slightly different.

Accordingly, unlike the foldable display according to an exemplary embodiment, the first display area AA1 is driven only by the first data integrated circuit 131 and the second display area AA2 is driven by the second data integrated circuit. If driving is performed only at 132 , a problem occurs in that a boundary between the first display area AA1 and the second display area AA2 is generated.

Accordingly, in the foldable display device according to the exemplary embodiment of the present invention, the data voltage output from the first data integrated circuit 131 is output to the second folding area FA2 and the second data integrated circuit 132 is outputted from the second data integrated circuit 132 . By outputting the output data voltage to the first folding area FA1 , a boundary line that may occur around the folding line FL may be relaxed.

Accordingly, in the unfolded state, the foldable display improves the display quality of the image so that the boundary line is not recognized, thereby perfectly realizing one image.

Hereinafter, a foldable display device according to another exemplary embodiment of the present invention will be described. Since the foldable display device according to an embodiment of the present invention and the foldable display device according to another embodiment of the present invention have a different sub-pixel arrangement relationship of a plurality of pixels and a transistor connection relationship of the MUX circuit 150 , the relationship between them is different. , will focus on this.

4 is a circuit diagram illustrating a MUX circuit of a foldable display device according to another exemplary embodiment of the present invention.

As shown in FIG. 4 , each of the plurality of pixels PX of the foldable display according to another exemplary embodiment includes a red sub-pixel R that emits red light and a green sub-pixel G that emits green light. and a blue sub-pixel B that emits blue light. Further, the plurality of red sub-pixels R and the plurality of blue sub-pixels B are alternately arranged in the same column, and the plurality of green sub-pixels G are arranged in the same column. Accordingly, the blue sub-pixel B disposed in one column and the two green sub-pixels G disposed in a column adjacent to the red sub-pixel R constitute one pixel.

In addition, the folding data line FDL may be composed of a first folding data line FDL1 to an eighth folding data line FDL8 . The first folding data line FDL1 , the second folding data line FDL2 , the third folding data line FDL3 , and the fourth folding data line FDL4 may be connected to the first folding area FA1 and a fifth The folding data line FDL5 , the sixth folding data line FDL6 , the seventh folding data line FDL7 , and the eighth folding data line FDL8 may be connected to the second folding area FA2 .

In addition, the blue sub-pixels B and the red sub-pixels R arranged in one column may be connected to one folding data line, and the plurality of green sub-pixels G may be connected to the other folding data line.

In detail, the plurality of red sub-pixels R and the plurality of blue sub-pixels B alternately arranged in the first folding area FA1 include the first folding data line FDL1 and the third folding data line FDL3 . ), and the plurality of red sub-pixels R and the plurality of blue sub-pixels B alternately arranged in the second folding area FA2 include the fifth folding data line FDL5 and the seventh folding data line FDL5 . It may be connected to the data line FDL7.

In addition, the plurality of green sub-pixels G disposed in the first folding area FA1 may be connected to each of the second folding data line FDL2 and the fourth folding data line FDL4, and the second folding area FA2 ) may be connected to each of the sixth folding data line FDL6 and the eighth folding data line FDL8.

Meanwhile, the connection line CL may include the first connection line CL1 to the eighth connection line CL8 . The first connection line CL1 , the second connection line CL2 , the third connection line CL3 , and the fourth connection line CL4 may be connected to the first data integrated circuit 131 , and a fifth connection line ( CL5 , the sixth connection line CL6 , the seventh connection line CL7 , and the eighth connection line CL8 may be connected to the second data integrated circuit 132 .

In addition, the mux circuit 150 of the foldable display according to another embodiment of the present invention includes a plurality of transistors controlled by the third selection signal SC and a plurality of transistors controlled by the fourth selection signal SD. , a plurality of transistors controlled by the fifth selection signal SE and a plurality of transistors controlled by the sixth selection signal SF.

Specifically, the plurality of transistors controlled by the third selection signal SC includes a TC1 transistor TC1 , a TC2 transistor TC2 , a TC3 transistor TC3 , and a TC4 transistor TC4 .

More specifically, in the TC1 transistor TC1, the third selection signal SC is applied to the gate electrode, the first folding data line FDL1 is connected to the first electrode, and the first connection line (FDL1) is connected to the second electrode. CL1) is connected. Accordingly, when the third selection signal SC is at the turn-on level, the TC1 transistor TC1 is turned on, so that the first folding data line FDL1 and the first connection line CL1 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the first connection line CL1 may be applied to the first folding data line FDL1 .

In the TC2 transistor TC2 , the third selection signal SC is applied to the gate electrode, the second folding data line FDL2 is connected to the first electrode, and the second connection line CL2 is connected to the second electrode. . Accordingly, when the third selection signal SC is at the turn-on level, the TC2 transistor TC2 is turned on, so that the second folding data line FDL2 and the second connection line CL2 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the second connection line CL2 may be applied to the second folding data line FDL2 .

In the TC3 transistor TC3 , the third selection signal SC is applied to the gate electrode, the fifth folding data line FDL5 is connected to the first electrode, and the fifth connection line CL5 is connected to the second electrode. . Accordingly, when the third selection signal SC is at the turn-on level, the TC3 transistor TC3 is turned on, so that the fifth folding data line FDL5 and the fifth connection line CL5 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fifth connection line CL5 may be applied to the fifth folding data line FDL5 .

In the TC4 transistor TC4 , the third selection signal SC is applied to the gate electrode, the sixth folding data line FDL6 is connected to the first electrode, and the sixth connection line CL6 is connected to the second electrode. . Accordingly, when the third selection signal SC is at the turn-on level, the TC4 transistor TC4 is turned on so that the sixth folding data line FDL6 and the sixth connection line CL6 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the sixth connection line CL6 may be applied to the sixth folding data line FDL6 .

Specifically, the plurality of transistors controlled by the fourth selection signal SD include a TD1 transistor TD1 , a TD2 transistor TD2 , a TD3 transistor TD3 , and a TD4 transistor TD4 .

More specifically, in the TD1 transistor TD1 , the fourth selection signal SD is applied to the gate electrode, the first folding data line FDL1 is connected to the first electrode, and the fifth connection line (FDL1) is connected to the second electrode. CL5) is connected. Accordingly, when the fourth selection signal SD is at the turn-on level, the TD1 transistor TD1 is turned on, so that the first folding data line FDL1 and the fifth connection line CL5 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fifth connection line CL5 may be applied to the first folding data line FDL1 .

In the TD2 transistor TD2 , the fourth selection signal SD is applied to the gate electrode, the second folding data line FDL2 is connected to the first electrode, and the sixth connection line CL6 is connected to the second electrode. . Accordingly, when the fourth selection signal SD is at the turn-on level, the TD2 transistor TD2 is turned on, so that the second folding data line FDL2 and the sixth connection line CL6 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the sixth connection line CL6 may be applied to the second folding data line FDL2 .

In the TD3 transistor TD3 , the fourth selection signal SD is applied to the gate electrode, the fifth folding data line FDL5 is connected to the first electrode, and the first connection line CL1 is connected to the second electrode. . Accordingly, when the fourth selection signal SD is at the turn-on level, the TD3 transistor TD3 is turned on, so that the fifth folding data line FDL5 and the first connection line CL1 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the first connection line CL1 may be applied to the fifth folding data line FDL5 .

In the TD4 transistor TD4 , the fourth selection signal SD is applied to the gate electrode, the sixth folding data line FDL6 is connected to the first electrode, and the second connection line CL2 is connected to the second electrode. . Accordingly, when the fourth selection signal SD is at the turn-on level, the TD4 transistor TD4 is turned on, so that the sixth folding data line FDL6 and the second connection line CL2 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the second connection line CL2 may be applied to the sixth folding data line FDL6 .

Specifically, the plurality of transistors controlled by the fifth selection signal SE includes a TE1 transistor TE1 , a TE2 transistor TE2 , a TE3 transistor TE3 , and a TE4 transistor TE4 .

More specifically, in the TE1 transistor TE1 , the fifth selection signal SE is applied to the gate electrode, the third folding data line FDL3 is connected to the first electrode, and the third connection line FDL3 is connected to the second electrode. CL3) is connected. Accordingly, when the fifth selection signal SE is at the turn-on level, the TE1 transistor TE1 is turned on, so that the third folding data line FDL3 and the third connection line CL3 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the third connection line CL3 may be applied to the third folding data line FDL3 .

In the TE2 transistor TE2 , the fifth selection signal SE is applied to the gate electrode, the fourth folding data line FDL4 is connected to the first electrode, and the fourth connection line CL4 is connected to the second electrode. . Accordingly, when the fifth selection signal SE is at the turn-on level, the TE2 transistor TE2 is turned on, so that the fourth folding data line FDL4 and the fourth connection line CL4 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fourth connection line CL4 may be applied to the fourth folding data line FDL4 .

In the TE3 transistor TE3 , the fifth selection signal SE is applied to the gate electrode, the seventh folding data line FDL7 is connected to the first electrode, and the seventh connection line CL7 is connected to the second electrode. . Accordingly, when the fifth selection signal SE is at the turn-on level, the TE3 transistor TE3 is turned on, so that the seventh folding data line FDL7 and the seventh connection line CL7 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the seventh connection line CL7 may be applied to the seventh folding data line FDL7 .

In the TE4 transistor TE4 , the fifth selection signal SE is applied to the gate electrode, the eighth folding data line FDL8 is connected to the first electrode, and the eighth connection line CL8 is connected to the second electrode. . Accordingly, when the fifth selection signal SE is at the turn-on level, the TE4 transistor TE4 is turned on, so that the eighth folding data line FDL8 and the eighth connection line CL8 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the eighth connection line CL8 may be applied to the eighth folding data line FDL8 .

Specifically, the plurality of transistors controlled by the sixth selection signal SF include a TF1 transistor TF1 , a TF2 transistor TF2 , a TF3 transistor TF3 , and a TF4 transistor TF4 .

In more detail, in the TF1 transistor TF1 , the sixth selection signal SF is applied to the gate electrode, the third folding data line FDL3 is connected to the first electrode, and the seventh connection line (FDL3) is connected to the second electrode. CL7) is connected. Accordingly, when the sixth selection signal SF is at the turn-on level, the TF1 transistor TF1 is turned on, so that the third folding data line FDL3 and the seventh connection line CL7 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the seventh connection line CL7 may be applied to the third folding data line FDL3 .

In the TF2 transistor TF2 , the sixth selection signal SF is applied to the gate electrode, the fourth folding data line FDL4 is connected to the first electrode, and the eighth connection line CL8 is connected to the second electrode. . Accordingly, when the sixth selection signal SF is at the turn-on level, the TF2 transistor TF2 is turned on, so that the fourth folding data line FDL4 and the eighth connection line CL8 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the eighth connection line CL8 may be applied to the fourth folding data line FDL4 .

In the TF3 transistor TF3 , the sixth selection signal SF is applied to the gate electrode, the seventh folding data line FDL7 is connected to the first electrode, and the third connection line CL3 is connected to the second electrode. . Accordingly, when the sixth selection signal SF is at the turn-on level, the TF3 transistor TF3 is turned on, so that the seventh folding data line FDL7 and the third connection line CL3 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the third connection line CL3 may be applied to the seventh folding data line FDL7 .

In the TF4 transistor TF4 , the sixth selection signal SF is applied to the gate electrode, the eighth folding data line FDL8 is connected to the first electrode, and the fourth connection line CL4 is connected to the second electrode. . Accordingly, when the sixth selection signal SF is at the turn-on level, the TF4 transistor TF4 is turned on, so that the eighth folding data line FDL8 and the fourth connection line CL4 are electrically connected to each other. can be connected Accordingly, the data voltage applied to the fourth connection line CL4 may be applied to the eighth folding data line FDL8 .

5A is a circuit diagram for explaining driving of a MUX circuit when a foldable display device according to another exemplary embodiment is in a folded state.

When the foldable display device according to another exemplary embodiment is in a folded state, the display panel 110 may be half driven. When the display panel 110 is half driven, the image displayed on the area displayed on the first display area AA1 and the image displayed on the second display area AA2 are different from each other.

Accordingly, when the display panel 110 is half driven, the first folding area FA1 is driven by the first data integrated circuit 131 , and the second folding area FA2 is driven by the second data integrated circuit 132 . ) can be driven by

To this end, the third selection signal SC and the fifth selection signal SE are set to the turn-on level, and the fourth selection signal SD and the sixth selection signal SF are set to the turn-off level.

Accordingly, the TC1 transistor TC1, the TC2 transistor TC2, the TC3 transistor TC3, the TC4 transistor TC4, the TE1 transistor TE1, the TE2 transistor TE2, the TE3 transistor TE3, and the TE4 transistor TE4 are All turned on, TD1 transistor (TD1), TD2 transistor (TD2), TD3 transistor (TD3), TD4 transistor (TD4), TF1 transistor (TF1), TF2 transistor (TF2), TF3 transistor (TF3) and TF4 transistor (TF4) ) are all turned off.

Accordingly, the first folding data line FDL1 and the first connection line CL1 are electrically connected, the second folding data line FDL2 and the second connection line CL2 are electrically connected, and the third folding data The line FDL3 and the third connection line CL3 are electrically connected, the fourth folding data line FDL4 and the fourth connection line CL4 are electrically connected, and the fifth folding data line FDL5 and the second connection line CL4 are electrically connected. The fifth connection line CL5 is electrically connected, the sixth folding data line FDL6 and the sixth connection line CL6 are electrically connected, and the seventh folding data line FDL7 and the seventh connection line CL7 are electrically connected. are electrically connected, and the eighth folding data line FDL8 and the eighth connection line CL8 are electrically connected.

Accordingly, the data voltages output from the first data integrated circuit 131 are the plurality of red sub-pixels R, the plurality of green sub-pixels G, and the plurality of blue sub-pixels AA1 disposed in the first display area AA1 . B) can be applied to each. In addition, the data voltages output from the second data integrated circuit 132 are the plurality of red sub-pixels R, the plurality of green sub-pixels G, and the plurality of blue sub-pixels AA2 disposed in the second display area AA2 . B) can be applied to each.

5B to 5D are circuit diagrams for explaining driving of a MUX circuit when the foldable display device according to another exemplary embodiment is in an unfolded state.

Specifically, FIG. 5B illustrates driving of the mux circuit 250 when the fourth selection signal SD and the fifth selection signal SE are at the turn-on level in the foldable display device according to another embodiment of the present invention. This is a circuit diagram for In addition, FIG. 5C illustrates driving of the mux circuit 250 when the third selection signal SC and the sixth selection signal SF are at turn-on levels in the foldable display device according to another embodiment of the present invention. circuit diagram for 5D is a circuit diagram illustrating driving of the mux circuit 250 when the fourth selection signal SD and the sixth selection signal SF are at turn-on levels in the foldable display device according to another embodiment of the present invention. to be.

When the foldable display device according to another exemplary embodiment is in an unfolded state, the display panel 110 may be fully driven. When the display panel 110 is fully driven, the image displayed on the area displayed on the first display area AA1 and the image displayed on the second display area AA2 form one image as a whole.

Accordingly, when the display panel 110 is fully driven, a portion of the second folding area FA2 is driven by the first data integrated circuit 131 , and a portion of the first folding area FA1 is driven by the second data It may be driven by an integrated circuit 132 .

To this end, referring to FIG. 5B , the fourth selection signal SD and the fifth selection signal SE are set to the turn-on level, and the third selection signal SC and the sixth selection signal SF are set to the turn-off level. set to

Accordingly, the TD1 transistor TD1, the TD2 transistor TD2, the TD3 transistor TD3, the TD4 transistor TD4, the TE1 transistor TE1, the TE2 transistor TE2, the TE3 transistor TE3, and the TE4 transistor TE4 are All turned on, TC1 transistor (TC1), TC2 transistor (TC2), TC3 transistor (TC3), TC4 transistor (TC4), TF1 transistor (TF1), TF2 transistor (TF2), TF3 transistor (TF3) and TF4 transistor (TF4) ) are all turned off.

Accordingly, the first folding data line FDL1 and the fifth connection line CL5 are electrically connected, the second folding data line FDL2 and the sixth connection line CL6 are electrically connected, and the third folding data The line FDL3 and the third connection line CL3 are electrically connected, the fourth folding data line FDL4 and the fourth connection line CL4 are electrically connected, and the fifth folding data line FDL5 and the second connection line CL4 are electrically connected. The first connection line CL1 is electrically connected, the sixth folding data line FDL6 and the second connection line CL2 are electrically connected, and the seventh folding data line FDL7 and the seventh connection line CL7 are electrically connected. are electrically connected, and the eighth folding data line FDL8 and the eighth connection line CL8 are electrically connected.

Accordingly, the data voltage output from the first data integrated circuit 131 to the first connection line CL1 and the second connection line CL2 is a plurality of red sub-pixels R disposed in the second display area AA2 . , may be applied to each of the plurality of green sub-pixels (G) and the plurality of blue sub-pixels (B). In addition, the data voltages output from the second data integrated circuit 132 to the fifth connection line CL5 and the sixth connection line CL6 are a plurality of red sub-pixels R disposed in the first display area AA1 . , may be applied to each of the plurality of green sub-pixels (G) and the plurality of blue sub-pixels (B).

In another form, referring to FIG. 5C , the fourth selection signal SD and the fifth selection signal SE are set to a turn-off level, and the third selection signal SC and the sixth selection signal SF are Set to turn-on level.

Accordingly, the TD1 transistor TD1, the TD2 transistor TD2, the TD3 transistor TD3, the TD4 transistor TD4, the TE1 transistor TE1, the TE2 transistor TE2, the TE3 transistor TE3, and the TE4 transistor TE4 are All turned off, TC1 transistor (TC1), TC2 transistor (TC2), TC3 transistor (TC3), TC4 transistor (TC4), TF1 transistor (TF1), TF2 transistor (TF2), TF3 transistor (TF3) and TF4 transistor ( TF4) are all turned on.

Accordingly, the first folding data line FDL1 and the first connection line CL1 are electrically connected, the second folding data line FDL2 and the second connection line CL2 are electrically connected, and the third folding data The line FDL3 and the seventh connection line CL7 are electrically connected, the fourth folding data line FDL4 and the eighth connection line CL8 are electrically connected, and the fifth folding data line FDL5 and the first connection line CL8 are electrically connected. The fifth connecting line CL5 is electrically connected, the sixth folding data line FDL6 and the sixth connecting line CL6 are electrically connected, and the seventh folding data line FDL7 and the third connecting line CL3 are electrically connected. are electrically connected, and the eighth folding data line FDL8 and the fourth connection line CL4 are electrically connected.

Accordingly, the data voltages output from the first data integrated circuit 131 to the third connection line CL3 and the fourth connection line CL4 are the plurality of red sub-pixels R disposed in the second display area AA2 . , may be applied to each of the plurality of green sub-pixels (G) and the plurality of blue sub-pixels (B). In addition, the data voltages output from the second data integrated circuit 132 to the seventh connection line CL7 and the eighth connection line CL8 are a plurality of red sub-pixels R disposed in the first display area AA1 . , may be applied to each of the plurality of green sub-pixels (G) and the plurality of blue sub-pixels (B).

Alternatively, when the display panel 110 is fully driven, the second folding area FA2 is driven by the first data integrated circuit 131 , and the first folding area FA1 is driven by the second data integration circuit 131 . It may be driven by circuit 132 .

To this end, referring to FIG. 5D , the fourth selection signal SD and the sixth selection signal SF are set to the turn-on level, and the third selection signal SC and the fifth selection signal SE are set to the turn-off level. set to

Accordingly, TD1 transistor TD1, TD2 transistor TD2, TD3 transistor TD3, TD4 transistor TD4, TF1 transistor TF1, TF2 transistor TF2, TF3 transistor TF3, and TF4 transistor TF4 are All turned on, TC1 transistor (TC1), TC2 transistor (TC2), TC3 transistor (TC3), TC4 transistor (TC4), TE1 transistor (TE1), TE2 transistor (TE2), TE3 transistor (TE3) and TE4 transistor (TE4) ) are all turned off.

Accordingly, the first folding data line FDL1 and the fifth connection line CL5 are electrically connected, the second folding data line FDL2 and the sixth connection line CL6 are electrically connected, and the third folding data The line FDL3 and the seventh connection line CL7 are electrically connected, the fourth folding data line FDL4 and the eighth connection line CL8 are electrically connected, and the fifth folding data line FDL5 and the first connection line CL8 are electrically connected. The first connection line CL1 is electrically connected, the sixth folding data line FDL6 and the second connection line CL2 are electrically connected, and the seventh folding data line FDL7 and the third connection line CL3 are electrically connected. are electrically connected, and the eighth folding data line FDL8 and the fourth connection line CL4 are electrically connected.

Accordingly, the data voltages output from the first data integrated circuit 131 are the plurality of red sub-pixels R, the plurality of green sub-pixels G, and the plurality of blue sub-pixels AA2 disposed in the second display area AA2 . B) can be applied to each. In addition, the data voltage output from the second data integrated circuit 132 is a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels arranged in the first display area AA1 . B) can be applied to each.

Accordingly, in the foldable display device according to another embodiment of the present invention, the data voltage output from the first data integrated circuit 131 is output to the second folding area FA2 and the second data integrated circuit 132 is By outputting the output data voltage to the first folding area FA1, a boundary line that may occur around the folding line may be relaxed.

Accordingly, in the unfolded state, the foldable display improves the display quality of the image so that the boundary line is not recognized, thereby perfectly realizing one image.

A foldable display device and a driving method thereof according to an embodiment of the present invention may be described as follows.

A foldable display device according to an embodiment of the present invention includes a display panel 110 including a plurality of display areas separated by a folding line, a plurality of data integrated circuits outputting data voltages to the display areas, and a plurality of data A boundary between the display regions may be minimized by including a MUX circuit for selectively applying the data voltage output from the integrated circuit to the plurality of display regions.

According to another feature of the present invention, the display panel 110 includes a first display area divided into a first folding area and a first non-folding area, and a second display area divided into a second folding area and a second non-folding area. may include

According to another feature of the present invention, the mux circuit is connected to the first folding area and the second folding area through a plurality of folding data lines, and through the plurality of connection lines, the first data integrated circuit and the second data integrated circuit can be connected to the circuit.

According to another feature of the present invention, the MUX circuit includes a plurality of transistors, each of the plurality of transistors is controlled by one of a plurality of selection signals, and a first electrode of each of the plurality of transistors is one of a plurality of folding data lines. connected to one, and the second electrode of each of the plurality of transistors may be connected to one of the plurality of connection lines.

According to another feature of the present invention, in the first folding area, a plurality of red sub-pixels connected to the first folding data line, a plurality of green sub-pixels connected to the second folding data line, and a third folding data line are connected a plurality of blue sub-pixels are disposed, and in the second folding area, a plurality of red sub-pixels connected to a fourth folding data line, a plurality of green sub-pixels connected to a fifth folding data line, and a sixth folding data line A plurality of connected blue sub-pixels may be disposed.

According to another feature of the present invention, the first data integrated circuit is connected to the first connection line, the second connection line, and the third connection line, and the second data integrated circuit includes the fourth connection line, the fifth connection line and the third connection line. It can be connected to 6 connecting wires.

According to another feature of the present invention, the MUX circuit unit includes a TA1 transistor, a TA2 transistor, a TA3 transistor, a TA4 transistor, a TA5 transistor, and a TA6 transistor controlled by a first selection signal, and includes a plurality of transistors controlled by a second selection signal. The transistors of the TB1 transistors, TB2 transistors, TB3 transistors, TB4 transistors, TB5 transistors, and TB6 transistors may include.

According to another feature of the present invention, in the TA1 transistor, a first selection signal is applied to the gate electrode, the first folding data line is connected to the first electrode, the first connection line is connected to the second electrode, and the TA2 transistor In the TA3 transistor, the first selection signal is applied to the gate electrode, the second folding data line is connected to the first electrode, the second connection line is connected to the second electrode, and the first selection signal is applied to the gate electrode in the TA3 transistor. , a third folding data line is connected to the first electrode, a third connection line is connected to the second electrode, a first selection signal is applied to the gate electrode in the TA4 transistor, and a fourth folding data line is connected to the first electrode connected, a fourth connection line is connected to the second electrode, a first selection signal is applied to the gate electrode of the TA5 transistor, a fifth folding data line is connected to the first electrode, and a fifth connection line is connected to the second electrode is connected, a first selection signal is applied to the gate electrode in the TA6 transistor, a sixth folding data line is connected to the first electrode, a sixth connection line is connected to the second electrode, and a first selection signal is applied to the gate electrode in the TB1 transistor. The second selection signal is applied, the first folding data line is connected to the first electrode, the fourth connection line is connected to the second electrode, the second selection signal is applied to the gate electrode of the TB2 transistor, and the first electrode is connected to the first electrode. The second folding data line is connected to the second electrode, the fifth connection line is connected to the second electrode, the second selection signal is applied to the gate electrode of the TB3 transistor, the third folding data line is connected to the first electrode, and the second The sixth connection line is connected to the electrode, the second selection signal is applied to the gate electrode of the TB4 transistor, the fourth folding data line is connected to the first electrode, the first connection line is connected to the second electrode, and TB5 In the transistor, the second selection signal is applied to the gate electrode, the fifth folding data line is connected to the first electrode, the second connection line is connected to the second electrode, and T In the B6 transistor, the second selection signal may be applied to the gate electrode, the sixth folding data line may be connected to the first electrode, and the third connection line may be connected to the second electrode.

According to another feature of the present invention, when the display panel 110 is in a folded state, the first selection signal may have a turn-on level and the second selection signal may have a turn-off level.

According to another feature of the present invention, when the display panel 110 is in the non-folding state, the first selection signal may have a turn-off level and the second selection signal may have a turn-on level.

According to another feature of the present invention, in the first folding area, a plurality of red sub-pixels, a plurality of blue sub-pixels, and a second folding data line are alternately connected to the first and third folding data lines, respectively; A plurality of green sub-pixels connected to each of the fourth data lines are disposed, and a plurality of red sub-pixels and a plurality of blue sub-pixels alternately connected to each of the fifth and seventh data lines are disposed in the second folding area. A plurality of green sub-pixels connected to the pixel and each of the sixth folding data line and the eighth data line may be disposed.

According to another aspect of the present invention, the first data integrated circuit is connected to the first connection line, the second connection line, the third connection line, and the fourth connection line, and the second data integrated circuit includes the fifth connection line and the fourth connection line. It may be connected to the 6 connection wire, the seventh connection wire, and the eighth connection wire.

According to another feature of the present invention, the mux circuit unit includes a TC1 transistor, a TC2 transistor, a TC3 transistor, and a TC4 transistor controlled by a third selection signal, and the TD1 transistor, TD2 transistor, and TD3 are controlled by the fourth selection signal. TE1 transistor, TE2 transistor, TE3 transistor and TE4 transistor, comprising a transistor and a TD4 transistor, controlled by a fifth select signal, the TF1 transistor, TF2 transistor, TF3 transistor and TF4 transistor being controlled by a sixth select signal may include.

According to another feature of the present invention, in the TC1 transistor, a third selection signal is applied to the gate electrode, the first folding data line is connected to the first electrode, the first connection line is connected to the second electrode, and the TC2 transistor In the TC3 transistor, the third selection signal is applied to the gate electrode, the second folding data line is connected to the first electrode, the second connection line is connected to the second electrode, and the third selection signal is applied to the gate electrode in the TC3 transistor. , a fifth folding data line is connected to the first electrode, a fifth connection line is connected to the second electrode, a third selection signal is applied to the gate electrode in the TC4 transistor, and a sixth folding data line is connected to the first electrode. connected, the sixth connection line is connected to the second electrode, the fourth selection signal is applied to the gate electrode of the TD1 transistor, the first folding data line is connected to the first electrode, and the fifth connection line is connected to the second electrode is connected, the fourth selection signal is applied to the gate electrode in the TD2 transistor, the second folding data line is connected to the first electrode, the sixth connection line is connected to the second electrode, and the gate electrode is connected to the gate electrode in the TD3 transistor. A fourth selection signal is applied, a fifth folding data line is connected to the first electrode, a first connection line is connected to the second electrode, a fourth selection signal is applied to a gate electrode in the TD4 transistor, and a first electrode is connected to the first electrode. The sixth folding data line is connected to the second electrode, the second connection line is connected to the second electrode, the fifth selection signal is applied to the gate electrode in the TE1 transistor, the third folding data line is connected to the first electrode, and the second A third connection line is connected to the electrode, a fifth selection signal is applied to the gate electrode in the TE2 transistor, a fourth folding data line is connected to the first electrode, a fourth connection line is connected to the second electrode, and TE3 In the transistor, a fifth selection signal is applied to the gate electrode, a seventh folding data line is connected to the first electrode, a seventh connection line is connected to the second electrode, and T In the E4 transistor, a fifth selection signal is applied to the gate electrode, an eighth folding data line is connected to the first electrode, an eighth connection line is connected to the second electrode, and a sixth selection signal is applied to the gate electrode in the TF1 transistor. is applied, the third folding data line is connected to the first electrode, the seventh connection line is connected to the second electrode, the sixth selection signal is applied to the gate electrode in the TF2 transistor, and the fourth folding data is applied to the first electrode. line is connected to the second electrode, an eighth connection line is connected to the second electrode, a sixth selection signal is applied to the gate electrode of the TF3 transistor, a seventh folding data line is connected to the first electrode, and a third data line is connected to the second electrode A connection line may be connected, a sixth selection signal may be applied to the gate electrode of the TF4 transistor, an eighth folding data line may be connected to the first electrode, and a fourth connection line may be connected to the second electrode.

According to another feature of the present invention, when the display panel 110 is in a folded state, the third selection signal and the fifth selection signal may have turn-on levels, and the fourth selection signal and the sixth selection signal may have turn-off levels. have.

According to another feature of the present invention, when the display panel 110 is in a non-folding state, the fourth selection signal and the fifth selection signal are at the turn-on level, and the third selection signal and the sixth selection signal are at the turn-off level, or , the third selection signal and the sixth selection signal are turn-on levels, the fourth selection signal and the fifth selection signal are turn-off levels, or the fourth selection signal and the sixth selection signal are turn-on levels, and the fifth selection signal and the fifth selection signal 6 The selection signal may be a turn-off level.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: foldable display device
110: display panel
120: gate driving circuit
130: data integrated circuit
131: first data integrated circuit
132: second data integrated circuit
140: printed circuit board
150, 250: mux circuit
AA: display area
NA: non-display area
AA1: first display area
FA1: first folding area
NFA1: first non-folding area
AA2: second display area
FA2: second folding area
NFA2: second non-folding area
PX: Pixel
R: Red sub-pixel
G: Green sub-pixel
B: blue sub-pixel
FL: folding line
DL: data line
FDL: Folding data line
NFDL: non-folding data line
GL: gate line
SA: first selection signal
SB: second selection signal
SC: third selection signal
SD: 4th selection signal
SE: fifth selection signal
SF: sixth selection signal

Claims (16)

a display panel including a plurality of display areas divided by folding lines;
a plurality of data integrated circuits outputting data voltages to the display area; and
and a MUX circuit for selectively applying the data voltages output from the plurality of data integrated circuits to the plurality of display areas.
According to claim 1,
The display panel is
a first display area divided into a first folding area and a first non-folding area; and
A foldable display comprising a second display area divided into a second folding area and a second non-folding area.
3. The method of claim 2,
The mux circuit is
connected to the first folding area and the second folding area through a plurality of folding data lines;
A foldable display device connected to the first data integrated circuit and the second data integrated circuit through a plurality of connection lines.
4. The method of claim 3,
The mux circuit includes a plurality of transistors,
each of the plurality of transistors is controlled by one of a plurality of selection signals;
a first electrode of each of the plurality of transistors is connected to one of the plurality of folding data lines;
The second electrode of each of the plurality of transistors is connected to one of the plurality of connection lines.
5. The method of claim 4,
In the first folding area,
a plurality of red sub-pixels connected to the first folding data line, a plurality of green sub-pixels connected to the second folding data line, and a plurality of blue sub-pixels connected to a third folding data line are disposed;
In the second folding area,
A foldable display, comprising: a plurality of red sub-pixels connected to a fourth folding data line, a plurality of green sub-pixels connected to a fifth folding data line, and a plurality of blue sub-pixels connected to a sixth folding data line.
6. The method of claim 5,
the first data integrated circuit is connected to a first connection line, a second connection line, and a third connection line;
and the second data integrated circuit is connected to a fourth connection line, a fifth connection line, and a sixth connection line.
7. The method of claim 6,
The mux circuit unit,
a TA1 transistor, a TA2 transistor, a TA3 transistor, a TA4 transistor, a TA5 transistor, and a TA6 transistor controlled by the first selection signal;
The plurality of transistors controlled by the second selection signal includes a TB1 transistor, a TB2 transistor, a TB3 transistor, a TB4 transistor, a TB5 transistor, and a TB6 transistor.
8. The method of claim 7,
In the TA1 transistor, the first selection signal is applied to a gate electrode, the first folding data line is connected to a first electrode, and the first connection line is connected to a second electrode,
In the TA2 transistor, the first selection signal is applied to a gate electrode, the second folding data line is connected to a first electrode, and the second connection line is connected to a second electrode,
In the TA3 transistor, the first selection signal is applied to a gate electrode, the third folding data line is connected to a first electrode, and the third connection line is connected to a second electrode,
In the TA4 transistor, the first selection signal is applied to a gate electrode, the fourth folding data line is connected to a first electrode, and the fourth connection line is connected to a second electrode,
In the TA5 transistor, the first selection signal is applied to a gate electrode, the fifth folding data line is connected to a first electrode, and the fifth connection line is connected to a second electrode,
In the TA6 transistor, the first selection signal is applied to a gate electrode, the sixth folding data line is connected to a first electrode, and the sixth connection line is connected to a second electrode,
In the TB1 transistor, the second selection signal is applied to a gate electrode, the first folding data line is connected to a first electrode, and the fourth connection line is connected to a second electrode,
In the TB2 transistor, the second selection signal is applied to a gate electrode, the second folding data line is connected to a first electrode, and the fifth connection line is connected to a second electrode,
In the TB3 transistor, the second selection signal is applied to a gate electrode, the third folding data line is connected to a first electrode, and the sixth connection line is connected to a second electrode,
In the TB4 transistor, the second selection signal is applied to a gate electrode, the fourth folding data line is connected to a first electrode, and the first connection line is connected to a second electrode,
In the TB5 transistor, the second selection signal is applied to a gate electrode, the fifth folding data line is connected to a first electrode, and the second connection line is connected to a second electrode,
In the TB6 transistor, the second selection signal is applied to a gate electrode, the sixth folding data line is connected to a first electrode, and the third connection line is connected to a second electrode.
8. The method of claim 7,
When the display panel is in a folded state,
The first selection signal is a turn-on level, and the second selection signal is a turn-off level.
8. The method of claim 7,
When the display panel is in a non-folding state,
The first selection signal is a turn-off level, and the second selection signal is a turn-on level.
5. The method of claim 4,
In the first folding area,
a plurality of red sub-pixels and a plurality of blue sub-pixels alternately connected to each of the first and third folding data lines, and a plurality of green sub-pixels respectively connected to the second and fourth data lines; placed,
In the second folding area,
a plurality of red sub-pixels and a plurality of blue sub-pixels alternately connected to each of the fifth and seventh folding data lines, and a plurality of green sub-pixels respectively connected to the sixth and eighth data lines; Deployed, foldable display device.
12. The method of claim 11,
the first data integrated circuit is connected to a first connection line, a second connection line, a third connection line, and a fourth connection line;
and the second data integrated circuit is connected to a fifth connection line, a sixth connection line, a seventh connection line, and an eighth connection line.
13. The method of claim 12,
The mux circuit unit,
a TC1 transistor, a TC2 transistor, a TC3 transistor, and a TC4 transistor controlled by a third selection signal;
a TD1 transistor, a TD2 transistor, a TD3 transistor, and a TD4 transistor controlled by a fourth selection signal;
a TE1 transistor, a TE2 transistor, a TE3 transistor, and a TE4 transistor controlled by a fifth select signal;
A foldable display device comprising a TF1 transistor, a TF2 transistor, a TF3 transistor, and a TF4 transistor controlled by a sixth selection signal.
14. The method of claim 13,
In the TC1 transistor, the third selection signal is applied to a gate electrode, the first folding data line is connected to a first electrode, and the first connection line is connected to a second electrode,
In the TC2 transistor, the third selection signal is applied to a gate electrode, the second folding data line is connected to a first electrode, and the second connection line is connected to a second electrode,
In the TC3 transistor, the third selection signal is applied to a gate electrode, the fifth folding data line is connected to the first electrode, and the fifth connection line is connected to a second electrode,
In the TC4 transistor, the third selection signal is applied to a gate electrode, the sixth folding data line is connected to a first electrode, and the sixth connection line is connected to a second electrode,
In the TD1 transistor, the fourth selection signal is applied to a gate electrode, the first folding data line is connected to a first electrode, and the fifth connection line is connected to a second electrode,
In the TD2 transistor, the fourth selection signal is applied to a gate electrode, the second folding data line is connected to a first electrode, and the sixth connection line is connected to a second electrode,
In the TD3 transistor, the fourth selection signal is applied to a gate electrode, the fifth folding data line is connected to a first electrode, and the first connection line is connected to a second electrode,
In the TD4 transistor, the fourth selection signal is applied to a gate electrode, the sixth folding data line is connected to a first electrode, and the second connection line is connected to a second electrode,
In the TE1 transistor, the fifth selection signal is applied to a gate electrode, the third folding data line is connected to the first electrode, and a third connection line is connected to the second electrode,
In the TE2 transistor, the fifth selection signal is applied to a gate electrode, the fourth folding data line is connected to a first electrode, and the fourth connection line is connected to a second electrode,
In the TE3 transistor, the fifth selection signal is applied to a gate electrode, the seventh folding data line is connected to a first electrode, and the seventh connection line is connected to a second electrode,
In the TE4 transistor, the fifth selection signal is applied to a gate electrode, the eighth folding data line is connected to a first electrode, and the eighth connection line is connected to a second electrode,
In the TF1 transistor, the sixth selection signal is applied to the gate electrode, the third folding data line is connected to the first electrode, and the seventh connection line is connected to the second electrode,
In the TF2 transistor, the sixth selection signal is applied to a gate electrode, the fourth folding data line is connected to a first electrode, and the eighth connection line is connected to a second electrode,
In the TF3 transistor, the sixth selection signal is applied to a gate electrode, the seventh folding data line is connected to a first electrode, and the third connection line is connected to a second electrode,
In the TF4 transistor, the sixth selection signal is applied to a gate electrode, the eighth folding data line is connected to a first electrode, and the fourth connection line is connected to a second electrode.
14. The method of claim 13,
When the display panel is in a folded state,
The third selection signal and the fifth selection signal are turn-on levels, and the fourth selection signal and the sixth selection signal are turn-off levels.
14. The method of claim 13,
When the display panel is in a non-folding state,
the fourth selection signal and the fifth selection signal are turn-on levels, and the third selection signal and the sixth selection signal are turn-off levels;
the third selection signal and the sixth selection signal are turn-on levels, and the fourth selection signal and the fifth selection signal are turn-off levels;
The fourth selection signal and the sixth selection signal are turn-on levels, and the fifth selection signal and the sixth selection signal are turn-off levels.

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