CN115632616A - But chip is put in low-power consumption drive of adaptive gain control - Google Patents
But chip is put in low-power consumption drive of adaptive gain control Download PDFInfo
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- CN115632616A CN115632616A CN202211651808.7A CN202211651808A CN115632616A CN 115632616 A CN115632616 A CN 115632616A CN 202211651808 A CN202211651808 A CN 202211651808A CN 115632616 A CN115632616 A CN 115632616A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a low-power-consumption driving and amplifying chip capable of self-adaptive gain control, which belongs to the technical field of integrated circuits and comprises a first switch switching network, a driving stage network, a self-adaptive final stage network, a through network and a second switch switching network. The circuit can be subjected to adaptive gain control according to the input power, so that the output power of the circuit is stable. The circuit of the invention combines the active attenuator and the diode detection circuit, so that the circuit can self-adaptively regulate the gain according to the feedback detection voltage, thereby ensuring that a required optimal input power range can be provided for a power amplifier at the later stage, and ensuring that the power amplifier can have higher output power and smaller nonlinear distortion. Meanwhile, the circuit has the advantages of wide band, low power consumption, small gain fluctuation in frequency band and ideal output power. The high linearity output switch network adopted by the circuit of the invention can bear larger voltage swing and smaller signal distortion.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a low-power-consumption driving and amplifying chip capable of self-adaptive gain control.
Background
When the input power is too high, the power amplifier enters a non-linear region, and the output power of the amplifier contains new frequency components, thereby causing distortion of the output signal, so that if the pre-driver amplifier of the power amplifier can provide a stable optimal power input point for the power amplifier, the non-linear distortion can be reduced. Therefore, for the driving and amplifying chip, if the amplifying capacity can be adjusted in a self-adaptive manner aiming at different input powers, a more stable power is finally output, and the driving and amplifying chip has better significance. Meanwhile, in a radio frequency system, power consumption is a very critical index, so that when the radio frequency amplifier is designed, the efficiency of the whole system can be improved if the low power consumption design can be carried out on the premise of ensuring gain and output power.
Disclosure of Invention
In order to solve the above problems, the present invention provides a low power consumption driving and amplifying chip capable of adaptive gain control.
The technical scheme of the invention is as follows: a low-power-consumption driving and amplifying chip capable of achieving self-adaptive gain control comprises a first switch switching network, a driving stage network, a self-adaptive final stage network, a through network and a second switch switching network;
the input end of the first switch switching network is used as the radio frequency input end of the low-power consumption driving and amplifying chip, the first output end of the first switch switching network is connected with the input end of the driving level network, and the second output end of the first switch switching network is connected with the input end of the through network;
the output end of the second switch switching network is used as the radio frequency output end of the low-power consumption driving and amplifying chip, the first input end of the second switch switching network is connected with the output end of the self-adaptive final-stage network, and the second input end of the second switch switching network is connected with the output end of the through network;
the first output end of the driving stage network is connected with the first input end of the self-adaptive final stage network; the second output of the driver stage network is connected to the second input of the adaptive final stage network.
The invention has the beneficial effects that:
(1) The low-power-consumption driving and amplifying chip has the characteristics of self-adaptive gain control and further stable output power, so that the required optimal input power can be provided for a rear-stage power amplifier, and the rear-stage power amplifier is ensured to have higher output power and smaller nonlinear distortion. Firstly, the driving and amplifying chip selects a chip working channel according to the magnitude of input power, and when the input power is overlarge, a signal can be selected to pass through a direct connection network without any amplification; when the input power is small, the signal is amplified through the driving stage network and then enters the self-adaptive final stage network, and the self-adaptive final stage network combines the active attenuator and the diode detection circuit, so that the circuit can self-adaptively adjust the gain of the circuit according to the feedback detection voltage, and finally the circuit outputs reasonable power;
(2) The circuit has the advantages of wide band, low power consumption, small gain fluctuation in frequency band and high output power. The driving stage adopts a negative feedback structure, so that the gain flatness is effectively improved; the self-adaptive final-stage network adopts a parallel-connection cascode structure, the structure can not only avoid the low breakdown voltage characteristic of an integrated circuit process and improve the reliability and stability of a circuit, but also effectively control power consumption and expand bandwidth, more importantly, the parallel-connection cascode structure also well makes up the defect of steep drop of high-end gain of the frequency of the single cascode structure, and can well improve high-frequency gain and output power. The circuit of the invention also adopts an active bias structure, so that the circuit has a certain temperature compensation effect.
Further, the first switch switching network comprises a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a resistor Rs5, a resistor Rs6, a capacitor C12, a microstrip line TLs1, a switch tube Ms2, a switch tube Ms3, a switch tube Ms4, a switch tube Ms5 and a switch tube Ms6;
one end of the capacitor C12 is used as an input end of the first switch switching network, and the other end thereof is connected with one end of the microstrip line TLs 1; the grid electrode of the switch tube Ms1 is connected with one end of the resistor Rs1, the source electrode of the switch tube Ms1 is respectively connected with the other end of the microstrip line TLs1 and the source electrode of the switch tube Ms4, and the drain electrode of the switch tube Ms2 is used as the second output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms 1; the grid electrode of the switch tube Ms2 is connected with one end of the resistor Rs4, and the source electrode of the switch tube Ms2 is connected with the drain electrode of the switch tube Ms 3; the grid electrode of the switch tube Ms3 is connected with one end of the resistor Rs5, and the source electrode is grounded; the other end of the resistor Rs4 is connected with the other end of the resistor Rs5 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms4 is connected with one end of the resistor Rs2, and the drain electrode of the switch tube Ms4 is connected with the source electrode of the switch tube Ms 5; the grid electrode of the switch tube Ms5 is connected with one end of the resistor Rs3, and the drain electrode of the switch tube Ms5 is used as the first output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms6; the other end of the resistor Rs2 is connected with the other end of the resistor Rs3 and the control voltage Vcon2 respectively; the grid of the switch tube Ms6 is connected with one end of the resistor Rs6, and the source electrode of the switch tube Ms6 is grounded; the other end of the resistor Rs1 is connected to the other end of the resistor Rs6 and the control voltage Vcon1, respectively.
The beneficial effects of the above further scheme are: the circuit of the invention adopts a switch network with high output power and high linear output, and can ensure that the switch can bear larger voltage swing and smaller signal distortion when high power is input.
Further, the driving stage network comprises a resistor R1, a grounding resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a grounding capacitor C4, a grounding inductor Lq1, an inductor Lq2, an inductor Lq3, a microstrip line L1 and a transistor M1;
one end of the capacitor C1 is used as the input end of the driving level network, and the other end of the capacitor C1 is respectively connected with one end of the capacitor C2 and the grounding inductor Lq 1; the grid electrode of the transistor M1 is respectively connected with one end of the resistor R3, one end of the resistor R4 and the other end of the capacitor C2, the source electrode of the transistor M1 is grounded, and the drain electrode of the transistor M1 is respectively connected with one end of the capacitor C3 and one end of the microstrip line L1; the other end of the microstrip line L1 is used as a second output end of the driving-level network and is connected with one end of an inductor Lq 3; the other end of the inductor Lq3 is used as a first output end of the driving level network and is respectively connected with one end of a grounding capacitor C4 and one end of a resistor R1; the other end of the resistor R1 is connected with the other ends of the grounding resistor R2 and the resistor R3 respectively.
The beneficial effects of the further scheme are as follows: the driving stage network carries out preliminary amplification on input signals and adopts a negative feedback structure, thereby effectively improving the gain flatness.
Further, the adaptive last-stage network includes a ground resistor R5, a resistor R6, a resistor R7, a resistor R8, a ground resistor R9, a resistor R10, a resistor R11, a ground resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a ground resistor R17, a ground resistor R18, a capacitor C5, a capacitor C6, a ground capacitor C7, a ground capacitor C8, a ground capacitor C9, a capacitor C10, a ground capacitor C11, a microstrip line L2, a microstrip line L3, an inductor Lq4, an inductor Lq5, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, and a transistor M7;
one end of the resistor R7 is used as a first input end of the self-adaptive final-stage network and is respectively connected with one end of the resistor R8, one end of the resistor R16, the grounded capacitor C9, one end of the inductor Lq4 and the power supply voltage VD; the other end of the resistor R7 is respectively connected with one ends of the grounding resistor R5 and the resistor R6; the grid electrode of the transistor M7 is respectively connected with one end of the resistor R8, one end of the resistor R10 and the drain electrode of the transistor M7, and the source electrode of the transistor M7 is connected with the grounding resistor R9; the grid electrode of the transistor M6 is connected with one end of the resistor R11, the source electrode of the transistor M is connected with the grounding resistor R18, and the drain electrode of the transistor M is respectively connected with one end of the capacitor C5, one end of the capacitor C6 and the other end of the resistor R6; the other end of the capacitor C5 is used as a second input end of the self-adaptive final-stage network; the other end of the capacitor C6 is connected with the other end of the resistor R10 and one end of the microstrip line L2; the grid of the transistor M2 is respectively connected with the other end of the microstrip line L2 and the grid of the transistor M4, the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is respectively connected with the source electrode of the transistor M3, the drain electrode of the transistor M4 and the source electrode of the transistor M5; the source of the transistor M4 is grounded; the gate of the transistor M3 is connected to one end of the resistor R14, one end of the resistor R15, and the gate of the transistor M5, respectively, and the drain thereof is connected to one end of the microstrip line L3, the other end of the inductor Lq4, and the drain of the transistor M5, respectively; the other end of the resistor R14 is connected with the other end of the resistor R16 and a grounding resistor R17 respectively; the other end of the resistor R15 is connected with the grounding capacitor C7; the other end of the resistor R11 is respectively connected with a grounding resistor R12, one end of a resistor R13, a grounding capacitor C8 and the cathode of the diode D5; the anode of the diode D5 is connected with the cathode of the diode D4; the anode of the diode D4 is connected with the cathode of the diode D3; the anode of the diode D3 is connected with the cathode of the diode D2; the anode of the diode D2 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with the other end of the resistor R13, the other end of the microstrip line L3 and one end of the capacitor C10 respectively; the other end of the capacitor C10 is connected with one end of the inductor Lq 5; the other end of the inductor Lq5 is used as the output end of the self-adaptive final stage network and is connected with a grounding capacitor C11.
The beneficial effects of the further scheme are as follows: the circuit self-adaptive final-stage network adopts the active attenuator, can continuously attenuate the gain of the circuit according to the feedback voltage, and the active attenuator divides the voltage by the power supply voltage VD to obtain the drain potential, so that the circuit only needs to adopt a single power supply VD for feeding, and is convenient to use; the adaptive final stage network adopts a diode detection circuit, and the initial attenuation power of the circuit can be selected by selecting the number of diodes and the value of RC, so that the output power range of the circuit can be roughly determined in the design.
Further, the through-network comprises an inductance Lq6;
one end of the inductor Lq6 is used as the input end of the through network, and the other end thereof is used as the output end of the through network.
Further, the second switch switching network comprises a resistor Rs7, a resistor Rs8, a ground resistor Rs9, a resistor Rs10, a resistor Rs11, a resistor Rs12, a capacitor C13, a microstrip line Tls2, a switch tube Ms7, a switch tube Ms8, a switch tube Ms9, a switch tube Ms10, a switch tube Ms11 and a switch tube Ms12;
the grid electrode of the switch tube Ms7 is connected with one end of the resistor Rs 7; the other end of the resistor Rs7 is connected with one end of the resistor Rs10 and the control voltage Vcon1 respectively, the source electrode of the resistor Rs7 is connected with one end of the microstrip line TLs2 and the source electrode of the switch tube Ms10 respectively, and the drain electrode of the resistor Rs7 is used as the second input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms 8; the grid electrode of the switch tube Ms8 is connected with one end of the resistor Rs8, and the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the grid electrode of the switch tube Ms9 is connected with one end of the resistor Rs9, and the source electrode of the switch tube Ms9 is grounded; the other end of the resistor Rs8 is connected with the other end of the resistor Rs9 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms10 is connected with one end of the resistor Rs12, and the drain electrode of the switch tube Ms10 is connected with the source electrode of the switch tube Ms 11; the grid electrode of the switch tube Ms11 is connected with one end of the resistor Rs11, and the drain electrode of the switch tube Ms11 is used as the first input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms12; the grid electrode of the switch tube Ms12 is connected with the other end of the resistor Rs10, and the source electrode of the switch tube Ms is grounded; the other end of the resistor Rs11 is connected with the other end of the resistor Rs12 and the control voltage Vcon2 respectively; the other end of the microstrip line Tls2 is connected with one end of a capacitor C13; the other end of the capacitor C13 serves as an output terminal of the second switching network.
Drawings
Fig. 1 is a schematic block diagram of a low-power-consumption driver/amplifier chip capable of adaptive gain control according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a low power consumption driver/amplifier chip capable of adaptive gain control according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a low power consumption driving and amplifying chip with adaptive gain control, which includes a first switch switching network, a driving stage network, an adaptive final stage network, a pass-through network, and a second switch switching network;
the input end of the first switch switching network is used as the radio frequency input end of the low-power consumption driving and amplifying chip, the first output end of the first switch switching network is connected with the input end of the driving level network, and the second output end of the first switch switching network is connected with the input end of the through network;
the output end of the second switch switching network is used as the radio frequency output end of the low-power consumption driving and amplifying chip, the first input end of the second switch switching network is connected with the output end of the self-adaptive final-stage network, and the second input end of the second switch switching network is connected with the output end of the through network;
the first output end of the driving stage network is connected with the first input end of the self-adaptive final stage network; the second output of the driver stage network is connected to the second input of the adaptive final stage network.
In the embodiment of the present invention, as shown in fig. 2, the first switch switching network includes a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a resistor Rs5, a resistor Rs6, a capacitor C12, a microstrip line TLs1, a switch tube Ms2, a switch tube Ms3, a switch tube Ms4, a switch tube Ms5, and a switch tube Ms6;
one end of the capacitor C12 is used as an input end of the first switch switching network, and the other end thereof is connected with one end of the microstrip line TLs 1; the grid electrode of the switch tube Ms1 is connected with one end of the resistor Rs1, the source electrode of the switch tube Ms1 is respectively connected with the other end of the microstrip line TLs1 and the source electrode of the switch tube Ms4, and the drain electrode of the switch tube Ms2 is used as the second output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms 1; the grid electrode of the switch tube Ms2 is connected with one end of the resistor Rs4, and the source electrode of the switch tube Ms2 is connected with the drain electrode of the switch tube Ms 3; the grid electrode of the switch tube Ms3 is connected with one end of the resistor Rs5, and the source electrode of the switch tube Ms is grounded; the other end of the resistor Rs4 is connected with the other end of the resistor Rs5 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms4 is connected with one end of the resistor Rs2, and the drain electrode of the switch tube Ms4 is connected with the source electrode of the switch tube Ms 5; the grid electrode of the switch tube Ms5 is connected with one end of the resistor Rs3, and the drain electrode of the switch tube Ms5 is used as the first output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms6; the other end of the resistor Rs2 is connected with the other end of the resistor Rs3 and the control voltage Vcon2 respectively; the grid of the switch tube Ms6 is connected with one end of the resistor Rs6, and the source electrode of the switch tube Ms6 is grounded; the other end of the resistor Rs1 is connected to the other end of the resistor Rs6 and the control voltage Vcon1, respectively.
In the embodiment of the present invention, as shown in fig. 2, the driver stage network includes a resistor R1, a ground resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a ground capacitor C4, a ground inductor Lq1, an inductor Lq2, an inductor Lq3, a microstrip line L1, and a transistor M1;
one end of the capacitor C1 is used as the input end of the driving level network, and the other end of the capacitor C1 is respectively connected with one end of the capacitor C2 and the grounding inductor Lq 1; the grid of the transistor M1 is respectively connected with one end of the resistor R3, one end of the resistor R4 and the other end of the capacitor C2, the source electrode of the transistor M is grounded, and the drain electrode of the transistor M is respectively connected with one end of the capacitor C3 and one end of the microstrip line L1; the other end of the microstrip line L1 is used as a second output end of the driving stage network and is connected with one end of the inductor Lq 3; the other end of the inductor Lq3 is used as a first output end of the driving level network and is respectively connected with one end of a grounding capacitor C4 and one end of a resistor R1; the other end of the resistor R1 is connected with the other ends of the grounding resistor R2 and the resistor R3 respectively.
In the embodiment of the present invention, as shown in fig. 2, the adaptive last-stage network includes a ground resistor R5, a resistor R6, a resistor R7, a resistor R8, a ground resistor R9, a resistor R10, a resistor R11, a ground resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a ground resistor R17, a ground resistor R18, a capacitor C5, a capacitor C6, a ground capacitor C7, a ground capacitor C8, a ground capacitor C9, a capacitor C10, a ground capacitor C11, a microstrip line L2, a microstrip line L3, an inductor Lq4, an inductor Lq5, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, and a transistor M7;
one end of the resistor R7 is used as a first input end of the self-adaptive final-stage network and is respectively connected with one end of the resistor R8, one end of the resistor R16, the grounded capacitor C9, one end of the inductor Lq4 and the power supply voltage VD; the other end of the resistor R7 is respectively connected with one ends of the grounding resistor R5 and the resistor R6; the grid electrode of the transistor M7 is respectively connected with one end of the resistor R8, one end of the resistor R10 and the drain electrode of the transistor M7, and the source electrode of the transistor M7 is connected with the grounding resistor R9; the grid electrode of the transistor M6 is connected with one end of the resistor R11, the source electrode of the transistor M is connected with the grounding resistor R18, and the drain electrode of the transistor M is respectively connected with one end of the capacitor C5, one end of the capacitor C6 and the other end of the resistor R6; the other end of the capacitor C5 is used as a second input end of the self-adaptive final-stage network; the other end of the capacitor C6 is connected with the other end of the resistor R10 and one end of the microstrip line L2; the grid of the transistor M2 is respectively connected with the other end of the microstrip line L2 and the grid of the transistor M4, the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is respectively connected with the source electrode of the transistor M3, the drain electrode of the transistor M4 and the source electrode of the transistor M5; the source of the transistor M4 is grounded; the gate of the transistor M3 is connected to one end of the resistor R14, one end of the resistor R15, and the gate of the transistor M5, respectively, and the drain thereof is connected to one end of the microstrip line L3, the other end of the inductor Lq4, and the drain of the transistor M5, respectively; the other end of the resistor R14 is connected with the other end of the resistor R16 and a grounding resistor R17 respectively; the other end of the resistor R15 is connected with a grounding capacitor C7; the other end of the resistor R11 is respectively connected with a grounding resistor R12, one end of a resistor R13, a grounding capacitor C8 and the cathode of the diode D5; the anode of the diode D5 is connected with the cathode of the diode D4; the anode of the diode D4 is connected with the cathode of the diode D3; the anode of the diode D3 is connected with the cathode of the diode D2; the anode of the diode D2 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with the other end of the resistor R13, the other end of the microstrip line L3 and one end of the capacitor C10 respectively; the other end of the capacitor C10 is connected with one end of the inductor Lq 5; the other end of the inductor Lq5 is used as the output end of the self-adaptive final stage network and is connected with a grounding capacitor C11.
In an embodiment of the present invention, as shown in fig. 2, the pass-through network includes an inductance Lq6;
one end of the inductor Lq6 is used as an input end of the through network, and the other end of the inductor Lq6 is used as an output end of the through network.
In the embodiment of the present invention, as shown in fig. 2, the second switch switching network includes a resistor Rs7, a resistor Rs8, a ground resistor Rs9, a resistor Rs10, a resistor Rs11, a resistor Rs12, a capacitor C13, a microstrip line Tls2, a switch tube Ms7, a switch tube Ms8, a switch tube Ms9, a switch tube Ms10, a switch tube Ms11, and a switch tube Ms12;
the grid electrode of the switch tube Ms7 is connected with one end of the resistor Rs 7; the other end of the resistor Rs7 is connected with one end of the resistor Rs10 and the control voltage Vcon1 respectively, the source electrode of the resistor Rs7 is connected with one end of the microstrip line TLs2 and the source electrode of the switch tube Ms10 respectively, and the drain electrode of the resistor Rs7 is used as the second input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms 8; the grid electrode of the switch tube Ms8 is connected with one end of the resistor Rs8, and the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the grid electrode of the switch tube Ms9 is connected with one end of the resistor Rs9, and the source electrode of the switch tube Ms9 is grounded; the other end of the resistor Rs8 is connected with the other end of the resistor Rs9 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms10 is connected with one end of the resistor Rs12, and the drain electrode of the switch tube Ms10 is connected with the source electrode of the switch tube Ms 11; the grid electrode of the switch tube Ms11 is connected with one end of the resistor Rs11, and the drain electrode of the switch tube Ms11 is used as the first input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms12; the grid electrode of the switch tube Ms12 is connected with the other end of the resistor Rs10, and the source electrode of the switch tube Ms is grounded; the other end of the resistor Rs11 is connected with the other end of the resistor Rs12 and the control voltage Vcon2 respectively; the other end of the microstrip line Tls2 is connected with one end of a capacitor C13; the other end of the capacitor C13 serves as an output terminal of the second switching network.
The following describes the working principle and process of the present invention with reference to fig. 2:
the first switch switching network and the second switch switching network both adopt an unbalanced serial-parallel combination structure, and both the two switch switching networks have high isolation. When the input signal is too large, the signal enters the through network through the first switch switching network without any amplification, and is finally output from the second switch switching network through the radio frequency output end. The branch circuits of the two switch switching networks for connecting the direct connection network respectively adopt a series switch tube and two parallel switch tubes, which not only can bear larger power, but also have higher linear output capability, thereby ensuring smaller distortion of input signals, when the channel works, two series tubes Ms1 and Ms7 are opened, parallel tubes Ms2 and Ms3, ms8 and Ms9 are turned off, the series tube corresponding to the other branch circuit is turned off, and the parallel tubes are opened. When a signal is small and needs to be amplified, the signal is input from the first switch switching network to the driving stage network, then is amplified by the self-adaptive final stage network and is output from the second switch switching network, the branches of the first switch switching network and the second switch switching network through which the signal passes at the moment are respectively provided with two series switch tubes and one parallel switch tube, and similarly, the series switch tubes on the branches at the moment are opened, the parallel switch tubes are closed, the series tubes of the other branch correspondingly connected with the through network are closed, and the parallel tubes are opened.
In the driving stage network, the capacitors C1-C2 and the grounding inductor Lq1 form input matching, the stage is used for improving the link gain and providing certain driving power for the self-adaptive final stage network, and meanwhile, the transistor M1 adopts a negative feedback structure and consists of a capacitor C3, an inductor Lq2 and a resistor R4, so that the gain flatness and the input standing wave are effectively improved. The drain voltage of the transistor M1 is provided by the power supply voltage VD through an inductor Lq3, and C4 is a filter capacitor; the gate voltage is obtained by dividing the power supply voltage VD by resistors R1 and R2.
In the adaptive final stage network, the cascode structure of a single large tube is changed into a parallel cascode structure of a small tube. The structure can not only avoid the low breakdown voltage characteristic of the integrated circuit process, improve the reliability and stability of the circuit, but also effectively reduce the power consumption and expand the bandwidth, and more importantly, because the high-frequency bandwidth of the large tube of the small tube is wider, the parallel cascode structure also better makes up the defect of the steep drop of the high-end gain of the cascode structure of the single large tube, and can well improve the high-frequency gain and the output power. The common source tubes are M2 and M4 connected in parallel, and the common gate tubes are M3 and M5 connected in parallel. The drain voltage of the common-gate tube is provided by the power supply voltage VD through the inductor Lq4, and the grid voltage of the common-source tube is obtained by the power supply voltage VD through the voltage division of the resistor R8 and the active tube M7. Due to the adoption of active bias, when the grid voltage fluctuates due to temperature fluctuation, the grid voltage can be subjected to certain temperature compensation through the adjustment of the active tube M7, so that the electrical property is stable. The capacitors C10-C11 and the inductor Lq5 constitute the output matching of the circuit.
The output end of the parallel cascode structure is connected with a diode detection structure, D1-D5 are detection diodes, and a resistor R12 and a capacitor C8 are low-frequency filter structures. The detector structure can detect different DC voltages for different output powers of the circuit and feed back the voltages to transistor M6 as its gate voltage. M6 is an enhancement type amplifier tube, and the leakage voltage is obtained by dividing the voltage of a power supply voltage VD through resistors R7 and R5 for the convenience of use and circuit simplification. The gate voltage fed back to the transistor M6 determines the conduction state and different conduction impedances of the transistor, so that continuous attenuation of signals is realized, adaptive gain control of the circuit is further completed, and finally adjustment of output power is completed through amplification of different gains. Because the power and the voltage of the diode detection structure are in one-to-one correspondence, and the slope of the diode detection structure can be adjusted through the number of the diodes and the size of the resistor, the initial power of attenuation can be roughly determined in design, when the initial power is larger than the initial power, the detection structure feeds back a voltage to enable the transistor M6 to gradually start the attenuation function, the attenuation is larger when the voltage is larger as the power is larger, when the power is smaller, the attenuation reduction gain is larger, the power is larger, and the power is larger like a power negative feedback effect, and finally the output power is stabilized in a rough range.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (6)
1. A low-power consumption driving and amplifying chip capable of self-adaptive gain control is characterized by comprising a first switch switching network, a driving stage network, a self-adaptive final stage network, a through network and a second switch switching network;
the input end of the first switch switching network is used as the radio frequency input end of the low-power-consumption driving and amplifying chip, the first output end of the first switch switching network is connected with the input end of the driving level network, and the second output end of the first switch switching network is connected with the input end of the through network;
the output end of the second switch switching network is used as the radio frequency output end of the low-power-consumption driving and amplifying chip, the first input end of the second switch switching network is connected with the output end of the self-adaptive final-stage network, and the second input end of the second switch switching network is connected with the output end of the through network;
the first output end of the driving stage network is connected with the first input end of the self-adaptive final stage network; a second output of the driver stage network is connected to a second input of the adaptive final stage network.
2. The low power consumption driver amplifier chip according to claim 1, wherein the first switching network comprises a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a resistor Rs5, a resistor Rs6, a capacitor C12, a microstrip line TLs1, a switching tube Ms2, a switching tube Ms3, a switching tube Ms4, a switching tube Ms5, and a switching tube Ms6;
one end of the capacitor C12 serves as an input end of the first switch switching network, and the other end of the capacitor C12 is connected with one end of the microstrip line TLs 1; the grid electrode of the switch tube Ms1 is connected with one end of the resistor Rs1, the source electrode of the switch tube Ms1 is respectively connected with the other end of the microstrip line TLs1 and the source electrode of the switch tube Ms4, and the drain electrode of the switch tube Ms1 is used as the second output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms 2; the grid electrode of the switch tube Ms2 is connected with one end of the resistor Rs4, and the source electrode of the switch tube Ms2 is connected with the drain electrode of the switch tube Ms 3; the grid electrode of the switch tube Ms3 is connected with one end of the resistor Rs5, and the source electrode of the switch tube Ms is grounded; the other end of the resistor Rs4 is connected with the other end of the resistor Rs5 and a control voltage Vcon2 respectively; the grid electrode of the switch tube Ms4 is connected with one end of the resistor Rs2, and the drain electrode of the switch tube Ms4 is connected with the source electrode of the switch tube Ms 5; the grid electrode of the switch tube Ms5 is connected with one end of the resistor Rs3, and the drain electrode of the switch tube Ms5 is used as the first output end of the first switch switching network and is connected with the drain electrode of the switch tube Ms6; the other end of the resistor Rs2 is connected with the other end of the resistor Rs3 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms6 is connected with one end of the resistor Rs6, and the source electrode of the switch tube Ms6 is grounded; the other end of the resistor Rs1 is connected to the other end of the resistor Rs6 and the control voltage Vcon1, respectively.
3. The low-power-consumption driving and discharging chip according to claim 1, wherein the driving stage network comprises a resistor R1, a grounding resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a grounding capacitor C4, a grounding inductor Lq1, an inductor Lq2, an inductor Lq3, a microstrip line L1 and a transistor M1;
one end of the capacitor C1 is used as an input end of the driving level network, and the other end of the capacitor C1 is respectively connected with one end of the capacitor C2 and the grounding inductor Lq 1; the grid electrode of the transistor M1 is respectively connected with one end of the resistor R3, one end of the resistor R4 and the other end of the capacitor C2, the source electrode of the transistor M is grounded, and the drain electrode of the transistor M is respectively connected with one end of the capacitor C3 and one end of the microstrip line L1; the other end of the microstrip line L1 is used as a second output end of the driving stage network and is connected with one end of an inductor Lq 3; the other end of the inductor Lq3 is used as a first output end of the driving level network and is respectively connected with one end of a grounding capacitor C4 and one end of a resistor R1; the other end of the resistor R1 is connected with the other ends of the grounding resistor R2 and the resistor R3 respectively.
4. The low power consumption discharge chip according to claim 1, wherein the adaptive last stage network comprises a ground resistor R5, a resistor R6, a resistor R7, a resistor R8, a ground resistor R9, a resistor R10, a resistor R11, a ground resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a ground resistor R17, a ground resistor R18, a capacitor C5, a capacitor C6, a ground capacitor C7, a ground capacitor C8, a ground capacitor C9, a capacitor C10, a ground capacitor C11, a microstrip line L2, a microstrip line L3, an inductor Lq4, an inductor Lq5, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, and a transistor M7;
one end of the resistor R7 is used as a first input end of the self-adaptive final stage network and is respectively connected with one end of a resistor R8, one end of a resistor R16, a grounded capacitor C9, one end of an inductor Lq4 and a power supply voltage VD; the other end of the resistor R7 is connected with one ends of a grounding resistor R5 and a resistor R6 respectively; the grid electrode of the transistor M7 is respectively connected with one end of the resistor R8, one end of the resistor R10 and the drain electrode of the transistor M7, and the source electrode of the transistor M7 is connected with the grounding resistor R9; the grid electrode of the transistor M6 is connected with one end of the resistor R11, the source electrode of the transistor M6 is connected with the grounding resistor R18, and the drain electrode of the transistor M6 is respectively connected with one end of the capacitor C5, one end of the capacitor C6 and the other end of the resistor R6; the other end of the capacitor C5 is used as a second input end of the self-adaptive final-stage network; the other end of the capacitor C6 is connected with the other end of the resistor R10 and one end of the microstrip line L2; the grid electrode of the transistor M2 is respectively connected with the other end of the microstrip line L2 and the grid electrode of the transistor M4, the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is respectively connected with the source electrode of the transistor M3, the drain electrode of the transistor M4 and the source electrode of the transistor M5; the source electrode of the transistor M4 is grounded; the grid electrode of the transistor M3 is respectively connected with one end of the resistor R14, one end of the resistor R15 and the grid electrode of the transistor M5, and the drain electrode of the transistor M3 is respectively connected with one end of the microstrip line L3, the other end of the inductor Lq4 and the drain electrode of the transistor M5; the other end of the resistor R14 is connected with the other end of the resistor R16 and a grounding resistor R17 respectively; the other end of the resistor R15 is connected with a grounding capacitor C7; the other end of the resistor R11 is respectively connected with a grounding resistor R12, one end of a resistor R13, a grounding capacitor C8 and the cathode of the diode D5; the anode of the diode D5 is connected with the cathode of the diode D4; the anode of the diode D4 is connected with the cathode of the diode D3; the anode of the diode D3 is connected with the cathode of the diode D2; the anode of the diode D2 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with the other end of the resistor R13, the other end of the microstrip line L3 and one end of the capacitor C10 respectively; the other end of the capacitor C10 is connected with one end of an inductor Lq 5; and the other end of the inductor Lq5 is used as the output end of the self-adaptive final-stage network and is connected with a grounding capacitor C11.
5. The low-power-consumption driving and discharging chip according to claim 1, wherein the through network comprises an inductor Lq6;
one end of the inductor Lq6 is used as an input end of the through network, and the other end of the inductor Lq6 is used as an output end of the through network.
6. The low-power-consumption discharge driving chip according to claim 1, wherein the second switching network comprises a resistor Rs7, a resistor Rs8, a grounding resistor Rs9, a resistor Rs10, a resistor Rs11, a resistor Rs12, a capacitor C13, a microstrip line Tls2, a switching tube Ms7, a switching tube Ms8, a switching tube Ms9, a switching tube Ms10, a switching tube Ms11, and a switching tube Ms12;
the grid electrode of the switch tube Ms7 is connected with one end of the resistor Rs 7; the other end of the resistor Rs7 is connected with one end of a resistor Rs10 and the control voltage Vcon1 respectively, the source electrode of the resistor Rs is connected with one end of a microstrip line TLs2 and the source electrode of the switch tube Ms10 respectively, and the drain electrode of the resistor Rs is used as the second input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms 8; the grid electrode of the switch tube Ms8 is connected with one end of the resistor Rs8, and the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the grid electrode of the switch tube Ms9 is connected with one end of the resistor Rs9, and the source electrode of the switch tube Ms9 is grounded; the other end of the resistor Rs8 is connected with the other end of the resistor Rs9 and the control voltage Vcon2 respectively; the grid electrode of the switch tube Ms10 is connected with one end of the resistor Rs12, and the drain electrode of the switch tube Ms10 is connected with the source electrode of the switch tube Ms 11; the grid electrode of the switch tube Ms11 is connected with one end of the resistor Rs11, and the drain electrode of the switch tube Ms11 is used as the first input end of the second switch switching network and is connected with the drain electrode of the switch tube Ms12; the grid electrode of the switch tube Ms12 is connected with the other end of the resistor Rs10, and the source electrode of the switch tube Ms is grounded; the other end of the resistor Rs11 is connected with the other end of the resistor Rs12 and the control voltage Vcon2 respectively; the other end of the microstrip line Tls2 is connected with one end of a capacitor C13; the other end of the capacitor C13 serves as an output end of the second switching network.
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