CN115621242A - Substrate with low warping stress, preparation method, packaging structure and electronic product - Google Patents
Substrate with low warping stress, preparation method, packaging structure and electronic product Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 114
- 238000002360 preparation method Methods 0.000 title claims abstract description 5
- 238000004806 packaging method and process Methods 0.000 title abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 242
- 239000002184 metal Substances 0.000 claims abstract description 109
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 239000012792 core layer Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 37
- 229910052802 copper Inorganic materials 0.000 claims description 37
- 239000010949 copper Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 36
- 238000012545 processing Methods 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 abstract description 9
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 7
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- 238000003475 lamination Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- FTQWRYSLUYAIRQ-UHFFFAOYSA-N n-[(octadecanoylamino)methyl]octadecanamide Chemical compound CCCCCCCCCCCCCCCCCC(=O)NCNC(=O)CCCCCCCCCCCCCCCCC FTQWRYSLUYAIRQ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention discloses a substrate with low warping stress, a preparation method, a packaging structure and an electronic product. The substrate comprises an intermediate core layer, a conductive through hole, a first surface dielectric layer, a second surface dielectric layer and 2N metal layers, wherein N is a positive integer, the first surface dielectric layer is arranged on the first surface of the intermediate core layer, the second surface dielectric layer is arranged on the second surface of the intermediate core layer, the first surface is used for connecting a chip, the second surface is the surface, opposite to the first surface, of the intermediate core layer and used for connecting the substrate, and the thermal expansion coefficient of the second surface dielectric layer is different from that of the first surface dielectric layer. The substrate provided by the invention can avoid the problem of insufficient soldering caused by warpage matching, and the yield is improved.
Description
Technical Field
The invention relates to a substrate with low warpage stress, a preparation method of the substrate with low warpage stress, a packaging structure comprising the substrate with low warpage stress and an electronic product, and belongs to the technical field of semiconductor packaging.
Background
Flip Chip (abbreviated FC) technology is a mainstream advanced packaging technology. The technology is to grow bumps (Bump) on the front surface of a chip, and then flip the chip to make the bumps and a substrate flip-chip bonding (FC Bond) complete interconnection. Compared with a traditional Wire Bonding interconnection mode, the FC technology brings more IO interfaces, and has better electrical and heat dissipation performance, so that the FC interconnection mode is widely applied to the market. At present, the common Flip-Chip packaging methods include two methods, namely FCCSP (Flip Chip Scale Package) and FCBGA (Flip Chip Ball Grid Array), wherein the FCCSP is generally applied to products with small-sized bare chips; while FCBGAs are typically used in bare chip products having large dimensions. The biggest feature of both FCCSP and FCBGA during flip-chip Bonding is that FCCSP performs Bonding on a Substrate strip (Substrate strip), while FCBGA performs Bonding on a Substrate strip cut Shan Houcheng as a Single Unit (Single Unit).
The false soldering is a package failure phenomenon commonly existing in the current FC technology, and the causes thereof are very complex and various, wherein the most common cause is that the warpage of the chip and the warpage of the substrate are not matched in the flip chip bonding process, so that the local bump is not soldered, or the internal stress after soldering is large and cracks. Generally speaking, the front surface of the chip is coated with a metal layer, and the thermal expansion coefficient of the chip material such as Si, gaAs and ceramic substrate material is 3 × 10 -6 K to 7X 10 -6 between/K, the metal layer usually has a thermal expansion coefficient of 10X 10 -6 More than/K, which is much larger than the silicon substrate, the reflow process of the flip chip bonding chip is easy to present smiling face-like Warpage (Smile warp), and the substrate usually presents crying face-like Warpage (Cry warp) due to the substrate process; thus, the bumps at the chip edge are easily cold-bonded (as shown in fig. 1).
In chinese patent No. ZL 200410063721.3, a package structure for preventing warpage is disclosed, which includes a plurality of chips and a reinforcing member. The plurality of chips are arranged on the upper surface of the packaging substrate, and the reinforcing member is fixed on the peripheral area of the lower surface of the packaging substrate corresponding to the chips in a surrounding mode. By the arrangement of the reinforcing member and the encapsulation, the warpage stress on the substrate caused by the encapsulation process of the chip can be prevented.
Disclosure of Invention
The invention provides a substrate with low warpage stress.
Another technical problem to be solved by the present invention is to provide a method for manufacturing a substrate with low warpage stress.
Another technical problem to be solved by the present invention is to provide a package structure including the substrate.
Another object of the present invention is to provide an electronic product including the substrate.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
according to a first aspect of the embodiments of the present invention, there is provided a substrate with low warpage stress, comprising an intermediate core layer, a conductive via, a first surface dielectric layer, a second surface dielectric layer and 2N metal layers, wherein N is a positive integer,
the first surface dielectric layer is on a first surface of the intermediate core layer and the second surface dielectric layer is on a second surface of the intermediate core layer,
the first surface is used for connecting a chip,
the second surface is a surface of the intermediate core layer opposite to the first surface for connection to a substrate,
the second surface dielectric layer has a coefficient of thermal expansion different from a coefficient of thermal expansion of the first surface dielectric layer.
Preferably, the thermal expansion coefficient of the second surface dielectric layer is larger than that of the first surface dielectric layer.
Wherein preferably, the first surface dielectric layer comprises at least a first dielectric layer,
the second surface dielectric layer comprises at least a second dielectric layer,
the second dielectric layer and the first dielectric layer have different coefficients of thermal expansion.
Preferably, the coefficient of thermal expansion of the second dielectric layer is greater than the coefficient of thermal expansion of the second dielectric layer.
Preferably, the thermal expansion coefficient of the second dielectric layer is more than 1.3 times of the thermal expansion coefficient of the second dielectric layer.
Preferably, the thickness of the second surface dielectric layer is greater than that of the first surface dielectric layer.
Preferably, the thickness of the second surface dielectric layer is increased by 5-25 um compared with the thickness of the first surface dielectric layer.
Preferably, the 2N metal layers comprise a first metal layer and a third metal layer,
the first metal layer is formed on the first surface, the third metal layer is formed on the second surface, and the first metal layer and the third metal layer are connected through the conductive via.
Preferably, the copper content of the first metal layer is different from the copper content of the third metal layer.
Preferably, the 2N metal layers further comprise a second metal layer and a fourth metal layer,
the second metal layer is positioned on the first surface; the fourth metal layer is located on the second surface,
and the sum of the copper contents of the first metal layer and the second metal layer is less than the sum of the copper contents of the third metal layer and the fourth metal layer.
According to a second aspect of the embodiments of the present invention, there is provided a method for manufacturing a substrate with low warpage stress, including the steps of:
s1: forming a first metal layer on a first surface of an intermediate core layer, a third metal layer on a second surface of the intermediate core layer, and a conductive via penetrating the first surface and the second surface, the second surface being opposite to the first surface;
s2: forming a first dielectric layer covering the second metal layer and a second dielectric layer covering the third metal layer by using a laminating process, wherein the material of the first dielectric layer and the material of the second dielectric layer have different thermal expansion coefficients;
s3: and finishing the processing of other substrate layers and subsequent processing processes.
Wherein preferably the first metal layer and the third metal layer have different copper contents.
According to a third aspect of the embodiments of the present invention, a package structure is provided, which includes the substrate with low warpage stress, and a chip connected to the substrate.
According to a fourth aspect of the embodiments of the present invention, an electronic product is provided, wherein the electronic product includes the substrate with low warpage stress.
Compared with the prior art, the invention ensures that the substrate is easy to show smiling face-shaped warping or crying face-shaped warping in the high-temperature reflow soldering process by adopting the dielectric layer materials with different thermal expansion coefficients at the two sides of the substrate and adopting the materials with different copper contents at the two sides of the substrate, thereby matching with the smiling face-shaped warping of a bare chip and avoiding the problem of insufficient soldering caused by mismatching of the warping. Therefore, the substrate with low warpage stress provided by the embodiment of the invention can avoid the problem of insufficient soldering caused by warpage matching, and the yield is improved.
Drawings
FIG. 1 is a schematic view of a cold joint caused by different deformations of a chip and a substrate;
FIG. 2 is a schematic view of a substrate with low warpage stress according to a first embodiment of the present invention;
FIG. 3 is a schematic view of a substrate with low warpage stress according to a second embodiment of the present invention;
FIG. 4 is a diagram illustrating the formation of a first metal layer and a third metal layer in a method for manufacturing a substrate with low warpage stress according to a fourth embodiment of the present invention;
FIG. 5 is a schematic view of a lamination step of a method for manufacturing a substrate with low warpage stress according to a fourth embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a subsequent step of a method for manufacturing a substrate with low warpage stress according to a fourth embodiment of the present invention;
fig. 7 is a diagram illustrating a package structure including a substrate with low warpage stress according to a fifth embodiment of the present invention.
Detailed Description
The technical contents of the invention are described in detail below with reference to the accompanying drawings and specific embodiments.
< first embodiment >
As shown in fig. 2, the substrate 100 with low warpage stress according to the embodiment of the invention includes an intermediate Core layer (CCL or BT Core) 1, a conductive via 11, 2M dielectric layers, and 2N metal layers, where M and N are positive integers.
The intermediate core layer 1 has a first surface and a second surface opposite to the first surface, and a conductive via 11 penetrating the first surface and the second surface. In this embodiment, the first surface is a side where the chip is located, and the second surface is a side where the printed circuit board is located.
The 2M dielectric layer comprises a first surface dielectric layer and a second surface dielectric layer which are symmetrically arranged. The first surface dielectric layer is an M dielectric layer positioned on the first surface of the middle core layer 1; the second surface dielectric layer is an M-layer dielectric layer located on the second surface of the middle core layer 1, where M is a positive integer.
The 2N metal layers are symmetrically arranged on the first surface metal layer and the second surface metal layer. The first surface metal layer is an N-layer metal layer positioned on the first surface of the middle core layer 1; the second surface metal layer is N metal layers located on the second surface of the middle core layer 1, and N is a positive integer.
In the present embodiment, the first surface dielectric layer is referred to as a first dielectric layer 21; the second surface dielectric layer is referred to as the second dielectric layer 22, i.e., M =1. The first surface metal layer refers to the first metal layer 211 and the second metal layer 212; the second surface metal layer refers to the third metal layer 221 and the fourth metal layer 222.
A first dielectric layer 21 overlies the first surface and a second dielectric layer 22 overlies the second surface. The first metal layer 211 is formed on the first surface, and the third metal layer 221 is formed on the second surface. And the first metal layer 211 and the third metal layer 221 are connected through the conductive via 11.
The first dielectric layer 21 covers the first surface of the intermediate core layer 1, and a first conductive hole 210 penetrating through the first dielectric layer 21 is formed therein. The second metal layer 212 is located on the upper surface of the first dielectric layer 21, and the first solder resist layer 31 covers the first dielectric layer 21. The first conductive via 210 connects the first metal layer 211 and the second metal layer 212. A chip (not shown) is connected to the second metal layer 212 by soldering or mounting.
The second dielectric layer 22, which covers the second surface of the middle core layer 1, has a second conductive hole 220 penetrating through the first dielectric layer 22. The third metal layer 221 and the fourth metal layer 222 are located on the surface of the second dielectric layer 22, and the second solder resist layer 32 covers the fourth metal layer 222. The second conductive via 220 connects the third metal layer 221 and the fourth metal layer 222. The substrate is connected to a printed circuit board or the like through the fourth metal layer 222.
The intermediate core layer 1 is a substrate having a low thermal expansion coefficient, such as a Copper Clad Laminate (CCL) or a BT (bis amide Triazine) board, but is not limited thereto, and may be a substrate having a relatively high thermal expansion coefficient. The first dielectric layer 21 on the first surface of the middle core layer 1 and the second dielectric layer 22 on the second surface of the middle core layer 1 are made of different materials, and the thermal expansion coefficient (thermal expansion coefficient) of the material of the second dielectric layer 22 is higher than that of the material of the first dielectric layer 21, so that the substrate is warped like a smile when being heated. Since the thermal expansion coefficient of the material of the second dielectric layer 22 is larger than that of the material of the first dielectric layer 21, the deformation at high temperature is larger, so that the substrate is warped like a smile. Preferably, the thermal expansion coefficient of the material of the second dielectric layer 22 is 1.2 times or more, more preferably 1.3 times or more, the thermal expansion coefficient of the material of the first dielectric layer 21, and the desired effect can be obtained. Those skilled in the art will appreciate that the coefficient of thermal expansion of the material of the second dielectric layer 22 is selected as the difference between the coefficients of thermal expansion of the materials of the first dielectric layer 21, and can be obtained by numerical simulation analysis depending on the required chip warpage, substrate thickness, and the like.
It should be noted that, in different embodiments of the present invention, the thicknesses of the dielectric layers of the first surface and the second surface of the intermediate core layer 1 are the same, but this does not limit the present invention. If the thicknesses of the dielectric layer material on the second surface are increased to be larger than that of the dielectric layer material on the first surface under the condition that the thicknesses are different, the smiling face-like warpage is more remarkably realized. In the present embodiment, the thickness of the dielectric layer material on the second surface is increased by 5 to 25um compared with the thickness of the dielectric layer material on the first surface in consideration of the actual processing and design conditions, but this does not limit the present invention, and may be increased or decreased as appropriate according to the actual conditions.
Further, the copper content on the first surface of the intermediate core layer 1 includes the sum of the copper contents of the first metal layer 211, the second metal layer 212, and the first conductive via 210. The copper content of the second surface of the intermediate core layer 1 includes the sum of the copper contents of the third metal layer 221, the fourth metal layer 222 and the second conductive via 220. It will be appreciated that if a copper containing composition is included in the first dielectric layer 21, the copper content to the first surface of the intermediate core layer 1 should also be calculated; similarly, if a composition including copper is included in the second dielectric layer 22, the copper content to the second surface of the intermediate core layer 1 should also be calculated.
In the substrate 100 with low warpage stress provided in the embodiment of the present invention, preferably, a difference obtained by subtracting the copper content of the first surface of the intermediate core layer 1 from the copper content of the second surface of the intermediate core layer 1 reaches a predetermined value (greater than zero), and the predetermined value is obtained by comprehensive calculation according to factors such as an expected chip warpage degree and a substrate size. The chip warpage degree refers to the size and shape of warpage of a chip carried by the substrate in a process of mounting the chip on the substrate. More preferably, the second surface of the intermediate core layer 1 contains copper in an amount of 5% to 20% higher than the first surface of the intermediate core layer 1, and more preferably the predetermined value is about 10%. Since copper has a relatively large coefficient of thermal expansion, it deforms largely at high temperatures. The side with high copper content (i.e. the side below the middle core layer 1 in fig. 2) deforms more than the side with low copper content (i.e. the side above the middle core layer 1 in fig. 2), and the difference between the former and the latter is larger than zero, so that the substrate generates corresponding smile-shaped warpage. If necessary, if the difference between the former and the latter is less than zero, the substrate may warp like a crying face.
Therefore, when the substrate 100 with low warpage stress provided by the embodiment of the present invention is used in the FC process, the substrate and the mounted chip need to be processed at high temperature during the reflow process. During this process, the deformation caused by the copper content of the second surface of the intermediate core layer of the substrate is higher than the deformation caused by the copper content of the first surface of the intermediate core layer of the substrate; and the thermal expansion coefficient of the dielectric layer (second dielectric layer 22) material of the second surface of the middle core layer is higher than that of the dielectric layer (first dielectric layer 21) material of the first surface of the middle core layer 1, so that the whole substrate forms smiling face-shaped warping, and the smiling face-shaped warping keeps the same deformation matching trend with the smiling face-shaped warping of the attached chip. Therefore, the substrate with low warpage stress provided by the embodiment of the invention greatly reduces the risk of forming the cold joint between the chip bumps and the substrate, and improves the yield of products.
< second embodiment >
The second embodiment of the present invention also provides a substrate 100 with low warpage stress. The substrate 100 includes a six-layer metal structure (fig. 3), or any 2N metal layers (N is a positive integer). Specifically, there is a first dielectric layer 21 on a first surface of the intermediate core layer 1 and a second dielectric layer 22 on a second surface. On the first surface there is a first metal layer 211, a third metal layer 212 and a fifth metal layer 213. Similarly, on the second surface there is a third metal layer 221, a fourth metal layer 222 and a sixth metal layer 223.
As with the substrate in the first embodiment, the dielectric layers of materials having different thermal expansion coefficients are used for the first surface and the second surface of the intermediate core layer 1, so that the thermal expansion coefficient of the dielectric layer material of the second surface of the intermediate core layer 1 is higher than that of the dielectric layer of the first surface. More preferably, the amount of copper on the second surface of the intermediate core layer 1 is higher than the amount of copper on the first surface of the intermediate core layer 1. By controlling the difference between the thermal expansion coefficient of the first dielectric layer on the first surface and the thermal expansion coefficient of the second dielectric layer on the second surface, and the difference between the copper content on the first surface and the copper content on the second surface, the substrate can be subjected to expected warping when being heated in the chip welding process.
< third embodiment >
Alternatively, a low warpage stress substrate according to a third embodiment of the present invention is provided in which, unlike the first embodiment, the materials of the solder resist layers of the first and second surfaces of the substrate are different, so that the thermal expansion coefficient of the solder resist layer material of the first surface is different from the thermal expansion coefficient of the solder resist layer material of the second surface. Therefore, the difference between the thermal expansion coefficients of the dielectric layer and the solder mask layer material on the first surface and the thermal expansion coefficients of the dielectric layer and the solder mask layer material on the second surface can be comprehensively adjusted, so that the thermal expansion coefficient control with higher flexibility is realized, and the warping degree of the substrate is further controlled.
< fourth embodiment >
The fourth embodiment of the present invention further provides a method for manufacturing a substrate with low warpage stress, as shown in fig. 4 to 6, including the following steps.
S1: a first metal layer is formed on the first surface 1A of the intermediate core layer 1, a third metal layer is formed on the second surface 1B, and a conductive via hole penetrating the first surface 1A and the second surface 1B is formed.
As shown in fig. 4, in the intermediate Core layer (CCL or BT Core) 1, conductive through holes 11 are formed to penetrate the intermediate Core layer 1 in an up-down symmetrical manner by a process such as laser via-hole drilling or mechanical drilling. Then, the first metal layer 211 is formed on the first surface 1A of the intermediate core layer 1 by plating, sputtering, or the like, and the third metal layer 221 is formed on the second surface 1B of the intermediate base layer.
S2: and forming a first dielectric layer covering the second metal layer and a second dielectric layer covering the third metal layer by using a laminating process, wherein the material of the first dielectric layer and the material of the second dielectric layer have different thermal expansion coefficients.
As shown in fig. 5, different layers of dielectric material (having different coefficients of thermal expansion) may be pressed onto the first and second surfaces of the intermediate core layer 1 by a lamination process to form a first dielectric layer 21 at the first surface 1A and a second dielectric layer 21 at the second surface 1B.
S3: and finishing the processing of other substrate layers and subsequent processing processes.
As shown in fig. 6, a second metal layer 212 is formed on the first dielectric layer 21, and a fourth metal layer 222 is formed on the second dielectric layer. And finishing subsequent substrate processing processes such as surface treatment of the second metal layer 212 and the fourth metal layer 222 exposed on the surface layer, for example, exposure, development, electroplating and the like, forming a solder mask, finishing subsequent substrate requirements such as surface treatment of the metal layer exposed on the surface layer and the like, so as to finish final substrate processing, and obtaining the substrate 100 with low warpage stress provided by the embodiment of the invention.
When the substrate with low warpage stress provided by the fourth embodiment of the present invention is used in the FC process, the substrate and the mounted chip need to be subjected to high temperature treatment during the reflow process, and in this process, the levels of the thermal expansion coefficients of the upper and lower dielectric layers of the substrate are different, and the copper contents of the upper and lower portions of the middle core layer are also different, so that the upper and lower deformations of the substrate are different (in this embodiment, the deformation of the lower half portion of the substrate is higher than the deformation of the upper half portion of the substrate). Therefore, the deformation matching trend of the substrate and the deformation of the attached chip is kept the same or different, the risk of forming insufficient solder joint between the chip salient point (Bump) and the substrate is greatly reduced, and the yield of products is greatly improved.
< fifth embodiment >
The fifth embodiment of the present invention further provides a package structure. The packaging structure comprises the substrate 100 with low warping stress and the chip 200 provided by the embodiment of the invention.
As shown in fig. 7, the substrate 100 with low warpage stress is electrically connected to the chip 200 through the second metal layer 212. Specifically, the chip includes a metal bump 201, and is soldered to the second metal layer 212 by using an interconnect structure 202 (e.g., a solder ball 202) through an SMT process, so as to achieve electrical connection between the chip 200 and the substrate 100 with low warpage stress. The interconnect structure 202 may be a ball bump (solder bump), a Copper pillar bump (Copper pillar bump), or a Flip chip Copper pillar bump.
< sixth embodiment >
The sixth embodiment of the invention also provides a packaging method, which is suitable for various FCCSP and FCBGA products. The packaging method comprises the following steps: the chip 200 is soldered to the aforementioned substrate with low warpage stress using an SMT process, resulting in a package structure including the substrate.
< seventh embodiment >
The seventh embodiment of the invention also provides an electronic product comprising the substrate with low warping stress. The electronic product may be a wireless communication terminal device, a wearable electronic device, or the like.
In summary, in the substrate with low warpage stress provided by the embodiments of the present invention, the dielectric layer materials with different thermal expansion coefficients are adopted on the two sides of the substrate, and the materials with different copper contents are adopted on the two sides of the substrate, or the solder resist materials with different thermal expansion coefficients are adopted, so that the substrate is easy to present smiling face-shaped warpage during the high temperature reflow soldering process, and thus the substrate is matched with the smiling face-shaped warpage of the bare chip, and the problem of insufficient soldering caused by mismatching of warpage is avoided. Those skilled in the art will understand that, according to actual needs, the substrate may be caused to have crying face-like warpage matching with the bare chip by using the present invention. Compared with the prior art, the substrate with low warpage stress provided by the embodiment of the invention can avoid the problem of insufficient solder joint caused by warpage matching, and the yield is improved.
The term "formation" as used herein means that the material can be obtained by one of various processes, and is not limited to the processes described in examples.
It is to be understood that the terms "thickness," "depth," "upper," "lower," "horizontal," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The substrate with low warpage stress, the manufacturing method, the package structure and the electronic product provided by the invention are described in detail above. It will be apparent to those skilled in the art that any obvious modifications thereof can be made without departing from the spirit of the invention, which infringes the patent right of the invention and bears the corresponding legal responsibility.
Claims (14)
1. A substrate with low warpage stress comprises a middle core layer, a conductive via, a first surface dielectric layer, a second surface dielectric layer and 2N metal layers, wherein N is a positive integer,
the first surface dielectric layer is on a first surface of the intermediate core layer, the second surface dielectric layer is on a second surface of the intermediate core layer,
the first surface is used for connecting a chip,
the second surface is a surface of the intermediate core layer opposite to the first surface for connection to a substrate,
the second surface dielectric layer has a coefficient of thermal expansion different from a coefficient of thermal expansion of the first surface dielectric layer.
2. The low warp stress substrate of claim 1 wherein:
the thermal expansion coefficient of the second surface dielectric layer is larger than that of the first surface dielectric layer.
3. The low warp stress substrate of claim 2 wherein:
the first surface dielectric layer comprises at least a first dielectric layer,
the second surface dielectric layer comprises at least a second dielectric layer,
the second dielectric layer and the first dielectric layer have different coefficients of thermal expansion.
4. The low warp stress substrate of claim 3 wherein:
the coefficient of thermal expansion of the second dielectric layer is greater than the coefficient of thermal expansion of the second dielectric layer.
5. The low warp stress substrate of claim 4 wherein:
the coefficient of thermal expansion of the second dielectric layer is more than 1.3 times of the coefficient of thermal expansion of the second dielectric layer.
6. The low warp stress substrate of claim 4 wherein:
the thickness of the second surface dielectric layer is larger than that of the first surface dielectric layer.
7. The low warp stress substrate of claim 6 wherein:
the thickness of the second surface dielectric layer is increased by 5-25 um compared with the thickness of the first surface dielectric layer.
8. The low warp stress substrate of claim 1 wherein:
the 2N metal layers comprise a first metal layer and a third metal layer,
the first metal layer is formed on the first surface, the third metal layer is formed on the second surface, and the first metal layer and the third metal layer are connected through the conductive through hole.
9. The low warp stress substrate of claim 8 wherein:
the copper content of the first metal layer is different from the copper content of the third metal layer.
10. The low warp stress substrate of claim 9 wherein:
the 2N metal layers further comprise a second metal layer and a fourth metal layer,
the second metal layer is positioned on the first surface; the fourth metal layer is located on the second surface,
and the sum of the copper contents of the first metal layer and the second metal layer is less than the sum of the copper contents of the third metal layer and the fourth metal layer.
11. A package structure comprising the low warpage substrate of any of claims 1-10, and a chip attached to the substrate.
12. An electronic product comprising the substrate with low warpage stress according to any one of claims 1 to 10.
13. A preparation method of a substrate with low warping stress is characterized by comprising the following steps:
s1: forming a first metal layer on a first surface of an intermediate core layer, a third metal layer on a second surface of the intermediate core layer, and a conductive via penetrating the first surface and the second surface, the second surface being opposite to the first surface;
s2: forming a first dielectric layer covering the second metal layer and a second dielectric layer covering the third metal layer by using a laminating process, wherein the material of the first dielectric layer and the material of the second dielectric layer have different thermal expansion coefficients;
s3: and finishing the processing of other substrate layers and subsequent processing processes.
14. The method of claim 13, wherein:
the first metal layer and the third metal layer have different copper contents.
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| CN202211610234.9A CN115621242A (en) | 2022-12-15 | 2022-12-15 | Substrate with low warping stress, preparation method, packaging structure and electronic product |
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| CN202211610234.9A CN115621242A (en) | 2022-12-15 | 2022-12-15 | Substrate with low warping stress, preparation method, packaging structure and electronic product |
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| US20130240258A1 (en) * | 2012-03-19 | 2013-09-19 | Ibiden Co., Ltd. | Printed wiring board |
| US20130334711A1 (en) * | 2012-06-19 | 2013-12-19 | International Business Machines Corporation | Copper Feature Design for Warpage Control of Substrates |
| CN104582252A (en) * | 2013-10-25 | 2015-04-29 | 三星电机株式会社 | Printed curcuit board and manufacturing method of the same |
| JP2016048768A (en) * | 2014-08-28 | 2016-04-07 | 日立化成株式会社 | Wiring board and manufacturing method of semiconductor device |
| CN106158816A (en) * | 2015-04-07 | 2016-11-23 | 矽品精密工业股份有限公司 | Package substrate |
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| US20040065473A1 (en) * | 2002-10-08 | 2004-04-08 | Siliconware Precision Industries, Ltd., Taiwan | Warpage preventing substrate |
| TW200929452A (en) * | 2007-12-26 | 2009-07-01 | Powertech Technology Inc | Laminate substrate and chip package utilizing the substrate |
| CN101562169A (en) * | 2008-04-16 | 2009-10-21 | 力成科技股份有限公司 | Lamination type base plate and chip packaging structure using same |
| US20130221518A1 (en) * | 2012-02-28 | 2013-08-29 | Ibiden Co., Ltd. | Printed wiring board |
| US20130240258A1 (en) * | 2012-03-19 | 2013-09-19 | Ibiden Co., Ltd. | Printed wiring board |
| US20130334711A1 (en) * | 2012-06-19 | 2013-12-19 | International Business Machines Corporation | Copper Feature Design for Warpage Control of Substrates |
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Application publication date: 20230117 |