CN115604176A - 利用多级信号传输的通信信道 - Google Patents

利用多级信号传输的通信信道 Download PDF

Info

Publication number
CN115604176A
CN115604176A CN202210083200.2A CN202210083200A CN115604176A CN 115604176 A CN115604176 A CN 115604176A CN 202210083200 A CN202210083200 A CN 202210083200A CN 115604176 A CN115604176 A CN 115604176A
Authority
CN
China
Prior art keywords
circuit
serializer
driver
transmitter
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210083200.2A
Other languages
English (en)
Chinese (zh)
Inventor
A·瑞查都瑞
J·马拉卡
S·麦提
S·N·萨姆巴图尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/455,306 external-priority patent/US20230011466A1/en
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN115604176A publication Critical patent/CN115604176A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/24—Multipath
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Dc Digital Transmission (AREA)
CN202210083200.2A 2021-07-09 2022-01-25 利用多级信号传输的通信信道 Pending CN115604176A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IN202111030830 2021-07-09
IN202111030830 2021-07-09
US17/455,306 US20230011466A1 (en) 2021-07-09 2021-11-17 Communications channel with multi-level signal transmission
US17/455,306 2021-11-17

Publications (1)

Publication Number Publication Date
CN115604176A true CN115604176A (zh) 2023-01-13

Family

ID=84534089

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210083200.2A Pending CN115604176A (zh) 2021-07-09 2022-01-25 利用多级信号传输的通信信道

Country Status (2)

Country Link
CN (1) CN115604176A (de)
DE (1) DE102022112544A1 (de)

Also Published As

Publication number Publication date
DE102022112544A1 (de) 2023-01-12

Similar Documents

Publication Publication Date Title
US7269212B1 (en) Low-latency equalization in multi-level, multi-line communication systems
US7072415B2 (en) Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation
US7456778B2 (en) Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
US6898724B2 (en) System for latching an output signal generated by comparing complimentary strobe signals and a data signal in response to a comparison of the complimentary strobe signals
US8436653B2 (en) Low power multi-level signaling
US7528635B2 (en) Multitap fractional baud period pre-emphasis for data transmission
US10200025B2 (en) Pulse-amplitude modulated hybrid comparator circuit
US20070164883A1 (en) Method and device for transmitting data over a plurality of transmission lines
JP2007505575A (ja) 選択可能なプリエンファシス信号レベルを有する、ｄａｃに基づくラインドライバ
US7768306B2 (en) Low to high voltage conversion output driver
US9813188B2 (en) Transmitting circuit, communication system, and communication method
KR20200022051A (ko) 데이터를 나타내는 다중 레벨 신호에 추가 구동을 제공하기 위한 장치 및 방법
JP3696812B2 (ja) 入出力インタフェースおよび半導体集積回路
US6552582B1 (en) Source follower for low voltage differential signaling
JP4439124B2 (ja) データ依存駆動強度制御ロジックを備えたバス・ドライバ
CN115604176A (zh) 利用多级信号传输的通信信道
US20230011466A1 (en) Communications channel with multi-level signal transmission
Lee et al. 12-Gb/s over four balanced lines utilizing NRZ braid clock signaling with no data overhead and spread transition scheme for 8K UHD intra-panel interfaces
WO2002021782A9 (en) Calibration of a multi-level current mode driver
KR20200003522A (ko) 저전력 유선 채널 송신기 및 이를 포함하는 송수신기
Rashdan Dual-time resolution time-based transceiver for low-power serial interfaces
KR101995027B1 (ko) 정전류 소모가 없는 저전력 송신기
US11874788B1 (en) Transmitter architecture for high speed memory interfaces
JP2016219988A (ja) 差動伝送回路、撮像装置、画像読取装置及び画像形成装置
US11663157B1 (en) Joint electron devices engineering council (JESD)204-to-peripheral component interconnect express (PCIe) interface

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination