CN115579428A - LED chip bonding method and LED chip - Google Patents

LED chip bonding method and LED chip Download PDF

Info

Publication number
CN115579428A
CN115579428A CN202211150711.8A CN202211150711A CN115579428A CN 115579428 A CN115579428 A CN 115579428A CN 202211150711 A CN202211150711 A CN 202211150711A CN 115579428 A CN115579428 A CN 115579428A
Authority
CN
China
Prior art keywords
layer
led chip
substrate
bonding
epitaxial wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211150711.8A
Other languages
Chinese (zh)
Inventor
杨天鹏
杨建国
卜浩礼
康建
邹浩洪
周荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Epitop Optoelectronic Co ltd
Original Assignee
Jiangxi Epitop Optoelectronic Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Epitop Optoelectronic Co ltd filed Critical Jiangxi Epitop Optoelectronic Co ltd
Priority to CN202211150711.8A priority Critical patent/CN115579428A/en
Publication of CN115579428A publication Critical patent/CN115579428A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B08B3/10—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration
    • B08B3/12—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
    • B08B3/123—Cleaning travelling work, e.g. webs, articles on a conveyor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses an LED chip bonding method and an LED chip, and relates to the technical field of LED chips. The LED chip bonding method comprises the following steps: s1, providing an epitaxial wafer and a substrate; s2, evaporating and plating a first ITO layer, a first bonding layer and a first bonding layer on the substrate; s3, evaporating and plating a second ITO layer on the epitaxial wafer; s4, providing a substrate, S5, forming a solder layer on the surface of the first bonding layer and the surface of the second bonding layer, and S6, and attaching the epitaxial wafer to the substrate. According to the LED chip bonding method and the LED chip, the bonding effect of the produced LED chip is better through the water bath cooling and ultrasonic cleaning modes, the phenomenon that the light transmittance of the LED chip is poor due to impurities cannot occur, the quality of the LED chip is improved to a great extent, the phenomenon that the light transmittance of the LED chip is poor frequently occurs is solved, and the problem that the light transmittance of the LED chip is poor due to certain impurities which are always remained on the surface of the LED chip is solved.

Description

LED chip bonding method and LED chip
Technical Field
The invention relates to the technical field of LED chips, in particular to an LED chip bonding method and an LED chip.
Background
The LED chip is a solid semiconductor device, the heart of the LED is a semiconductor wafer, one end of the wafer is attached to a support, the other end of the wafer is a cathode, the other end of the wafer is connected with the anode of a power supply, and the whole wafer is packaged by epoxy resin. Also called LED light-emitting chip, is the core component of the LED lamp, namely the P-N junction. The main functions are as follows: the electric energy is converted into light energy, and the main material of the chip is monocrystalline silicon.
At the manufacturing end of the LED chip, substrate replacement is an important process, and the process can enable the chip to achieve the purpose of increasing heat dissipation and improving light transmission or back light emission by changing different substrates. At present, the main substrate replacement methods are mainly divided into two types, one is to replace the substrate with Si or other non-transparent substrate through metal bonding, and the other is surface activation bonding, and the method is mainly used in the back light chip process.
In the prior art, the chip manufacturing process needs to rely on different bonding modes as main production steps for replacing the substrate, the bonding mode in the prior art has certain defects, and if the surface activation bonding mode is adopted, although the light transmittance is high, the activated surface basically adopts SiO 2 The current expansion of the materials is relatively weak, if other metals such as copper and silver are adopted for surface activation, the preparation cost is greatly increased, the processed LED chip has poor light transmittance, and certain impurities remain on the surface of the processed LED chip, so that the light transmittance of the LED chip is poor; in view of this, we propose an LED chip bonding method and an LED chip.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides an LED chip bonding method and an LED chip, and solves the problems mentioned in the background technology.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: an LED chip bonding method, comprising the steps of:
s1, providing an epitaxial wafer and a substrate;
s2, evaporating and plating a first ITO layer, a first bonding layer and a first bonding layer on the substrate;
s3, a second ITO layer is deposited on the epitaxial wafer in a vapor deposition mode, and a Cr layer is deposited on the second ITO layer in a vapor deposition mode;
s4, providing a substrate, and sequentially evaporating a second bonding layer, a brazing filler metal barrier layer and a second bonding layer on the substrate;
s5, forming a brazing filler metal layer on the surfaces of the first bonding layer and the second bonding layer, and attaching the substrate and the base plate, wherein the surface of the brazing filler metal layer is an attaching surface, and the brazing filler metal layer is completely diffused to the first bonding layer and the second bonding layer to realize bonding;
and S6, attaching the epitaxial wafer to the substrate, attaching the first ITO layer on the substrate to one side of the epitaxial wafer, on which the Cr layer is evaporated, and cooling and cleaning the attached epitaxial wafer and the substrate.
Optionally, the solder layer is made of metal with a melting point of 380 ℃ or less or an alloy containing metal with a melting point of 380 ℃ or less.
Optionally, the first ITO layer on the substrate and the side of the epitaxial wafer on which the Cr layer is evaporated are attached to each other, and the first ITO layer and the side of the epitaxial wafer are subjected to annealing treatment in an annealing device, and the substrate and the epitaxial wafer are subjected to pressure treatment after the annealing treatment, wherein the ambient temperature of the annealing treatment is greater than 360 ℃.
Optionally, the environment of the pressure treatment is 1.2MPa.
Optionally, the cooling temperature in the cooling and cleaning treatment is 0-1 ℃, and the cooling mode is water bath cooling.
Optionally, ultrasonic cleaning is adopted in the cooling and cleaning treatment, and the substrate and the epitaxial wafer are placed in an ultrasonic cleaning machine for cleaning.
Optionally, in the process of evaporating the Cr layer on the second ITO layer, the ambient vacuum condition is greater than 6E-6Torr, the ambient temperature condition is 180-220 degrees celsius, and the evaporation rate is
Figure BDA0003857021250000031
Optionally, the bonding time is 75min-120min.
Optionally, the thicknesses of the first ITO layer and the second ITO layer are both
Figure BDA0003857021250000032
An LED chip is prepared by the LED chip bonding method.
(III) advantageous effects
The invention provides an LED chip bonding method and an LED chip. The method has the following beneficial effects:
(1) According to the LED chip bonding method and the LED chip, the bonding effect of the produced LED chip is better through the water bath cooling and ultrasonic cleaning modes, the phenomenon that the light transmittance of the LED chip is poor due to impurities cannot occur, the quality of the LED chip is improved to a great extent, the problem that the light transmittance of the LED chip is poor due to the fact that the LED chip always has certain impurities on the surface of the LED chip is solved.
(2) The LED chip bonding method and the LED chip avoid using expensive metal to carry out surface activation, completely melt the brazing filler metal layer, diffuse the brazing filler metal layer to the first bonding layer and the second bonding layer to carry out bonding, namely, utilize liquid phase diffusion welding, so that the brazing filler metal layer can be melted and diffused at a lower temperature to form a stable mixed layer with the first bonding layer and the second bonding layer, obtain a better bond and an interface, can process to obtain a cost with better quality through lower cost, and are suitable for processing and production in factories.
(3) According to the LED chip bonding method and the LED chip, the first ITO layer, the second ITO layer and the Cr layer which are evaporated are diffused to the first ITO layer and the second ITO layer in a high-temperature mode, and the second ITO layer is bonded with the second ITO layer. The current expansion effect is good, the ITO light transmittance is extremely high, the current expansion effect can be achieved, the penetration of light is not influenced by the thickness of the Cr layer, and good current expansion and light transmittance are guaranteed at the joint of the epitaxial wafer and the substrate.
Drawings
FIG. 1 is a schematic view of an LED chip according to the present invention;
FIG. 2 is a schematic view of the overall flow structure of the present invention.
In the figure: 1. a substrate; 2. a first ITO layer; 3. a Cr layer; 4. a second ITO layer; 5. and (7) an epitaxial wafer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It should be noted that all directional indicators (such as up, down, left, right, front, back \8230;) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
Example 1:
referring to fig. 1-2, the present invention provides a technical solution: an LED chip bonding method, comprising the steps of:
s1, providing an epitaxial wafer 5 and a substrate 1, wherein the substrate 1 is made of one of silicon, silicon carbide, gaAs and AlN;
s2, evaporating a first ITO layer 2, a first bonding layer and a first bonding layer on the substrate 1, wherein the first bonding layer is made of Ti and 25-40nm in thickness, the first bonding layer is made of Ni and 1.2-1.6 microns in thickness;
s3, a second ITO layer 4 is deposited on the epitaxial wafer 5 in a vapor deposition mode, and a Cr layer 3 is deposited on the second ITO layer 4 in a vapor deposition mode;
s4, providing a substrate, and sequentially evaporating a second bonding layer on the substrate, wherein the material of the second bonding layer is Ti, the thickness of the second bonding layer is 25-40nm, the material of the brazing filler metal barrier layer is Ni, and the thickness of the second bonding layer is 1.2-1.6 microns;
s5, forming a brazing filler metal layer on the surfaces of the first bonding layer and the second bonding layer, wherein the rear pair of the brazing filler metal layer is 500nm, the brazing filler metal layer can be formed in a thermal evaporation mode, an electron beam evaporation mode, a sputtering and electroplating mode, the substrate 1 is attached to the base plate, the surface of the brazing filler metal layer is an attaching surface, and the brazing filler metal layer is completely diffused to the first bonding layer and the second bonding layer to realize bonding;
s6, attaching the epitaxial wafer 5 to the substrate 1, attaching the first ITO layer 2 on the substrate 1 to one side of the epitaxial wafer 5 with the Cr layer 3 deposited, and cooling and cleaning the attached epitaxial wafer 5 and the substrate 1.
The brazing filler metal layer is made of metal with a melting point of 380 ℃ or less or alloy containing metal with a melting point of 380 ℃ or less. The first ITO layer 2 on the substrate 1 and one side of the epitaxial wafer 5 with the Cr layer 3 evaporated are attached to each other, annealing treatment needs to be carried out in annealing equipment, the environment temperature of the annealing treatment is higher than 360 ℃, and the substrate 1 and the epitaxial wafer 5 are subjected to pressurization treatment after the annealing treatment. The pressure treatment atmosphere was 1.2MPa. The method avoids using expensive metal for surface activation, and the brazing filler metal is completely melted and diffused to the first bonding layer and the second bonding layer for bonding, namely liquid phase diffusion welding is utilized, so that the brazing filler metal can be melted and diffused at a lower temperature to form a stable mixed layer with the first bonding layer and the second bonding layer, a better bond and an interface are obtained, the cost with better quality can be obtained through lower cost, and the method is suitable for processing and producing in factories
The cooling temperature in the cooling and cleaning treatment is 0-1 ℃, the cooling mode is water bath cooling, and the cooling water is an ice-water mixture. Adopt ultrasonic cleaning in the cooling cleaning process, put substrate 1 and epitaxial wafer 5 and clear up in the ultrasonic cleaner, through water bath cooling and ultrasonic cleaning's mode, make the LED chip bonding effect of producing better, and can not appear leading to the relatively poor phenomenon of LED chip luminousness because of impurity, promote the quality of LED chip in very big degree, the relatively poor phenomenon of luminousness often appears in the LED chip has been solved, always certain impurity on its surface, the problem that the luminousness rate is poor that leads to the LED chip.
In the process of evaporating the Cr layer 3 on the second ITO layer 4, the environmental vacuum condition is more than 6E-6Torr, the environmental temperature condition is 180-220 ℃, and the evaporation transition rate is
Figure BDA0003857021250000051
The bonding time is 75-120 min. The thickness of the first ITO layer 2 and the second ITO layer 4 are both
Figure BDA0003857021250000052
The first ITO layer, the second ITO layer and the Cr layer of coating by vaporization make the Cr layer diffuse to first ITO layer and second ITO layer through the mode of high temperature, bind second ITO layer and second ITO layer. The current spreading effect is good, the ITO light transmittance is extremely high, the current spreading effect can be achieved, the thickness of the Cr layer does not influence the penetration of light, and good current spreading and light transmittance are guaranteed at the joint of the epitaxial wafer 5 and the substrate.
The invention also provides an LED chip, which is prepared by adopting the LED chip bonding method.
Example 2:
referring to fig. 1-2, the present invention provides a technical solution: an LED chip bonding method, comprising the steps of:
s1, providing an epitaxial wafer 5 and a substrate 1, wherein the substrate 1 is made of one of silicon, silicon carbide, gaAs and AlN;
s2, evaporating a first ITO layer 2, a first bonding layer and a first bonding layer on the substrate 1, wherein the first bonding layer is made of Ti and 40-45nm in thickness, the first bonding layer is made of Ni and 1.2-1.6 microns in thickness;
s3, evaporating a second ITO layer 4 on the epitaxial wafer, and evaporating a Cr layer 3 on the second ITO layer 4;
s4, providing a substrate, and sequentially evaporating and plating a second bonding layer on the substrate, wherein the material of the second bonding layer is Ti, the thickness of the second bonding layer is 40-45nm, the material of the brazing filler metal barrier layer is Ni, and the thickness of the second bonding layer is 1.2-1.6 microns;
s5, forming a brazing filler metal layer on the surfaces of the first bonding layer and the second bonding layer, wherein the rear pair of the brazing filler metal layer is 500nm, the brazing filler metal layer can be formed in a thermal evaporation mode, an electron beam evaporation mode and a sputtering and electroplating mode, the substrate 1 is attached to the base plate, the surface of the brazing filler metal layer is an attachment surface, and the brazing filler metal layer is completely diffused to the first bonding layer and the second bonding layer to realize bonding;
and S6, attaching the epitaxial wafer 5 to the substrate 1, attaching the first ITO layer 2 on the substrate 1 to one side of the epitaxial wafer 5 with the Cr layer 3, and cooling and cleaning the attached epitaxial wafer 5 and the substrate 1.
The brazing filler metal layer is made of metal with a melting point of 380 ℃ or less or alloy containing metal with a melting point of 380 ℃ or less. The first ITO layer 2 on the substrate 1 and one side of the epitaxial wafer 5, which is evaporated with the Cr layer 3, are attached to each other, annealing treatment needs to be carried out in annealing equipment, the ambient temperature of the annealing treatment is higher than 360 ℃, and the substrate 1 and the epitaxial wafer 5 are subjected to pressurization treatment after the annealing treatment. The pressure treatment atmosphere was 1.2MPa.
The cooling temperature in the cooling and cleaning treatment is 0-1 ℃, the cooling mode is water bath cooling, and the cooling water is an ice-water mixture. Ultrasonic cleaning is adopted in the cooling and cleaning treatment, and the substrate 1 and the epitaxial wafer 5 are placed in an ultrasonic cleaning machine for cleaning.
In the process of evaporating and plating the Cr layer 3 on the second ITO layer 4, the environmental vacuum condition is more than 6E-6Torr, the environmental temperature condition is 180-220 ℃, and the evaporation plating rate is
Figure BDA0003857021250000071
The bonding time is 75min-120min. The thickness of the first ITO layer 2 and the second ITO layer 4 are both
Figure BDA0003857021250000072
The invention also provides an LED chip, which is prepared by adopting the LED chip bonding method.
Example 3:
referring to fig. 1-2, the present invention provides a technical solution: an LED chip bonding method, comprising the steps of:
s1, providing an epitaxial wafer 5 and a substrate 1, wherein the substrate 1 is made of one of silicon, silicon carbide, gaAs and AlN;
s2, evaporating a first ITO layer 2, a first bonding layer and a first bonding layer on the substrate 1, wherein the first bonding layer is made of Ti and 45-60nm thick, the first bonding layer is made of Ni and 1.2-1.6 microns thick;
s3, evaporating a second ITO layer 4 on the epitaxial wafer, and evaporating a Cr layer 3 on the second ITO layer 4;
s4, providing a substrate, and sequentially evaporating a second bonding layer on the substrate, wherein the material of the second bonding layer is Ti, the thickness of the second bonding layer is 45-60nm, the material of the brazing filler metal barrier layer is Ni, and the thickness of the second bonding layer is 1.2-1.6 microns;
s5, forming a brazing filler metal layer on the surfaces of the first bonding layer and the second bonding layer, wherein the rear pair of the brazing filler metal layer is 500nm, the brazing filler metal layer can be formed in a thermal evaporation mode, an electron beam evaporation mode, a sputtering and electroplating mode, the substrate 1 is attached to the base plate, the surface of the brazing filler metal layer is an attaching surface, and the brazing filler metal layer is completely diffused to the first bonding layer and the second bonding layer to realize bonding;
s6, attaching the epitaxial wafer 5 to the substrate 1, attaching the first ITO layer 2 on the substrate 1 to one side of the epitaxial wafer 5 with the Cr layer 3 deposited, and cooling and cleaning the attached epitaxial wafer 5 and the substrate 1.
The brazing filler metal layer is made of metal with a melting point of 380 ℃ or less or alloy containing metal with a melting point of 380 ℃ or less. The first ITO layer 2 on the substrate 1 and one side of the epitaxial wafer 5, which is evaporated with the Cr layer 3, are attached to each other, annealing treatment needs to be carried out in annealing equipment, the ambient temperature of the annealing treatment is higher than 360 ℃, and the substrate 1 and the epitaxial wafer 5 are subjected to pressurization treatment after the annealing treatment. The pressure treatment atmosphere was 1.2MPa.
The cooling temperature in the cooling and cleaning treatment is 0-1 ℃, the cooling mode is water bath cooling, and the cooling water is an ice-water mixture. Ultrasonic cleaning is adopted in the cooling and cleaning treatment, and the substrate 1 and the epitaxial wafer 5 are placed in an ultrasonic cleaning machine for cleaning.
In the process of evaporating and plating the Cr layer 3 on the second ITO layer 4, the environmental vacuum condition is more than 6E-6Torr, the environmental temperature condition is 180-220 ℃, and the evaporation plating rate is
Figure BDA0003857021250000081
The bonding time is 75min-120min. The thickness of the first ITO layer 2 and the second ITO layer 4 are both
Figure BDA0003857021250000082
The invention also provides an LED chip, which is prepared by adopting the LED chip bonding method.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. An LED chip bonding method is characterized in that: the bonding method comprises the following steps:
s1, providing an epitaxial wafer and a substrate;
s2, evaporating and plating a first ITO layer, a first bonding layer and a first bonding layer on the substrate;
s3, a second ITO layer is deposited on the epitaxial wafer in a vapor deposition mode, and a Cr layer is deposited on the second ITO layer in a vapor deposition mode;
s4, providing a substrate, and sequentially evaporating a second bonding layer, a brazing filler metal barrier layer and a second bonding layer on the substrate;
s5, forming a brazing filler metal layer on the surfaces of the first bonding layer and the second bonding layer, and attaching the substrate and the base plate, wherein the surface of the brazing filler metal layer is an attaching surface, and the brazing filler metal layer is completely diffused to the first bonding layer and the second bonding layer to realize bonding;
and S6, attaching the epitaxial wafer to the substrate, attaching the first ITO layer on the substrate to one side of the epitaxial wafer, on which the Cr layer is evaporated, and cooling and cleaning the attached epitaxial wafer and the substrate.
2. The LED chip bonding method according to claim 1, wherein: the brazing filler metal layer is made of metal with a melting point of 380 ℃ or less or alloy containing metal with a melting point of 380 ℃ or less.
3. The LED chip bonding method according to claim 1, wherein: the method is characterized in that the first ITO layer on the substrate and one side of the epitaxial wafer, which is coated with the Cr layer in an evaporation mode, are attached to each other, annealing treatment needs to be carried out in annealing equipment, the environment temperature of the annealing treatment is higher than 360 ℃, and the substrate and the epitaxial wafer are subjected to pressurization treatment after the annealing treatment.
4. The LED chip bonding method according to claim 3, wherein: the pressure treatment environment was 1.2MPa.
5. The LED chip bonding method according to claim 1, wherein: the cooling temperature in the cooling and cleaning treatment is 0-1 ℃, and the cooling mode is water bath cooling.
6. The LED chip bonding method according to claim 5, wherein: and ultrasonic cleaning is adopted in the cooling and cleaning treatment, and the substrate and the epitaxial wafer are placed in an ultrasonic cleaning machine for cleaning.
7. The LED chip bonding method according to claim 1, wherein: in the process of evaporating the Cr layer on the second ITO layer, the environmental vacuum condition is more than 6E-6Torr, and the environmental temperatureThe condition is 180-220 ℃, and the transition rate of the evaporation is
Figure FDA0003857021240000021
8. The LED chip bonding method according to claim 1, wherein: the bonding time is 75min-120min.
9. The LED chip bonding method according to claim 1, wherein: the thickness of the first ITO layer and the second ITO layer are both
Figure FDA0003857021240000022
10. An LED chip, characterized in that: the LED chip comprises an LED chip, and the LED chip is prepared by the LED chip bonding method of claims 1-9.
CN202211150711.8A 2022-09-21 2022-09-21 LED chip bonding method and LED chip Pending CN115579428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211150711.8A CN115579428A (en) 2022-09-21 2022-09-21 LED chip bonding method and LED chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211150711.8A CN115579428A (en) 2022-09-21 2022-09-21 LED chip bonding method and LED chip

Publications (1)

Publication Number Publication Date
CN115579428A true CN115579428A (en) 2023-01-06

Family

ID=84581864

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211150711.8A Pending CN115579428A (en) 2022-09-21 2022-09-21 LED chip bonding method and LED chip

Country Status (1)

Country Link
CN (1) CN115579428A (en)

Similar Documents

Publication Publication Date Title
US8471386B2 (en) Junction body, semiconductor module, and manufacturing method for junction body
CN101293294B (en) Sealing-in method for packaging outer shell with aluminum silicon carbide
CN101764121B (en) Interlayer insulated stacked composite material and preparation method thereof
CN103170765B (en) Preparation method for gold-tin eutectic solder
CN104690383B (en) Between a kind of all-metal, compound interconnects preparation method and the structure of solder joint
CN101182642A (en) Method of electroplating combined vacuum coating preparing Au-Sn alloy solder
JPS60177635A (en) Manufacture of good heat conductive substrate
CN101502904A (en) Aluminum silicon carbide composite material for packaging microelectron and method for brazing kovar alloy
TWI496166B (en) Solar cell screen-printing composition, solar cell and method for manufacturing a metallization structure
CN102891240B (en) Light emitting diode (LED) with inverted structure and manufacturing method thereof
JP2011011366A (en) Method of manufacturing metal laminated structure
JP2007500450A (en) Composite materials and electrical circuits or modules
CN115411006A (en) Micro-welding point based on nanocrystalline copper matrix and preparation method thereof
US3522087A (en) Semiconductor device contact layers
CN113894460A (en) Self-propagating brazing film and preparation method thereof
CN115579428A (en) LED chip bonding method and LED chip
WO2023226457A1 (en) Display panel, and light-emitting element and back plate for use in display panel
JP5580772B2 (en) Manufacturing method of metal laminated structure
WO2023070551A1 (en) Light-emitting device, light-emitting module and manufacturing method therefor
Zhang et al. A Process Improvement in Silver-indium Transient Liquid Phase Bonding Method for the High-Power Electronics and Photonics Packaging
CN203300630U (en) Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process
CN214411241U (en) Flip LED chip with low voidage
CN100591181C (en) Method of manufacturing flip welding LED chip
CN104651898B (en) A kind of preparation method of intermetallic compound film
CN207199664U (en) High-power LED light source and LED light source module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination