CN203300630U - Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process - Google Patents
Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process Download PDFInfo
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- CN203300630U CN203300630U CN2013202726822U CN201320272682U CN203300630U CN 203300630 U CN203300630 U CN 203300630U CN 2013202726822 U CN2013202726822 U CN 2013202726822U CN 201320272682 U CN201320272682 U CN 201320272682U CN 203300630 U CN203300630 U CN 203300630U
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Abstract
The utility model provides a back-surface metallized structure for a P-type silicon chip device and applicable to the eutectic soldering process, which belongs to the technical field of semiconductor devices. The utility model is characterized in that the back surface of a P-type silicon semiconductor substrate is provided with a multi-element alloy layer composed of III-group element atoms, gold atoms and P-type silicon semiconductor materials. A gold metal layer is arranged on the multi-element alloy layer, or a SnCu/SnSb metal layer is arranged on the gold metal layer. The thickness of the multi-element alloy layer is 0.02-0.3 micrometers. The thickness of the gold metal layer is 1-2 micrometers. According to the technical scheme of the utility model, the structure is reasonable and the doped concentration on the back surface is improved. Therefore, the organic combination of the high density with the metallization is realized on the back surface. The pressure drop of the semiconductor chip is further lowered. In this way, the back-surface metallized structure for the P-type silicon semiconductor chip and applicable to the eutectic soldering process is realized. On one hand, the pressure drop of the semiconductor chip is lowered. On the other hand, the requirement of the eutectic soldering process for packaging the semiconductor chip is satisfied.
Description
Technical field
The utility model relates to a kind of P type silicon device chip back face metalization structure that can be used for the eutectic weldering, belongs to technical field of semiconductor device.
Background technology
Now, semiconductor device chip all wishes to use the eutectic solder technology with connecting of base material.The eutectic weldering claims again the low-melting alloy welding.Eutectic alloy is former is the concept of from a kind of phasor characteristic of bianry alloy, drawing, and its fundamental characteristics is: two kinds of different metals can form alloy in the constant weight ratio under the melting temperature far below separately.Be generalized to now multicomponent alloy.Eutectic weldering refers to the phenomenon of eutectic solder generation eutectic thing fusion at relatively low temperature, and eutectic alloy is directly from the solid-state liquid state that changes to, and without the plastic stage, thereby welding temperature is low, the quality of the mechanical performance of welding and electrical property is good.
The existing single layer of gold structure of silicon semiconductor chip that is fit at present the eutectic welding procedure has again multilayer gold structure.With respect to the silicon semiconductor chip of eutectic welding procedure, want to reduce the pressure drop of semiconductor chip, to improve on the one hand the doping content of semiconductor substrate; To reduce on the other hand the contact resistance of base material metal and base material in metallization process.Reduce this contact resistance, for the normal method of mending N-type foreign matter of phosphor or arsenic at the silicon semiconductor chip back side that adopts of N type semiconductor; For the normal method of mending P type element boron at chip back that adopts of P type Si semiconductor, to improve the doping content of semiconductor interface contact area.The P type Si semiconductor back side is mended boron and is usually adopted the method for diffusion or Implantation.In fact also can, by mend other III family element atoms at semiconductor back surface, reach the effect that improves back side doping content as the method by PVD technique and alloy for P type Si semiconductor.The utility model " can be used for eutectic weldering P type silicon device chip back face metalization structure ", realized meeting the requirement of eutectic technology welding and obtain good ohmic contact, mechanical strength pad preferably.
Summary of the invention
The purpose of this utility model is exactly the deficiency that exists for overcoming above-mentioned prior art, a kind of P type silicon device chip back face metalization structure for eutectic weldering is provided, meet the requirement of eutectic technology welding and obtain good ohmic contact, mechanical strength pad preferably.
The purpose of this utility model is to realize like this, the P type silicon device chip back face metalization structure that can be used for the eutectic weldering, it is characterized in that, the P type silicon semiconductor substrate back side is provided with the multicomponent alloy layer of III family element atom and gold and P type silicon semiconductor material, is provided with gold metal layer on the multicomponent alloy layer.Described multicomponent alloy layer thickness is the 0.02-0.3 micron.Gold metal layer thickness is the 1-2 micron.
Can also be provided with SnCu or SnSb metal level on described gold metal layer.
The utility model is rational in infrastructure, by mend the method for III family element atom at the P type silicon semiconductor material back side, multicomponent alloy layer and the gold metal layer of III family element atom and gold and P type silicon semiconductor material is set, and improves the doping content at the back side.The method that combines by PVD and alloy technique, having changed in the past single P type silicon semiconductor material is the multicomponent alloy layer of P type silicon semiconductor material and golden gallium alloy or golden aluminium alloy or golden indium alloy with the alloy-layer of gold, has realized back side high concentration and metallized combination.Further reduce the pressure drop of semiconductor chip, realized meeting the P type silicon semiconductor chip back face metalization structure of eutectic technology.Reduce on the one hand the pressure drop of P type silicon semiconductor chip, met on the other hand the requirement of semiconductor die package eutectic welding procedure.
Description of drawings
Fig. 1 is structural representation of the present utility model.
In figure: 1 .P type silicon semiconductor substrate, 2. multicomponent alloy layer, 3. additional SnCu or SnSb metal level on gold metal layer or gold metal layer.
Embodiment
The P type silicon device chip back face metalization structure that can be used for the eutectic weldering, by the method for at P type silicon semiconductor substrate 1 back side, mending III family element atom, multicomponent alloy layer 2 and the gold metal layer 3 of III family element atom and gold and P type silicon semiconductor material are set, multicomponent alloy layer 2 is arranged on P type silicon semiconductor substrate, on the multicomponent alloy layer, gold metal layer is set.Can also add SnCu or SnSb metal level on gold metal layer.Described multicomponent alloy layer thickness is the 0.02-0.3 micron.Gold metal layer thickness is the 1-2 micron.
The P type silicon device chip back face metalization structure that the utility model can be used for the eutectic weldering is to realize by the method that PVD and alloy technique combine, and its technical process can have two schemes, and is described as follows:
Scheme one:
Step 4. the semiconductor substrate of completing steps three is dried.
Step 5. to the chemical corrosion of the semiconductor substrate of completing steps four or burnishing surface evaporates successively or sputter gold gallium alloy or golden aluminium alloy or golden indium alloy, gold.
Step 6. the semiconductor substrate of completing steps five is carried out alloy under uniform temperature, atmosphere.Complete the back face metalization structure.
Scheme two:
Step 4. the semiconductor substrate of completing steps three is dried.
Step 5. adopt the method for evaporation or sputter to evaporate successively or sputter gold gallium alloy or golden aluminium alloy or golden indium alloy, gold to the chemical corrosion of the semiconductor substrate of completing steps four or burnishing surface.
Step 6. with the semiconductor substrate of completing steps five alloy under uniform temperature, atmosphere.
Step 7. to the evaporation of back metal face or sputter gun-metal or the tin pewter of the semiconductor substrate of completing steps six.Complete the back face metalization structure.
Claims (3)
1. the P type silicon device chip back face metalization structure that can be used for the eutectic weldering, it is characterized in that, the P type silicon semiconductor substrate back side is provided with the multicomponent alloy layer of III family element atom and gold and P type silicon semiconductor material, is provided with gold metal layer or is provided with SnCu or SnSb metal level again on the multicomponent alloy layer on gold metal layer.
2. according to claim 1, can be used for the P type silicon device chip back face metalization structure that eutectic welds, it is characterized in that, described multicomponent alloy layer thickness is the 0.02-0.3 micron.
3. according to claim 1, can be used for the P type silicon device chip back face metalization structure that eutectic welds, it is characterized in that, described gold metal layer thickness is the 1-2 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202726822U CN203300630U (en) | 2013-05-20 | 2013-05-20 | Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202726822U CN203300630U (en) | 2013-05-20 | 2013-05-20 | Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203300630U true CN203300630U (en) | 2013-11-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013202726822U Expired - Lifetime CN203300630U (en) | 2013-05-20 | 2013-05-20 | Back-surface metallized structure for P-type silicon chip device and applicable to eutectic soldering process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019200515A1 (en) * | 2018-04-16 | 2019-10-24 | 华为技术有限公司 | Chip, chip package structure, and packaging method |
-
2013
- 2013-05-20 CN CN2013202726822U patent/CN203300630U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019200515A1 (en) * | 2018-04-16 | 2019-10-24 | 华为技术有限公司 | Chip, chip package structure, and packaging method |
| CN111886684A (en) * | 2018-04-16 | 2020-11-03 | 华为技术有限公司 | Chip, chip packaging structure and packaging method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131120 |
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| CX01 | Expiry of patent term |