CN115579036A - DDR (double data Rate) continuous storage circuit based on FPGA (field programmable Gate array) and implementation method thereof - Google Patents
DDR (double data Rate) continuous storage circuit based on FPGA (field programmable Gate array) and implementation method thereof Download PDFInfo
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Abstract
The application relates to the field of integrated circuits, and discloses a DDR (double data rate) continuous storage circuit based on an FPGA (field programmable gate array) and an implementation method thereof. The circuit comprises a sampling cache module, a data switching module, a first register, a second register, a data processing module, an address switching module and a memory controller. When the memory controller sends out an interrupt signal: the address switching module controls the sampling cache module to output data to the data switching module, the data switching module stops sending the data, the received data are sequentially stored in the first register and the second register respectively, and the data processing module stops forwarding the data. After the interruption is finished, the data processing module reads the data stored in the first register and the second register, transmits the data to the memory controller and then continuously forwards the data output by the data processing module to the memory controller; and the memory controller writes the received data into the DDR memory through the DDR physical layer interface.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a DDR (double data Rate) continuous storage circuit based on an FPGA (field programmable Gate array) and an implementation method thereof.
Background
This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
With the rapid development of the information age, the total amount of data is continuously rising, which puts more urgent demands on the speed and capacity of data processing, and in order to solve the problems, a large-capacity and high-bandwidth DDR interface is generated.
Because double-data rate synchronous dynamic random access memory (DDR) has many pins and is complex to operate, people optimize the DDR interface, and the DDR interface is customarily called as a DDR user interface. The interface is realized by combining a Memory Controller (MC) and a physical layer (PHY), wherein the PHY is directly connected with DDR particles, and the problem of time sequence matching of data and addresses between a logic device and the DDR is solved. The other end of the PHY is connected with the MC through the DFI bus, and the interface of the MC, which is connected to the user end, is the DDR user interface.
The user data is written into the DDR, the user data is directly processed into a DFI bus protocol interface and is directly connected to the PHY, but the DFI protocol is relatively complex and is not convenient for operation of general engineers, then the design logic of a user is greatly simplified after the MC is added to the PHY, but the pressure of the MC for processing the data is also increased, an interrupt signal is generated when the MC module processes the high-speed data, the data written by the user is lost during the interrupt period, and the data can be continuously written after the interrupt is finished.
Disclosure of Invention
The present application aims to provide a DDR continuous storage circuit based on an FPGA and a method for implementing the same, which can continuously write data even if a memory controller generates an interrupt signal, and do not lose data after the interrupt is recovered.
The application discloses DDR continuous memory circuit based on FPGA includes: the device comprises a sampling cache module, a data switching module, a first register, a second register, a data processing module, an address switching module and a memory controller;
the sampling cache module is configured to obtain input data and cache the input data;
the address switching module is configured to subtract 2 units from a current address when receiving an interrupt signal sent by the memory controller, and control the sampling buffer module to output two units of data to the data switching module in two clock cycles later;
the data switching module is configured to immediately stop sending data to the data processing module when receiving an interrupt signal sent by the memory controller, and sequentially store the data of the two units received in the following two clock cycles to the first register and the second register respectively;
the data processing module is configured to immediately stop forwarding the data output by the data processing module to the memory controller when receiving an interrupt signal sent by the memory controller, sequentially read the data stored in the first register and the second register and transmit the data to the memory controller in two clock cycles after the interrupt is finished, and then continue to forward the data output by the data processing module to the memory controller;
the memory controller is configured to write the received data to the DDR memory through the DDR physical layer interface.
In a preferred embodiment, when the memory controller does not generate an interrupt, the sampling cache module obtains input data and caches the input data, and then outputs the data to the data switching module, the data switching module sends the data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.
In a preferred embodiment, the sampling buffer module includes a sampling module, a first random access memory and a second random access memory; and the sampling module alternately stores the acquired input data into the first random access memory and the second random access memory.
In a preferred embodiment, the address switching module includes an enable selection module and a first address accumulator, the sample buffer module sends a chip select signal to the enable selection module, the enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal, the first address accumulator is configured to automatically accumulate to a maximum value and then reset to 0 for recounting, and when an interrupt signal sent by the memory controller is received, the current address is subtracted by 2 units.
In a preferred embodiment, when the chip select signal is at a high level, the first read enable signal output by the enable selection module is at a high level, and the second read enable signal is at a low level; or, when the chip select signal is at a low level, the first read enable signal output by the enable selection module is at a low level, and the second read enable signal is at a high level.
In a preferred embodiment, the data processing module includes a second address accumulator and a selector, the second address accumulator is configured to stop address accumulation when receiving an interrupt signal from the memory controller, and continue accumulation after the interrupt is ended, and the selector is configured to arrange the data streams in the data switching module, the first register and the second register in address order and write the data streams into the memory controller in sequence.
In a preferred embodiment, the first random access memory and the second random access memory share one address and data signal.
In a preferred embodiment, the apparatus further includes a phase-locked loop, which provides clock signals to the data processing module, the memory controller, the address switching module, and the data switching module.
The application also discloses a realization method of the DDR continuous storage circuit based on the FPGA, which comprises the following steps:
the sampling cache module acquires input data and caches the input data;
the memory controller sends out an interrupt signal;
when the address switching module receives the interrupt signal, subtracting 2 units from the current address, and controlling the sampling cache module to output the data of the two units to the data switching module in two subsequent clock cycles;
the data switching module immediately stops sending data to the data processing module when receiving the interrupt signal, and respectively and sequentially stores the data of the two units received in the following two clock cycles to a first register and a second register;
when the data processing module receives the interrupt signal, the data processing module immediately stops forwarding the data output by the data processing module to the memory controller;
the memory controller interrupts;
the data processing module sequentially reads the data stored in the first register and the second register and transmits the data to the memory controller in two clock cycles after the interruption is finished, and then continuously forwards the data output by the data processing module to the memory controller;
and the memory controller writes the received data into the DDR memory through the DDR physical layer interface.
In a preferred embodiment, the sampling and buffering module obtaining input data and buffering further includes the sampling module obtaining input data and alternately storing the input data in the first random access memory and the second random access memory.
In the embodiment of the application, when data interruption is met, DDR can be written in a seamless connection mode.
Further, two random access memories are adopted, and after the interruption occurs, the address of the lost data in the random access memories is recalculated, so that the data loss can be prevented.
Furthermore, the sampling module alternately stores the data into the two random access memories, so that read-write collision can be avoided, and the stability of the data is enhanced.
The respective technical features disclosed in the above summary, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings can be freely combined with each other to constitute various new technical solutions (all of which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a sampling module architecture according to one embodiment of the present application;
FIG. 3 is a block diagram of an address switch module according to an embodiment of the present application;
FIG. 4 is a block diagram of a data processing module according to an embodiment of the present application;
FIG. 5 is a timing diagram according to an embodiment of the present application;
FIG. 6 is a schematic flow diagram according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
Description of partial concepts:
a Field Programmable Gate Array (FPGA) is a product of further development based on Programmable devices such as Programmable Array Logic (PAL) and General Array Logic (GAL). The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), not only solves the defects of custom circuits, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
A Random Access Memory (RAM), also called an internal Memory, is an internal Memory that directly exchanges data with a Central Processing Unit (CPU). It can be read and written at any time (except for refreshing), and has high speed, and is usually used as a temporary data storage medium of an operating system or other programs in operation. The RAM can write (store) or read (take out) information from any one of designated addresses at any time when it is operated.
A Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), which is commonly called DDR, is a Synchronous Dynamic Random Access Memory (SDRAM) with Double Data transmission Rate, where the Data transmission Rate is twice the system clock frequency, and the transmission performance is better than that of the conventional SDRAM due to the increased speed.
The memory controller is an important component for controlling the memory inside the computer system and is responsible for data exchange between the memory and the processor. The memory controller determines the maximum memory capacity, memory type and speed, memory grain data depth and data width, and other important parameters that can be used by the processor, that is, determines the memory performance of the processor, thereby having a large impact on the overall performance of the processor.
A phase locked loop is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target frequency.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present application relates to a DDR continuous memory circuit based on an FPGA, a schematic circuit structure of which is shown in fig. 1, and the circuit includes: the device comprises a sampling cache module, a data switching module, a first register, a second register, a data processing module, an address switching module and a memory controller.
The sample buffer module is configured to obtain input data and buffer the input data. Optionally, the sampling buffer module includes a sampling module, a first random access memory and a second random access memory; the sampling module alternately stores the acquired input data to the first random access memory and the second random access memory, so that read-write collision can be avoided, and the stability of the data is enhanced.
The structure of the sampling module is shown in fig. 2. Optionally, the sampling module comprises a data receiving module, an address counter and a data selector. The data input by the user enters the data receiving module, and the data is sampled by the externally input associated clock.
Optionally, the data is first written into the first random access memory, and the enable signal of the first random access memory is at a high level; and the number of samples is counted by an address counter, and when the address is counted to the maximum value of the capacity of a single random access memory, the address value is set to 0, and the first random access memory enable signal is set to low and the second random access memory enable signal is set to high. Alternatively, the data is first written into the second random access memory, with the second random access memory enable signal high, the address value set to 0 when the address counts to the maximum of the capacity of a single random access memory, and the second random access memory enable signal will be set low and the first random access memory enable signal will be set high. The capacity of the random access memory is selected from various types, such as 1024 × 4bit,1024 × 16bit,1024 × 64bit, and the like.
When receiving an interrupt signal sent by a memory controller, the address switching module subtracts 2 units from the current address, and controls the sampling buffer module to output the data of the two units to the data switching module in two clock cycles later, so as to avoid data loss and data continuity.
The structure diagram of the address switching module is shown in fig. 3, and optionally, the address switching module includes an enable selection module and a first address accumulator, the sampling buffer module sends a chip select signal to the enable selection module, and the enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal. The first address accumulator is configured to automatically accumulate to a maximum value and then count again with a 0, subtract 2 units from the current address upon receiving an interrupt signal from the memory controller, and take 0 if the address is less than 2 units.
Optionally, when the chip select signal is at a high level, the first read enable signal output by the enable selection module is at a high level, and the second read enable signal is at a low level; optionally, when the chip select signal is at a low level, the first read enable signal output by the enable selection module is at a low level, and the second read enable signal is at a high level.
When receiving an interrupt signal sent by a memory controller, the data switching module immediately stops sending data to the data processing module, and respectively and sequentially stores the data of the two units received in the following two clock cycles to the first register and the second register. And after the interruption is finished, directly transmitting the data acquired from the sampling cache module to the data processing module.
When receiving an interrupt signal sent by the memory controller, the data processing module immediately stops forwarding the data output by the data processing module to the memory controller, sequentially reads the data stored in the first register and the second register in two clock cycles after the interrupt is finished, transmits the data to the memory controller, and then continues forwarding the data output by the data processing module to the memory controller.
The structure diagram of the data processing module is shown in fig. 4, and optionally, the data processing module includes a second address accumulator and a selector, the second address accumulator is configured to stop address accumulation when receiving an interrupt signal sent by the memory controller, and continue accumulation after the interrupt is ended, and the selector is configured to arrange the data streams in the data switching module, the first register and the second register in order of addresses and write the data streams into the memory controller in sequence.
Optionally, the data switching module to the data processing module is a channel 1, the data switching module to the first register to the data processing module is a channel 2, and the data switching module to the second register to the data processing module is a channel 3. And the data processing module processes data from three channels of the channel 1, the channel 2 and the channel 3, and writes the sorted and sorted data streams into the memory controller in sequence and finally writes the data streams into the DDR when the memory controller is judged to be in an idle state. Optionally, when there is no interrupt, the data may be transmitted on the channel 1 all the time, that is, after the data is transmitted to the data switching module, the data is directly transmitted to the data processing module, and the data processing module forwards the data to the memory controller. When the memory controller sends out an interrupt signal, the module stops backward data transmission, waits for the update values of the first register and the second register, after the interrupt is finished, the data processing module sequentially reads the data of the first register and the data of the second register, or sequentially reads the data of the second register and the data of the first register and forwards the data to the memory controller module, and the third data and the following data are transmitted on the channel 1 until the next interrupt arrives. By adopting the two registers, after the interruption is finished, the data of the channel 1 is not transmitted to the data processing module, and the data of the two units are prepared in advance and stored in the two registers respectively, so that the maximum efficiency of data transmission is ensured.
And the memory controller writes the received data into the DDR memory through the DDR physical layer interface.
Optionally, when the memory controller does not generate an interrupt, the sampling cache module obtains input data and caches the input data, and then outputs the data to the data switching module, the data switching module sends the data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.
Optionally, the first random access memory and the second random access memory share one address and data signal.
Optionally, the circuit further includes a phase-locked loop, where the phase-locked loop provides a clock signal to the data processing module, the memory controller, the address switching module, and the data switching module.
Alternatively, the interrupt signal may be greater than or equal to two clock cycles. Alternatively, the interrupt signal may be less than two clock cycles, and the above embodiment may be handled as if the interrupt signal is equal to the length of two clock cycles.
In order to better understand the technical solution of the present application, the following description is given with reference to a specific example, in which the listed details are mainly for the sake of understanding and are not intended to limit the scope of the present application.
Fig. 5 is a timing chart when an interrupt is generated. In the figure, clk is a clock signal, addr _ ram is a random access memory address, and data _ ddr is data received by ddr. The interrupt signal is at low level, then the interrupt command is sent out because the memory controller processes data busy, at this time, the interrupt signal is at high level, the data processing module stops sending data to the memory controller, the corresponding addr _ ram in the figure stops increasing, the current address subtracts 2 units, and the interrupt is waited to end.
The first register and the second register sequentially store the data of the two units received in two clock cycles after the interrupt occurs, after the interrupt is finished, the data processing module immediately acquires the data of the two units, writes the data into the DDR through the memory controller, and continues to acquire the data from the channel 1 after the data are acquired, so that the data continuity can be realized even if the memory controller is interrupted.
A second embodiment of the present application relates to a method for implementing a DDR continuous memory circuit based on an FPGA, a flowchart of which is shown in fig. 6, and the method includes the following steps:
in step 601, the sample buffer module obtains input data and buffers the input data.
In step 602, the memory controller issues an interrupt signal.
In step 603, the address switching module subtracts 2 units from the current address when receiving the interrupt signal, and controls the sampling buffer module to output the data of two units to the data switching module in the following two clock cycles.
In step 604, the data switching module immediately stops sending data to the data processing module when receiving the interrupt signal, and sequentially stores the data of the two units received in the following two clock cycles to the first register and the second register, respectively.
In step 605, the data processing module immediately stops forwarding the data output by the data processing module to the memory controller when receiving the interrupt signal.
In step 606, the memory controller interrupt ends.
In step 607, the address switching module continues address accumulation after the interrupt ends.
In step 608, the data processing module sequentially reads the data stored in the first register and the second register and transmits the data to the memory controller in two clock cycles after the interrupt is ended, and then continues to forward the data output by the data processing module to the memory controller.
In step 609, the data switching module continues to send data to the data processing module after the interruption is finished.
In step 610, the memory controller writes the received data to the DDR memory through the DDR physical layer interface.
Optionally, in step 601, the obtaining and buffering input data by the sample buffer module may further include: the sampling module acquires input data and alternately stores the input data in the first random access memory and the second random access memory.
This embodiment is a method embodiment corresponding to the first embodiment, and the technical details in the first embodiment may be applied to this embodiment, and the technical details in this embodiment may also be applied to the first embodiment.
It should be noted that, in the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In this application, if a reference is made to performing an action based on an element, it is meant to refer to performing the action based on at least the element, including two cases: performing the action based only on the element, and performing the action based on the element and other elements. Multiple, etc. expressions include 2, 2 2 kinds and more than 2, more than 2 times and more than 2 kinds.
The sequence numbers used in describing the steps of the method do not in themselves constitute any limitation on the order of the steps. For example, the step with the larger sequence number is not necessarily executed after the step with the smaller sequence number, and the step with the larger sequence number may be executed first and then the step with the smaller sequence number may be executed in parallel, as long as the execution sequence is reasonable for those skilled in the art. As another example, multiple steps with consecutive numbered sequence numbers (e.g., step 101, step 102, step 103, etc.) do not limit other steps that may be performed therebetween, e.g., there may be other steps between step 101 and step 102.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment"); however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.
All documents mentioned in this specification are to be considered as being integrally included in the disclosure of the present application so as to be able to be a basis for modification as necessary. It should be understood that the above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Claims (10)
1. A DDR continuous storage circuit based on FPGA is characterized by comprising: the device comprises a sampling cache module, a data switching module, a first register, a second register, a data processing module, an address switching module and a memory controller;
the sampling cache module is configured to obtain input data and cache the input data;
the address switching module is configured to subtract 2 units from a current address when receiving an interrupt signal sent by the memory controller, and control the sampling buffer module to output two units of data to the data switching module in two clock cycles later;
the data switching module is configured to immediately stop sending data to the data processing module when receiving an interrupt signal sent by the memory controller, and sequentially store the data of the two units received in the following two clock cycles to the first register and the second register respectively;
the data processing module is configured to immediately stop forwarding the data output by the data processing module to the memory controller when receiving an interrupt signal sent by the memory controller, sequentially read the data stored in the first register and the second register and transmit the data to the memory controller in two clock cycles after the interrupt is ended, and then continue forwarding the data output by the data processing module to the memory controller;
the memory controller is configured to write the received data to the DDR memory through the DDR physical layer interface.
2. The FPGA-based DDR continuous memory circuit of claim 1, wherein when the memory controller does not generate an interrupt, the sample cache module obtains input data and caches the input data, and outputs the data to the data switch module, the data switch module sends the data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.
3. The FPGA-based DDR continuous memory circuit of claim 1, wherein the sample cache module comprises a sampling module, a first random access memory and a second random access memory; the sampling module alternately stores the acquired input data to the first random access memory and the second random access memory.
4. The FPGA-based DDR sequential storage circuit of claim 3, wherein the address switch module comprises an enable selection module and a first address accumulator, wherein the sample buffer module sends a chip select signal to the enable selection module, the enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal, the first address accumulator is configured to automatically accumulate to a maximum value and then count again with 0, and the current address is subtracted by 2 units upon receiving an interrupt signal from the memory controller.
5. The FPGA-based DDR continuous memory circuit as claimed in claim 4, wherein when said chip select signal is high, said first read enable signal outputted by said enable select module is high, and said second read enable signal is low; or, when the chip select signal is at a low level, the first read enable signal output by the enable selection module is at a low level, and the second read enable signal is at a high level.
6. The FPGA-based DDR scram circuit of claim 1, wherein said data processing module comprises a second address accumulator and a selector, said second address accumulator is configured to stop address accumulation when receiving an interrupt signal from said memory controller and continue accumulation after the interrupt is over, said selector is configured to address-sequentially arrange and sequentially write data streams in said data switching module, said first register and said second register into said memory controller.
7. The FPGA-based DDR sequential storage circuit of claim 3, wherein said first random access memory and said second random access memory share an address and data signal.
8. The FPGA-based DDR continuous memory circuit of claim 1 further comprising a phase locked loop to provide clock signals to said data processing module, said memory controller, said address switching module and said data switching module.
9. A realization method of DDR continuous storage circuit based on FPGA is characterized by comprising the following steps:
the sampling cache module acquires input data and caches the input data;
the memory controller sends out an interrupt signal;
when the address switching module receives the interrupt signal, subtracting 2 units from the current address, and controlling the sampling cache module to output the data of the two units to the data switching module in the following two clock cycles;
the data switching module immediately stops sending data to the data processing module when receiving the interrupt signal, and respectively and sequentially stores the data of the two units received in the following two clock cycles to a first register and a second register;
when the data processing module receives the interrupt signal, the data processing module immediately stops forwarding the data output by the data processing module to the memory controller;
the memory controller interrupt ends;
the data processing module sequentially reads the data stored in the first register and the second register and transmits the data to the memory controller in two clock cycles after the interruption is finished, and then continuously forwards the data output by the data processing module to the memory controller;
and the memory controller writes the received data into the DDR memory through the DDR physical layer interface.
10. The method as claimed in claim 9, wherein the sampling buffer module obtains the input data and buffers the input data, and the sampling module obtains the input data and alternately stores the input data in the first random access memory and the second random access memory.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118152013A (en) * | 2024-05-13 | 2024-06-07 | 此芯科技(北京)有限公司 | Assembly line module interaction circuit, system on chip and electronic equipment |
| CN118734757A (en) * | 2024-09-04 | 2024-10-01 | 成都维德青云电子有限公司 | DDR physical layer interface circuit based on FPGA and control method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118152013A (en) * | 2024-05-13 | 2024-06-07 | 此芯科技(北京)有限公司 | Assembly line module interaction circuit, system on chip and electronic equipment |
| CN118152013B (en) * | 2024-05-13 | 2024-08-02 | 此芯科技(北京)有限公司 | Assembly line module interaction circuit, system on chip and electronic equipment |
| CN118734757A (en) * | 2024-09-04 | 2024-10-01 | 成都维德青云电子有限公司 | DDR physical layer interface circuit based on FPGA and control method thereof |
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