CN113132654A - Multi-video source splicing processing method and device and video splicer - Google Patents
Multi-video source splicing processing method and device and video splicer Download PDFInfo
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Abstract
The embodiment of the invention discloses a multi-video source splicing processing method and device and a video splicer. The multi-video source splicing processing method comprises the following steps: caching a plurality of video sources to be spliced to a plurality of first cache areas according to preset input bit widths; respectively transferring the video sources to be spliced which are respectively cached to the first cache areas to a first cache subarea by a preset output bit width; switching the video source to be spliced with the data storage length meeting the specified length to a corresponding second cache subarea cached to a plurality of second cache subareas by the preset output bit width; and controlling the video source to be spliced which is transferred to the corresponding first cache subarea to be stored in a designated area of a target memory according to the memory writing request recorded to the third cache area. The embodiment of the invention effectively solves the problems that the existing multi-video source splicing processing method can cause the BRAM resource of the programmable logic device to be consumed greatly and waste much.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a multi-video source splicing processing method, a multi-video source splicing processing device and a video splicer.
Background
When a plurality of video sources to be spliced are spliced on a memory in a multi-video splicer, each video source to be spliced needs two mutually ping-pong cache regions for caching image data, and the data write bit width of each cache region facing the source to be spliced is far smaller than the data read bit width facing the memory. For example: the width of the spliced complete image is 2048, the data input bit width of each video source to be spliced is 32 bits, and when the data reading bit width of the memory is 512 bits, if the cache depth of each video source to be spliced is 4096, two cache areas which are ping-pong to each other can just cache two lines of image data of the spliced complete image; when the configuration scheme is adopted in a programmable logic device, each video source to be spliced consumes 7.5 BRAM (Block Ram) resources of the programmable logic device, if the programmable logic device accesses 4 video sources to be spliced, 30 BRAM resources of the programmable logic device are consumed, but when the cache depth of one BRAM resource of the programmable logic device is 8192, the number of the BRAM resources actually consumed by the programmable logic device is 7.5.
Therefore, the existing multi-video source splicing processing method can cause the consumption of BRAM resources of the programmable logic device to be large and waste to a large extent.
Disclosure of Invention
In order to overcome the defects and shortcomings of the prior art, the embodiment of the invention provides a multi-video source splicing processing method, a multi-video source splicing processing device and a video splicer.
On one hand, the multi-video source splicing processing method provided by the embodiment of the invention comprises the following steps: caching a plurality of video sources to be spliced to a plurality of first cache areas according to preset input bit widths; respectively transferring the plurality of video sources to be spliced, which are respectively cached to the plurality of first cache regions, to a plurality of first cache subregions of a second cache region by using a preset output bit width, wherein the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than 1; polling whether the data storage lengths of the plurality of video sources to be spliced in the plurality of first cache subareas respectively meet a specified length, and when the data storage length of each video source to be spliced in the corresponding first cache subarea meets the specified length, initiating a memory write request, recording the memory write request to a third cache area, and switching the video source to be spliced with the data storage length meeting the specified length to a corresponding second cache subarea in a plurality of second cache subareas cached to a fourth cache area in the preset output bit width; and controlling the video sources to be spliced which are transferred to the corresponding first cache subarea to be stored in a designated area of a target memory according to the memory writing request recorded to the third cache area, so as to splice the video sources to be spliced in the target memory.
In this embodiment, a plurality of video sources to be spliced are respectively cached to a plurality of corresponding first cache regions by a preset input bit width, image data of the plurality of video sources to be spliced, which are respectively cached in the plurality of first cache regions, are transferred to a second cache region or a fourth cache region by a preset output bit width according to a time division multiplexing principle, and the image data of the plurality of video sources to be spliced, which are cached in the second cache region and the fourth cache region and ping-pong with each other, are transferred to a target memory according to a memory write request, so that the plurality of spliced video sources are spliced in the target memory; the video sources to be spliced actually consume the second cache region and the fourth cache region in the programmable logic device, so that BRAM resources of the programmable logic device are saved.
In an embodiment of the present invention, the respectively transferring the plurality of video sources to be spliced, which are respectively cached in the plurality of first cache regions, to a plurality of first cache subregions of a second cache region by using a preset output bit width includes: polling a plurality of cache states of the plurality of video sources to be spliced in the plurality of first cache regions respectively, and when any one of the cache states meets a target state, transferring the video sources to be spliced, of which the cache states meet the target state, in the plurality of video sources to be spliced to the corresponding first cache subarea in the plurality of first cache subareas by using the preset output bit width.
In an embodiment of the present invention, the controlling, according to the memory write request recorded to the third cache region, the to-be-spliced video source that has been transferred to the corresponding first cache subregion to be stored in a specified region of a target memory, so as to implement splicing of the plurality of to-be-spliced video sources in the target memory specifically includes: and controlling the target memory to be communicated with the second cache region and storing the video source to be spliced which is transferred to the corresponding first cache subregion to the designated region of the target memory according to a video source identifier contained in the memory write request, an identifier of the second cache region, a start address of the requested data writing and the length of the requested data writing.
In an embodiment of the present invention, the caching the plurality of video sources to be spliced to the plurality of first cache regions according to the preset input bit width respectively includes: caching each video source to be spliced to the plurality of first-in first-out cache areas of the first cache area corresponding to the video source to be spliced in the preset input bit width and a sequential alternate mode, wherein the input bit width and the output bit width of the plurality of first-in first-out cache areas are equal and equal to the preset input bit width.
In an embodiment of the present invention, the caching the plurality of video sources to be spliced to the plurality of first cache regions according to the preset input bit width respectively includes: caching each video source to be spliced to a double-port RAM of the first cache region corresponding to the video source to be spliced according to the preset input bit width, wherein the double-port RAM is provided with the preset input bit width and the preset output bit width.
On the other hand, an apparatus for splicing multiple video sources according to an embodiment of the present invention includes: the data conversion module is used for caching a plurality of video sources to be spliced into a plurality of first cache areas according to preset input bit widths; the data unloading module is used for unloading the video sources to be spliced which are respectively cached in the first cache regions to a plurality of first cache subregions of a second cache region by a preset output bit width, wherein the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than or equal to 1; the state polling machine is used for polling whether the data storage lengths of the video sources to be spliced in the first cache subareas respectively meet the specified length, and when the data storage length of each video source to be spliced in the corresponding first cache subarea meets the specified length, initiating a memory write request, recording the memory write request to a third cache area, and switching the video source to be spliced with the data storage length meeting the specified length to a second cache subarea corresponding to a plurality of second cache subareas cached to a fourth cache area by the preset output bit width; and the write control module is used for controlling the video sources to be spliced which are transferred to the corresponding first cache subarea to be stored in a designated area of a target memory according to the memory write request recorded to the third cache area so as to realize splicing of the video sources to be spliced in the target memory.
In an embodiment of the present invention, the data unloading module is specifically configured to: polling a plurality of cache states of the plurality of video sources to be spliced in the plurality of first cache regions respectively, and when any one of the cache states meets a target state, transferring the video sources to be spliced, of which the cache states meet the target state, in the plurality of video sources to be spliced to the corresponding first cache subarea in the plurality of first cache subareas by using the preset output bit width. .
In an embodiment of the present invention, the write control module is specifically configured to: and controlling the target memory to be communicated with the second cache region and storing the video source to be spliced which is transferred to the corresponding first cache subregion to the designated region of the target memory according to a video source identifier contained in the memory write request, an identifier of the second cache region, a start address of the requested data writing and the length of the requested data writing. .
In an embodiment of the present invention, the data conversion module is specifically configured to: caching each video source to be spliced to a plurality of first-in first-out cache areas of the first cache area corresponding to the video source to be spliced in a preset input bit width and sequential alternate mode, wherein the input bit width and the output bit width of the first-in first-out cache areas are equal and equal to the preset input bit width; or caching each video source to be spliced to a double-port RAM of the first cache region corresponding to the video source to be spliced according to the preset input bit width, wherein the double-port RAM is provided with the preset input bit width and the preset output bit width.
In another aspect, an embodiment of the present invention provides a video splicer, including: a programmable logic device, configured to execute the multi-video source stitching processing method according to any one of the above items, where the plurality of first buffer areas, the second buffer area, the third buffer area, and the fourth buffer area are built in the programmable logic device; and the volatile memory is electrically connected with the programmable logic device and is used as the target memory.
In summary, the above embodiments of the present application may have the following advantages or beneficial effects: caching a plurality of video sources to be spliced to a plurality of corresponding first cache regions according to a preset input bit width, transferring image data of the video sources to be spliced, which are cached in the first cache regions respectively, to a second cache region or a fourth cache region according to a time division multiplexing principle according to a preset output bit width, and transmitting the image data of the video sources to be spliced, which are cached in the second cache region and the fourth cache region and are ping-pong with each other, to a target memory according to a memory write request so as to splice the plurality of spliced video sources in the target memory; the video sources to be spliced actually consume the second cache region and the fourth cache region in the programmable logic device, so that BRAM resources of the programmable logic device are saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a video splicer according to a first embodiment of the present invention.
Fig. 2 is a schematic flowchart of a multi-video source splicing processing method according to an embodiment of the present invention.
Fig. 3 is a schematic process diagram of a programmable logic device implementing the multi-video source stitching processing method.
Fig. 4 is another process diagram of the programmable logic device implementing the multi-video source stitching processing method.
Fig. 5 is a block diagram of a multi-video source splicing apparatus according to a second embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a multi-video source splicing processing system according to a third embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a computer-readable storage medium according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1, a video splicer according to a first embodiment of the invention is shown, where the video splicer 200 includes, for example, a programmable logic device 210 and a volatile memory 220 electrically connected to the programmable logic device 210.
The Programmable logic device 210 may be an FPGA (Field Programmable Gate Array) device; the volatile memory 220 may be a DDR (Double Data Rate) memory. The programmable logic device 210 is configured to receive a plurality of video sources to be stitched and execute a multi-video source stitching processing method to achieve stitching of the plurality of video sources to be stitched in the volatile memory 220.
Referring to fig. 2, the multi-video source splicing processing method includes, for example:
step S10, caching a plurality of video sources to be spliced to a plurality of first cache areas by preset input bit widths respectively;
step S30, respectively dumping the plurality of video sources to be spliced, which are respectively cached in the plurality of first cache regions, to a plurality of first cache subregions of a second cache region by a preset output bit width, where the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than 1;
step S50, polling whether the data storage lengths of the multiple video sources to be spliced in the multiple first buffer sub-areas respectively satisfy a specified length, and when the data storage length of the corresponding first buffer sub-area of each video source to be spliced satisfies the specified length, initiating a memory write request, recording the memory write request to a third buffer area, and switching the video source to be spliced whose data storage length satisfies the specified length to a corresponding second buffer sub-area in multiple second buffer sub-areas buffered to a fourth buffer area with the preset output bit width; and
step S70, according to the memory write request recorded to the third cache region, controlling the video source to be stitched that has been transferred to the corresponding first cache subregion to be stored in a designated region of a target memory, so as to implement the stitching of the plurality of video sources to be stitched in the target memory.
For better understanding of the present embodiment, two different specific implementations of the multi-video source splicing processing method will be described in detail below with reference to fig. 3 and 4.
[ PROPERTIES OF EMBODIMENT I ]
Referring to fig. 3, input sources 0 to 3 are four video sources to be spliced, and the four video sources to be spliced correspond to four first buffer areas; for example, each video source to be spliced is cached to the corresponding first cache region by an input bit width of 32 bits, and the four first cache regions are internal memories of the programmable logic device 210.
Each of the First buffer areas may include a plurality of, for example, 4 First-in First-out buffer areas, where the First-in First-out buffer areas may be FIFO (First Input First Output) memories inside the programmable logic device 210, and a data read-write bit width of each FIFO memory and an Input bit width of a corresponding video source to be spliced are both 32 bits; when each video source to be spliced is input to the programmable logic device 210 with an input bit width of 32 bits, the video sources to be spliced are alternately cached in the corresponding four FIFO memories, and when all the empty signals of the four FIFO memories are pulled low, the image data cached in the four FIFO memories by the video sources to be spliced are transferred to the second cache region or the fourth cache region.
The data unloading module polls the first cache regions and is used for unloading the image data cached in the first cache regions to a second cache region or a fourth cache region in sequence, wherein the second cache region and the fourth cache region are ping-pong, the second cache region comprises a plurality of first cache subregions respectively corresponding to the video sources to be spliced, and the fourth cache region comprises a plurality of second cache subregions respectively corresponding to the video sources to be spliced; the second cache region and the fourth cache region are respectively the built-in memories of the programmable logic device 210, and the target memory is the volatile memory 220.
Specifically, the data dump module polls the buffer states of the plurality of first buffer areas in sequence, and when the buffer state of any one of the first buffer areas is that all null signals are pulled low, that is, when all the null signals of the four FIFO memories of the first buffer area are pulled low, the image data buffered in the four FIFO memories with all the null signals pulled low is dumped into the first buffer subarea corresponding to the video source to be spliced in the second buffer area by using the output bit width of 128 bit.
Since the data conversion module stores the video sources to be spliced in the four FIFOs of the corresponding first buffer areas, therefore, the empty signals of the four FIFOs are all pulled low by 4 clock cycles, the corresponding data dump module can complete the polling of the four first buffer areas in 4 clock cycles, and the image data buffered in the first buffer area where the empty signal is all pulled down is dumped in each clock cycle, therefore, the data unloading module can sequentially unload the data cached in the four first cache regions into the corresponding first cache subareas in the second cache region (or into the corresponding second cache subareas in the fourth cache region) in four clock cycles, therefore, the data conversion module can not generate data accumulation, and the depth of the FIFO memory is set to be 32bit to meet the requirement, therefore, the caching operation of 32-bit input bit width and 128-bit output bit width is realized for each video source to be spliced.
The state polling machine is configured to poll whether data storage lengths of a plurality of first buffer sub-areas (or a plurality of second buffer sub-areas in a fourth buffer area) in which the plurality of video sources to be spliced are respectively cached in the second buffer area satisfy a specified length, where the specified length is, for example, a length of one line of image data of the video sources to be spliced, that is, when the data storage length of the image data cached in the first buffer sub-area is one line of image data of the corresponding video source to be spliced, initiate a memory write request, and record the memory write request to a third buffer area, where the third buffer area is an internal memory of the programmable logic device 210, and switch and cache the video sources to be spliced into the second buffer sub-area corresponding to the video sources to be spliced in the fourth buffer area.
When the memory write request record in the third cache region is not empty, the memory write request in the third cache region is not responded, the write control module initiates the memory write request, and when the target memory responds to the memory write request, the write control module transmits corresponding image data into the target memory according to the memory write request; after completing the memory write request once, continuously checking whether the memory write request record in the third cache region is empty, and executing the next memory write request when the memory write request record is not empty.
The process that the write control module transfers the corresponding image data into the target memory according to the memory write request specifically comprises the following steps: the memory writing request comprises a video source identifier associated with a video to be spliced, an identifier of the second cache region or an identifier of the fourth cache region, a start address of the requested writing data on the target memory and the length of the requested writing data; the write control module and the MUX module connect the corresponding second cache region or the fourth cache region to the target memory according to the identifier of the second cache region or the identifier of the fourth cache region, and further control, according to the memory write request recorded in the third cache region, that image data of a video source to be spliced (corresponding to the video source identifier) cached in the corresponding second cache region or the fourth cache region (i.e., image data of a specified length cached in the first cache subregion or the second cache subregion corresponding to the video source to be spliced) is stored in a specified region of the target memory (i.e., a region corresponding to the start address of the requested write data and the length of the requested write data), so as to realize splicing of the four spliced video sources in the target memory.
In the above specific implementation process, for example, the input bit width of the second buffer area and the input bit width of the fourth buffer area are both 128 bits, the output bit width of the second buffer area and the output bit width of the fourth buffer area are, for example, 512 bits, and the storage depth is, for example, 8192, so that the second buffer area and the fourth buffer area respectively consume 7.5 BRAM resources of the programmable logic device 210, the plurality of first buffer sub-areas of the second buffer area can respectively buffer one line of image data of the corresponding video source to be spliced, and similarly, the plurality of second buffer sub-areas of the fourth buffer area can respectively buffer one line of image data of the corresponding video source to be spliced; therefore, the second buffer area and the fourth buffer area can buffer two lines of image data of four video sources to be spliced to realize ping-pong operation, so that the second buffer area and the fourth buffer area consume 15 BRAM resources of the programmable logic device 210.
In another specific embodiment, the multiple first buffer areas may also be multiple dual-port RAMs, where the dual-port RAMs have a preset input bit width, for example, 32 bits, and a preset output bit width, for example, 128 bits, and a process of caching the multiple video sources to be spliced respectively by using the multiple dual-port RAMs and transferring the image data, cached in the multiple video sources to be spliced respectively, in the multiple dual-port RAMs to the second buffer area or the fourth buffer area is similar to the process of using the first buffer area as the multiple FIFO resources, which is not described herein again.
[ MEANS FOR CARRYING OUT THE PROCEDURE II ]
Referring to fig. 4, the video sources to be spliced are divided into a plurality of groups, for example, 2 groups, each group of video sources to be spliced corresponds to a data conversion module, a data dump module and a write control module, the plurality of groups of video sources to be spliced correspond to the same target storage, and the process of splicing each group of video sources to be spliced and the corresponding data dump module, data dump module and write control module on the target storage in cooperation with each other is the same as the process of splicing the plurality of video sources to be spliced on the target storage, and is not repeated here; of course, embodiments of the invention are not limited thereto.
In summary, in the embodiments of the present invention, a plurality of video sources to be spliced are respectively cached in a preset input bit width to a plurality of corresponding first cache regions, image data of the plurality of video sources to be spliced, which are respectively cached in the plurality of first cache regions, are transferred to a second cache region or a fourth cache region according to a time division multiplexing principle by using a preset output bit width, and image data of the plurality of video sources to be spliced, which are cached in the second cache region and the fourth cache region and are ping-pong to each other, are transferred to a target memory according to a memory write request, so as to splice the plurality of spliced video sources in the target memory; the video sources to be spliced actually consume the second cache region and the fourth cache region in the programmable logic device, so that BRAM resources of the programmable logic device are saved. In addition, it should be noted that the input bit width 32bit and the output bit width 128bit of the first buffer area, and the output bit width 512bit of the second and fourth buffer areas are only examples, and are not used to limit the embodiments of the present invention; for example, when the number of the video sources to be spliced is 8 and the input bit width of the first buffer area still adopts 32 bits, the output bit width of the first buffer area should be designed to be 32 bits by 8-256 bits.
[ second embodiment ]
Referring to fig. 5, a multi-video source splicing processing apparatus according to a second embodiment of the present invention is provided, where the multi-video source splicing processing apparatus 100 includes:
the data conversion module 10 is configured to cache a plurality of video sources to be spliced to a plurality of first cache regions according to a preset input bit width;
a data unloading module 30, configured to unload, to a plurality of first buffer sub-areas of a second buffer area, the plurality of video sources to be spliced, which are respectively buffered in the plurality of first buffer areas, by a preset output bit width, where the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than or equal to 1;
the state polling machine 50 is configured to poll whether the data storage lengths of the video sources to be spliced in the first cache subregions respectively satisfy a specified length, and initiate a memory write request when the data storage length of each video source to be spliced in the corresponding first cache subregion satisfies the specified length, record the memory write request to a third cache region, and switch the video source to be spliced whose data storage length satisfies the specified length to a corresponding second cache subregion in a plurality of second cache subregions that are cached to a fourth cache region in the preset output bit width; and
and a write control module 70, configured to control, according to the memory write request recorded to the third cache region, the video source to be stitched that has been transferred to the corresponding first cache subregion to be stored in a specified region of a target memory, so as to implement the stitching of the multiple video sources to be stitched in the target memory.
For the detailed functional details of the data conversion module 10, the data unloading module 30, the status poll machine 50 and the write control module 70, reference may be made to the related descriptions of steps S10, S30, S50 and S70 in the foregoing first embodiment, and further description is omitted here. Further, it is noted that the data conversion module 10, the data dump module 30, the status poll machine 50 and the write control module 70 may be software modules stored in a non-volatile memory and executed by a processor to perform the operations of steps S10, S30, S50 and S70 in the first embodiment.
[ third embodiment ]
Referring to fig. 6, which is a schematic structural diagram of a multi-video source stitching processing system according to a third embodiment of the present invention, the multi-video source stitching processing system 400 includes, for example, a processor 430 and a memory 410 electrically connected to the processor 430, the memory 410 stores a computer program 411, and the processor 430 executes the computer program 411 to implement the multi-video source stitching processing method according to the first embodiment.
[ fourth example ] A
Referring to fig. 7, it is a schematic structural diagram of a computer-readable storage medium according to a fourth embodiment of the present invention, where the computer-readable storage medium 500 is, for example, a non-volatile memory, and it is, for example: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions, such as Read Only Memories (ROMs), flash memories, and the like. The computer-readable storage medium 500 has stored thereon computer-executable instructions 510. The computer-readable storage medium 500 may execute the computer-executable instructions 510 by one or more processors or processing devices to implement the multi-video source stitching processing method as described in the first embodiment above.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A multi-video source splicing processing method is characterized by comprising the following steps:
caching a plurality of video sources to be spliced to a plurality of first cache areas according to preset input bit widths;
respectively transferring the plurality of video sources to be spliced, which are respectively cached to the plurality of first cache regions, to a plurality of first cache subregions of a second cache region by using a preset output bit width, wherein the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than 1;
polling whether the data storage lengths of the plurality of video sources to be spliced in the plurality of first cache subareas respectively meet a specified length, and when the data storage length of each video source to be spliced in the corresponding first cache subarea meets the specified length, initiating a memory write request, recording the memory write request to a third cache area, and switching the video source to be spliced with the data storage length meeting the specified length to a corresponding second cache subarea in a plurality of second cache subareas cached to a fourth cache area in the preset output bit width; and
and controlling the video sources to be spliced which are transferred to the corresponding first cache subarea to be stored in a designated area of a target memory according to the memory writing request recorded to the third cache area, so as to splice the video sources to be spliced in the target memory.
2. The method as claimed in claim 1, wherein the transferring the video sources to be stitched respectively buffered in the first buffer areas to the first buffer sub-areas of the second buffer area by a preset output bit width comprises:
polling a plurality of cache states of the plurality of video sources to be spliced in the plurality of first cache regions respectively, and when any one of the cache states meets a target state, transferring the video sources to be spliced, of which the cache states meet the target state, in the plurality of video sources to be spliced to the corresponding first cache subarea in the plurality of first cache subareas by using the preset output bit width.
3. The method according to claim 1, wherein the controlling, according to the memory write request recorded to the third cache region, the to-be-stitched video source that has been transferred to the corresponding first cache subregion to be stored in a designated region of a target memory, so as to achieve stitching of the to-be-stitched video sources in the target memory comprises:
and controlling the target memory to be communicated with the second cache region and storing the video source to be spliced which is transferred to the corresponding first cache subregion to the designated region of the target memory according to a video source identifier contained in the memory write request, an identifier of the second cache region, a start address of the requested data writing and the length of the requested data writing.
4. The multi-video source splicing processing method according to claim 1, wherein caching the plurality of video sources to be spliced to the plurality of first cache regions according to a preset input bit width respectively comprises:
caching each video source to be spliced to the plurality of first-in first-out cache areas of the first cache area corresponding to the video source to be spliced in the preset input bit width and a sequential alternate mode, wherein the input bit width and the output bit width of the plurality of first-in first-out cache areas are equal and equal to the preset input bit width.
5. The multi-video source splicing processing method according to claim 1, wherein caching the plurality of video sources to be spliced to the plurality of first cache regions according to a preset input bit width respectively comprises:
caching each video source to be spliced to a double-port RAM of the first cache region corresponding to the video source to be spliced according to the preset input bit width, wherein the double-port RAM is provided with the preset input bit width and the preset output bit width.
6. A multi-video source splicing processing device is characterized by comprising:
the data conversion module is used for caching a plurality of video sources to be spliced into a plurality of first cache areas according to preset input bit widths;
the data unloading module is used for unloading the video sources to be spliced which are respectively cached in the first cache regions to a plurality of first cache subregions of a second cache region by a preset output bit width, wherein the preset output bit width is N times of the preset input bit width, and N is a positive integer greater than or equal to 1;
the state polling machine is used for polling whether the data storage lengths of the video sources to be spliced in the first cache subareas respectively meet the specified length, and when the data storage length of each video source to be spliced in the corresponding first cache subarea meets the specified length, initiating a memory write request, recording the memory write request to a third cache area, and switching the video source to be spliced with the data storage length meeting the specified length to a second cache subarea corresponding to a plurality of second cache subareas cached to a fourth cache area by the preset output bit width; and
and the write control module is used for controlling the video sources to be spliced which are transferred to the corresponding first cache subarea to be stored in a designated area of a target memory according to the memory write request recorded to the third cache area, so as to splice the video sources to be spliced in the target memory.
7. The multi-video source splicing processing device according to claim 6, wherein the data unloading module is specifically configured to:
polling a plurality of cache states of the plurality of video sources to be spliced in the plurality of first cache regions respectively, and when any one of the cache states meets a target state, transferring the video sources to be spliced, of which the cache states meet the target state, in the plurality of video sources to be spliced to the corresponding first cache subarea in the plurality of first cache subareas by using the preset output bit width.
8. The multi-video source splicing processing device according to claim 6, wherein the write control module is specifically configured to:
and controlling the target memory to be communicated with the second cache region and storing the video source to be spliced which is transferred to the corresponding first cache subregion to the designated region of the target memory according to a video source identifier contained in the memory write request, an identifier of the second cache region, a start address of the requested data writing and the length of the requested data writing.
9. The multi-video source splicing processing device according to claim 6, wherein the data conversion module is specifically configured to:
caching each video source to be spliced to a plurality of first-in first-out cache areas of the first cache area corresponding to the video source to be spliced in a preset input bit width and sequential alternate mode, wherein the input bit width and the output bit width of the first-in first-out cache areas are equal and equal to the preset input bit width; or
Caching each video source to be spliced to a double-port RAM of the first cache region corresponding to the video source to be spliced according to the preset input bit width, wherein the double-port RAM is provided with the preset input bit width and the preset output bit width.
10. A video splicer, comprising:
the programmable logic device is used for executing the multi-video source splicing processing method according to any one of claims 1 to 5, wherein the plurality of first buffer areas, the second buffer area, the third buffer area and the fourth buffer area are arranged in the programmable logic device; and
and the volatile memory is electrically connected with the programmable logic device and is used as the target memory.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113890746A (en) * | 2021-08-16 | 2022-01-04 | 曙光信息产业(北京)有限公司 | Attack traffic identification method, device, equipment and storage medium |
| CN113986792A (en) * | 2021-10-26 | 2022-01-28 | 新华三信息安全技术有限公司 | Data bit width conversion method and communication equipment |
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| CN110134366A (en) * | 2019-05-21 | 2019-08-16 | 合肥工业大学 | A kind of method and device being written in parallel to multichannel FIFO |
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| CN110134366A (en) * | 2019-05-21 | 2019-08-16 | 合肥工业大学 | A kind of method and device being written in parallel to multichannel FIFO |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113890746A (en) * | 2021-08-16 | 2022-01-04 | 曙光信息产业(北京)有限公司 | Attack traffic identification method, device, equipment and storage medium |
| CN113890746B (en) * | 2021-08-16 | 2024-05-07 | 曙光信息产业(北京)有限公司 | Attack traffic identification method, device, equipment and storage medium |
| CN113986792A (en) * | 2021-10-26 | 2022-01-28 | 新华三信息安全技术有限公司 | Data bit width conversion method and communication equipment |
| CN113986792B (en) * | 2021-10-26 | 2024-05-24 | 新华三信息安全技术有限公司 | Data bit width conversion method and communication equipment |
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