CN111400213A - Method, device and system for transmitting data - Google Patents
Method, device and system for transmitting data Download PDFInfo
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- CN111400213A CN111400213A CN201910935871.5A CN201910935871A CN111400213A CN 111400213 A CN111400213 A CN 111400213A CN 201910935871 A CN201910935871 A CN 201910935871A CN 111400213 A CN111400213 A CN 111400213A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17331—Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
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Abstract
The disclosure provides a method, a device and a system for transmitting data, and belongs to the technical field of computers. The method comprises the following steps: the memory area of the sending end comprises a data memory area and a control memory area, wherein address information of the data memory area of the receiving end is stored in the control memory area of the sending end, when data is sent, target data is obtained and stored in the data memory area, according to the data volume of the target data, the address information of a target memory block into which the target data is written is obtained in the control memory area of the sending end, wherein the target memory block belongs to the receiving end, according to the address information of the target memory block, the target data is written into the target memory block through unilateral operation, and after the receiving end processes the target data, a confirmation message sent through unilateral operation is received. By adopting the method and the device, the overall transmission performance can be improved.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a system for transmitting data.
Background
With the development of computer technology and network technology, a large amount of data is transmitted between two network devices, and thus, the delay of data transmission directly affects the efficiency of data processing. In order to increase the delay of data transmission, a high-bandwidth and low-delay network transmission technology, namely, an RDMA (Remote Direct Memory Access) technology, is proposed.
In the related technology, when using RDMA technology, each time when sending data, the sending end uses one-time bilateral operation to obtain the memory address information of the receiving end, the sending end uses unilateral operation to read and write the memory, the receiving end uses bilateral operation to inform the sending end that the data processing of a certain memory block is finished, the memory block can be continuously used, and the multiplexing of the memory block is realized.
Because the memory is read and written by using the single-side operation, and the communication of the double-side operation needs to be additionally carried out, the transmission delay is increased, and the transmission performance is poorer.
Disclosure of Invention
In order to solve the problem of poor transmission performance, the embodiments of the present disclosure provide a method, an apparatus, and a system for transmitting data. The technical scheme is as follows:
in a first aspect, a method for transmitting data is provided, where a memory area of a transmitting end includes a data memory area and a control memory area, and address information of the data memory area of a receiving end is stored in the control memory area of the transmitting end, and the method includes:
acquiring target data and storing the target data in the data memory area;
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a control memory area of the sending end, wherein the target memory block belongs to the receiving end;
writing the target data into the target memory block through unilateral operation according to the address information of the target memory block;
and receiving a confirmation message sent by the receiving end through unilateral operation after the target data is processed by the receiving end.
Optionally, the method further includes:
adding a sending task of the target data to a first queue of a control memory area of the sending end, wherein the sending task comprises address information of the target memory block;
the writing the target data into the target memory block through a single-side operation according to the address information of the target memory block includes:
when the sending task of the target data starts to be processed in the first queue, the target data is written into the target memory block through a single-side operation according to the address information of the target memory block.
Optionally, the obtaining, according to the data size of the target data, address information of a target memory block into which the target data is to be written in a control memory area of the sending end includes:
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a second queue of a control memory area of the sending end, wherein the second queue is used for storing the address information of unallocated memories; deleting the address information of the target memory block from the second queue;
the method further comprises the following steps:
after the completion of the processing of the sending task of the target data is detected, deleting the sending task of the target data in the first queue, and adding a waiting task corresponding to the target data to a third queue of a control memory area of the sending end, wherein the third queue is used for storing the sent sending task;
and after receiving the confirmation message, restoring the address information of the target memory block to the second queue.
Optionally, after receiving the acknowledgment message, restoring the address information of the target memory block to the second queue includes:
after receiving the acknowledgment message, if the adjacent memory block of the target memory block exists in the third queue and the adjacent memory block corresponds to the acknowledgment message, merging the target memory block and the adjacent memory block, and restoring address information of the merged memory block to the second queue.
Optionally, the method further includes:
determining a memory grade to which the merged memory block belongs in the third queue based on the capacity of the merged memory block;
and updating the address information of the merged memory block to an address information area corresponding to the memory rank in the third queue.
Optionally, the restoring the address information of the merged memory block to the second queue includes:
and if the merging period is reached or the memory space of the second queue is insufficient, restoring the address information of the merged memory block to the second queue.
In a second aspect, a method for transmitting data is provided, which is applied to a receiving end, where a memory area of the receiving end includes a data memory area and a control memory area, and the method includes:
processing target data written in a target memory block by a sending end through unilateral operation after determining the target data;
and after the target data is processed, sending a confirmation message of the target memory block to the sending end through unilateral operation.
Optionally, the method further includes:
when the target memory block writes data, adding a task record of the target memory block in a fourth queue of a control memory area of the receiving end;
the processing the target data comprises:
after the data writing of the target memory block is completed, deleting the task record in the fourth queue, and adding the task record in a fifth queue of a control memory area of the receiving end;
when the target data is detected to be processed completely, deleting task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of the receiving end;
after the target data is processed, sending a confirmation message of the target memory block to the sending end through a unilateral operation, including:
after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
In a third aspect, a device for transmitting data is provided, where a memory area of a transmitting end includes a data memory area and a control memory area, and address information of the data memory area of a receiving end is stored in the control memory area of the transmitting end, and the device includes:
the acquisition module is used for acquiring target data;
the storage module is used for storing the target data to the data memory area;
the obtaining module is further configured to obtain, in a control memory area of the sending end, address information of a target memory block into which the target data is to be written according to the data size of the target data, where the target memory block belongs to the receiving end;
a write-in module, configured to write the target data into the target memory block through a single-side operation according to the address information of the target memory block;
and the receiving module is used for receiving the confirmation message sent by the receiving end through unilateral operation after the target data is processed by the receiving end.
Optionally, the apparatus further comprises:
an adding module, configured to add a sending task of the target data to a first queue of a control memory area of the sending end, where the sending task includes address information of the target memory block;
the write module is configured to:
when the sending task of the target data starts to be processed in the first queue, the target data is written into the target memory block through a single-side operation according to the address information of the target memory block.
Optionally, the obtaining module is further configured to:
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a second queue of a control memory area of the sending end, wherein the second queue is used for storing the address information of unallocated memories; deleting the address information of the target memory block from the second queue;
the adding module is further configured to:
after the completion of the processing of the sending task of the target data is detected, deleting the sending task of the target data in the first queue, and adding a waiting task corresponding to the target data to a third queue of a control memory area of the sending end, wherein the third queue is used for storing the sent sending task;
and after receiving the confirmation message, restoring the address information of the target memory block to the second queue.
Optionally, the adding module is further configured to:
after receiving the acknowledgment message, if the adjacent memory block of the target memory block exists in the third queue and the adjacent memory block corresponds to the acknowledgment message, merging the target memory block and the adjacent memory block, and restoring address information of the merged memory block to the second queue.
Optionally, the adding module is further configured to:
determining a memory grade to which the merged memory block belongs in the third queue based on the capacity of the merged memory block;
and updating the address information of the merged memory block to an address information area corresponding to the memory rank in the third queue.
Optionally, the adding module is further configured to:
and if the merging period is reached or the memory space of the second queue is insufficient, restoring the address information of the merged memory block to the second queue.
In a fourth aspect, a device for transmitting data is provided, which is applied to a receiving end, where a memory area of the receiving end includes a data memory area and a control memory area, and the device includes:
the processing module is used for processing the target data after the target data written in the target memory block by the sending end through the unilateral operation is determined;
and a sending module, configured to send, to the sending end, a confirmation message of the target memory block through a single-side operation after the target data is processed.
Optionally, the apparatus further comprises:
an adding module, configured to add a task record of the target memory block to a fourth queue of a control memory area of the receiving end when data is written in the target memory block;
the processing module is configured to:
after the data writing of the target memory block is completed, deleting the task record in the fourth queue, and adding the task record in a fifth queue of a control memory area of the receiving end;
when the target data is detected to be processed completely, deleting task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of the receiving end;
the sending module is configured to:
after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
In a fifth aspect, a system for transmitting data is provided, where the system includes a sending end and a receiving end, where:
the transmitting end, as described in the third aspect above; the receiving end is the receiving end according to the fourth aspect.
In a sixth aspect, a computer-readable storage medium is provided, in which a computer program is stored, and the computer program, when executed by a processor, implements the method for transmitting data according to the first aspect.
In a seventh aspect, a computer-readable storage medium is provided, in which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method for transmitting data according to the second aspect.
In an eighth aspect, a sending end is provided, where the sending end includes a processor and a memory, where the memory is used to store a computer program; the processor is configured to execute the program stored in the memory, and implement the method for transmitting data according to the first aspect.
In a ninth aspect, a receiving end is provided, which comprises a processor and a memory, wherein the memory is used for storing a computer program; the processor is configured to execute the program stored in the memory, and implement the method for transmitting data according to the first aspect.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least comprise:
in the embodiment of the present disclosure, a memory area of a sending end includes a data memory area and a control memory area, address information of the data memory area of a receiving end is stored in the control memory area of the sending end, when sending data, target data is obtained and stored in the data memory area, according to a data amount of the target data, address information of a target memory block into which the target data is to be written is obtained in the control memory area of the sending end, where the target memory block belongs to the receiving end, according to the address information of the target memory block, the target data is written into the target memory block through a single-sided operation, and a confirmation message sent by the receiving end through the single-sided operation after the receiving end has processed the target data is received. Therefore, the transmitting end can transmit data only through unilateral operation without using bilateral operation, and transmission delay is low, so that transmission performance can be improved.
Drawings
Fig. 1 is a memory structure provided in an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for transmitting data according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a memory structure provided in an embodiment of the present disclosure;
fig. 4 is a flowchart of a method for transmitting data according to an embodiment of the disclosure;
FIG. 5 is a diagram illustrating a structure of a queue according to an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating a structure of a queue according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a method for transmitting data according to an embodiment of the disclosure;
fig. 8 is a flowchart illustrating a method for transmitting data according to an embodiment of the disclosure;
fig. 9 is a schematic flow chart of data transmission provided by the embodiment of the present disclosure;
fig. 10 is a schematic flow chart of data transmission provided by the embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of an apparatus for transmitting data according to an embodiment of the present disclosure;
fig. 15 is a schematic structural diagram of a transmitting end according to an embodiment of the present disclosure;
fig. 16 is a schematic structural diagram of a receiving end according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
For better understanding of the disclosed embodiments, RDMA single-sided WRITE (WRITE) operations in the related art are first introduced:
RDMA one-sided WRITE operation (WRITE): RDMA WRITE, as shown in fig. 1, a single-sided memory area is provided in each of a sending end and a receiving end, and each of the sending end and the receiving end is provided with three queues, namely a sending queue, a receiving queue and a completion queue, and the sending end and the receiving end both correspond to a HCA (Host Channel Adapter).
In the related art, the RDMA WRITE operation data transmission process can be divided into 3 steps:
(1) sending the related information (authority and address) of the memory address corresponding to the receiving end to the sending end in an RDMA send (bilateral operation) form;
(2) the sending end writes data into the receiving end in RDMA WRITE mode by using the relevant information of the memory address corresponding to the receiving end;
(3) the receiving end SENDs an acknowledgement message in RDMA SEND form after processing the data.
As shown in fig. 2, the detailed process is as follows:
step S1: starting a process;
step S2: initializing and registering a memory for connection;
step S3: initializing connection;
step S4: memory address and authority to operate using SEND/RECV (SEND/receive) transfer RDMA WRITE;
step S5: using RDMA WRITE operation to write data into the memory address obtained in last step;
step S6: transmitting an acknowledgement message using a SEND/RECV operation;
step S7: the transmission is ended.
Thus, as can be seen from the above description, in the related art, when data transmission is performed, two memory modes, namely, a bilateral operation mode and a unilateral operation mode, are used, which is not beneficial to management.
The embodiment of the disclosure provides a method for transmitting data, and an execution main body of the method can be a sending end and a receiving end. The sending end may be a terminal or a server, and the receiving end may also be a terminal or a server, which is not limited in the embodiments of the present disclosure.
The sending end may be provided with a processor, a memory, and a transceiver, where the processor may be configured to process transmission data, the memory may be configured to store data required and generated during data transmission, and the transceiver may be configured to receive and send data, such as receiving an acknowledgement message from the receiving end, and sending data to the receiving end.
The receiving end may be provided with a processor, a memory, and a transceiver, where the processor may be configured to process transmission data, the memory may be configured to store data required and generated in the process of transmitting data, and the transceiver may be configured to receive and transmit data, such as data sent by the sending end, and send an acknowledgement message to the sending end.
The embodiment of the present disclosure provides a method for transmitting data, where the method may be applied to a transmitting end, and as shown in fig. 3, provides a memory model of RDMA WRITE operations related to the embodiment of the present disclosure:
the memory operated by the sender RDMA WRITE may be divided into two continuous memory areas, namely, a control memory area and a data memory area, where the data memory area is used to store data to be transmitted when performing unilateral operation, and in practical applications, the data memory area may be split and merged according to a certain rule according to a use condition, and the control memory area is a memory area used to control data transmission.
The memory operated by the receiving end RDMA WRITE may also be divided into two continuous memory areas, namely a control memory area and a data memory area, where the data memory area is used to store data transmitted during unilateral operation, and in practical applications, the data memory area may be split and merged according to a certain rule according to a use condition, and the control memory area is a memory area used to control data transmission.
As shown in fig. 4, the execution flow of the method corresponding to the memory model shown in fig. 3 can be as follows
In implementation, after the sending end and the receiving end come on line, the sending end and the receiving end first need to initialize memories, the process may be a memory area for registering a response in a local HCA, the memory area includes a data memory area and a Control memory area, then the sending end and the receiving end connect, the connection may be a TCP (Transmission Control Protocol)/IP (Internet Protocol, interconnection Protocol between networks) connection, then the receiving end synchronizes address information (which may include addresses and permissions of the memory areas) of its own data memory area to the sending end, the process may be transmitted through the TCP/IP connection, or may be synchronized through SEND/RECV. Thus, the sending end can obtain the address information of the data memory area of the receiving end, and the sending end can store the address information in the control memory area.
The subsequent sending end needs to send data to the receiving end, and the sending end can acquire the data to be sent (namely target data) and store the data to the own data memory area. For example, the sending end is a user terminal, the receiving end is a cloud storage server, the sending end has data to send to the cloud storage server for storage, and the data is target data.
In implementation, the sending end may use the data size of the target data, and apply for address information of the memory, into which the target data is written at the receiving end, in the control memory area of the sending end, where the address information may be referred to as address information of the target memory block, and the data size that can be written by the target memory block is greater than or equal to the data size of the target data.
In implementation, after the sending end acquires the address information of the target memory block, the sending end has the address information of the memory block to be written, so that the HCA can write the target data into the target memory block by using a single-side operation. After detecting the write-in, the receiving end may process the target data, for example, store the target data to a disk, and when it is determined that the processing is completed, may send a confirmation message to the sending end through a single-sided operation.
In implementation, after receiving the acknowledgment message sent by the receiving end, the sending end may determine that the sending of the target data is completed, may delete the target data from the data memory area, and may arrange the target memory block to other data.
Optionally, in step 403, in order to more conveniently manage the sending data, a plurality of queues may be provided, and the process may be as follows:
and adding a sending task of the target data to a first queue of a control memory area of a sending end, wherein the sending task comprises address information of a target memory block, and when the sending task of the target data starts to be processed in the first queue, writing the target data into the target memory block through unilateral operation according to the address information of the target memory block.
In an implementation, the control memory area of the sending end maintains three queues, namely a first queue (which may also be referred to as a work queue), a second queue (which may also be referred to as an idle queue), and a third queue (which may also be referred to as a wait queue), where the first queue is used to store a sending task of data to be sent, the second queue is used to store address information of a memory into which data is not written in the receiving end, and the third queue is used to store a sending task of data that has been sent to the receiving end.
After applying for the target memory block to the own control memory area, the sending end may add a sending task of the target data to the first queue, where the sending task may include address information of the target memory block, and in addition, if the first queues are queues of sending tasks, the task types (including a sending type and a receiving type) may not be stored, and if the first queues are not queues of sending tasks, the sending end also includes a receiving task, that is, the sending task of the target data includes the address information of the target memory block and the task type (i.e., the sending type).
When the tasks for sending the target data are sequentially queued in the first queue, the address information and the task type of the target memory block may be read in the first queue, and then the target data may be written into the target memory block of the receiving end through a single-sided operation. Thus, the target data can be written into the target memory block of the receiving end.
Optionally, for convenience of management, the address information of the data memory area of the receiving end is also stored in the control memory area of the sending end, and the processing may be as follows:
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a second queue of a control memory area of a sending end, wherein the second queue is used for storing the address information of unallocated memories; deleting the address information of the target memory block from the second queue; after the completion of the processing of the sending task of the target data is detected, deleting the sending task of the target data in the first queue, and adding a waiting task corresponding to the target data to a third queue of a control memory area of the sending end, wherein the third queue is used for the sending task which is completed to be sent; and after receiving the confirmation message, restoring the address information of the target memory block to the second queue.
In implementation, the sending end may obtain, in the second queue, address information of the memory block corresponding to the data size of the target data, that is, address information of the target memory block, and then delete, in the second queue, the address information of the target memory block.
When the sending end detects that the sending of the target data is completed, a sending task of the target data can be deleted from the first queue, then a waiting task corresponding to the target data is added to a third queue of a control memory area of the sending end, after receiving a confirmation message of a corresponding target memory block sent by the receiving end, the sending end can add address information of the target memory block to the second queue, and delete the waiting task corresponding to the target data from the third queue. In this way, subsequent other data may use the target memory block.
Optionally, as shown in fig. 5, the address information of the memory blocks in the first queue, the second queue, and the third queue is also stored according to the memory rank, and different memory ranks correspond to the memory blocks in the memory rank, for example, the memory rank is 40k, and the size of the memory block with the memory rank of 40k is 40 k. The arrows in the second queue and the third queue in fig. 5 indicate that a memory block with a memory rank of 20k can be moved from the third queue to a memory block set with a memory rank of 20k in the second queue.
Optionally, in order to reduce memory fragments at the receiving end, in the embodiment of the present disclosure, a processing process of merging memory blocks is further provided:
after receiving the confirmation message, if the adjacent memory block of the target memory block exists in the third queue and the adjacent memory block corresponds to the confirmation message, merging the target memory block and the adjacent memory block, and recovering the address information of the merged memory block to the second queue.
In implementation, after receiving the acknowledgment message of the target memory block, it may be detected whether the neighboring memory blocks of the target memory block (the neighboring memory blocks refer to memory blocks neighboring on an address indicated by the address information) exist in the third queue, and if the neighboring memory blocks of the target memory block exist, it may be determined whether the memory blocks already correspond to acknowledgment messages sent by the receiving end, and if all the memory blocks correspond to acknowledgment messages sent by the receiving end, the memory blocks and the target memory block may be merged, and the address information of the merged memory blocks is recovered to the second queue. For example, the address information of the target memory block 1 is 1 to 10, the address information of the memory block 2 is 11 to 20, it can be seen that 10 is adjacent to 11, the target memory block 1 and the memory block 2 are obtained by dividing the same memory block, and both the target memory block 1 and the memory block 2 have an acknowledgement message sent by a receiving end, and the target memory block 1 and the memory block 2 may be merged to obtain a memory block 0, where the corresponding address information is 1 to 20. For another example, the address information of the target memory block 1 in the third queue is 1 to 10, the address information of the memory block 3 is 45 to 60, it can be seen that 45 is not adjacent to 10, and the target memory block 1 and the memory block 3 are not obtained by dividing the same memory block, so that the target memory block 1 and the memory block 3 cannot be merged.
Therefore, small memory blocks can be combined into a large memory block in time, and the existing memory fragments are fewer.
It should be noted that, since the merging of the memory blocks is a process that consumes processing resources comparatively, the memory blocks are merged in the third queue, but not in the second queue, and the application of the memory blocks during data transmission is not affected.
Optionally, for more convenient merging, the address information of the memory blocks belonging to the same memory rank may be stored together, and the processing may be as follows:
and determining the memory grade to which the merged memory block belongs in the third queue based on the capacity of the merged memory block, and updating the address information of the merged memory block into an address information list corresponding to the memory grade in the third queue.
In an implementation, the memory rank is used to reflect the data size, i.e., capacity, of the data that the memory block can store. After the merged memory block is obtained, the capacities of the memory blocks before merging may be added to obtain the capacity of the merged memory block, then the rank to which the capacity belongs is determined, and then the address information of the merged memory block is updated to the address information area corresponding to the memory rank in the third queue. As shown in fig. 6, there are currently four memory ranks in the third queue, which are 160k, 80k, 40k, and 20k, respectively, where there are used memory blocks and idle memory blocks in the 20k memory rank, and the idle memory blocks indicate that the acknowledgement message of the receiving end has been received, and may be merged, and two memory blocks of 20k may be merged to 40k, and two memory blocks of 40k are merged to 80k, and two memory blocks of 80k are merged to a memory block of 160 k.
Optionally, the foregoing recovering the address information of the target memory block to the second queue may further satisfy the following condition:
and if the merging period is reached or the memory space of the second queue is insufficient, restoring the address information of the merged memory block to the second queue.
The merging period may be preset and stored to the sending end, for example, 10 minutes.
In implementation, after the memory blocks are merged to obtain the memory blocks, whether a merging period is reached may be determined, and if the merging period is reached, the address information of the memory blocks obtained by merging may be restored to the second queue.
Or after the memory blocks are obtained by merging, it may be determined whether the memory space of the third queue is smaller than the data size of the data to be currently sent, and if so, it may be determined that the memory space is insufficient, and the address information of the memory blocks obtained by merging may be restored to the second queue.
In addition, as shown in fig. 7, in order to more clearly express data transmission between the sending end and the receiving end, it can be seen that the target data transmitted by the sending end is directly written into the data memory area of the receiving end, and the acknowledgement message returned by the receiving end is returned to the control memory area of the sending end.
In addition, in the embodiment of the present disclosure, a process of processing RDMA WRITE operation by the receiving end is further provided, as shown in fig. 8, the flow may be as follows:
In an implementation, after the sending end writes the target data into the target memory block of the receiving end, the receiving end may obtain the target data from the target memory block, and then process the target data, for example, perform a storage process on the target data.
In implementation, after the receiving end completes processing of the target data, the receiving end may send a confirmation message of the target memory block to the sending end through a single-side operation, so that the sending end may continue to use the target memory block after receiving the confirmation message.
Optionally, for better management, the receiving end may perform the following processing:
when the target memory block writes data, adding a task record of the target memory block in a fourth queue of a control memory area of a receiving end; after the data writing of the target memory block is completed, deleting the task records in the fourth queue, and adding the task records in a fifth queue of a control memory area of the receiving end; when the target data is detected to be processed completely, deleting the task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of a receiving end; after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
The first value and the second value may be preset and stored in the receiving end, for example, the first value may be 10, the second value may be 20k, and the like.
In an implementation, the receiving end manages the receiving tasks according to the queues, and the control memory area of the receiving end maintains three queues, namely a fourth queue (which may also be referred to as a work queue), a fifth queue (which may also be referred to as a wait queue), and a sixth queue (which may also be referred to as an idle queue), where the fourth queue is used to store the receiving tasks that are to receive data, the fifth queue is used to store the tasks that have written data into the memory and are waiting for processing, and the sixth queue is used to store the tasks that have been processed.
When the receiving end receives the target data sent by the sending end, that is, when the data is written in the target memory block, the task record of the target memory block is added to the fourth queue of the control memory area of the receiving end, and the data in the target memory block is identified to be received. After the data in the target memory block is written, the receiving end may delete the task record in the fourth queue, and then in a fifth queue of the control memory area of the receiving end, the task record identifies the target data in the target memory block to be processed.
When the target data in the processing target memory block is scheduled, the target data can be processed, after the processing is completed, the task record of the target data can be deleted in the fifth queue, and then the receiving end adds the task record in the sixth queue of the control memory area of the receiving end to mark that the task record processing is completed.
The receiving end can determine whether the number of the task records in the sixth queue reaches a first value, if so, can send the acknowledgement messages of all the task records in the sixth queue to the sending end through unilateral operation, and if not, send the acknowledgement messages of all the task records in the sixth queue to the sending end when waiting for reaching the first value. Or the receiving end may determine whether the space occupied by the task records in the sixth queue reaches the second value, if the space occupied by the task records in the sixth queue reaches the second value, the receiving end may send the acknowledgement messages of all the task records in the sixth queue to the sending end through a single-side operation, and if the space occupied by the task records in the sixth queue does not reach the second value, the receiving end may send the acknowledgement messages of all the task records in the sixth queue to the sending end while waiting for reaching the second value. Since the task of the target memory block is recorded in the sixth queue, the target memory block is also transmitted.
In this way, the acknowledgement messages of a plurality of memory blocks can be sent in batch, rather than individually, so that the number of communications is reduced, and the overall transmission delay is also reduced to a certain extent.
In addition, in order to facilitate understanding of the processing processes of the transmitting end and the receiving end, a schematic diagram as shown in fig. 9 is provided, in fig. 9, the transmitting end and the receiving end respectively perform initialization of a memory and connection, the transmitting end and the receiving end establish connection, the transmitting end and the receiving end respectively and synchronously control a memory area in advance (the process is 1, the transmitting end and the receiving end respectively apply for the memory to the system, 2, the transmitting end and the receiving end register the memory in an RDMA form (at this time, since address information of the other party is not known, the memory area is controlled or two simultaneous situations of SEND/RECV and WRITE are registered, the data memory area is only registered in a WRITE form), 3, the transmitting end and the receiving end respectively acquire information (address and authority) of the two memories after the registration is completed, 4, the transmitting end and the receiving end synchronize the information (by using socket operation or bilateral operation, if the socket operation is used, the control memory area may be only registered in a WRITE form), the transmitting end transmits data to the receiving end through a single-sided operation, and the receiving end transmits a confirmation message to the receiving end through the single-sided operation.
In addition, as shown in fig. 10, in the embodiment of the present disclosure, a schematic processing flow diagram is further provided:
step a1, start;
step A2: starting a process;
step A3: initializing and registering a memory for connection;
step A4: initializing connection, and synchronously controlling a memory area in advance;
step A5: applying for a memory space to a free queue of a control memory area;
step A6: filling a WRITE task into a work queue of a control memory area;
step A7: operating the data memory area of the receiving end according to tasks in a work queue of the control memory area;
step A8: shifting the tasks which are executed and are to be processed by the receiving end into a waiting queue;
step A9: RDMA WRITE is used for operating the synchronous control memory area and starting the background thread processing memory control area;
step A91: synchronizing the control information synchronized by the receiving end to obtain the processed internal memory information of the receiving end;
step A92: merging the memory blocks in the third queue;
step A93: and merging the waiting queues into the second queue according to a preset memory threshold or timing.
In addition, after step a9, it is also possible to check whether there is a task in the first queue, and if so, go to step a5, otherwise, the communication ends.
In the embodiment of the present disclosure, a memory area of a sending end includes a data memory area and a control memory area, address information of the data memory area of a receiving end is stored in the control memory area of the sending end, when sending data, target data is obtained and stored in the data memory area, according to a data amount of the target data, address information of a target memory block into which the target data is to be written is obtained in the control memory area of the sending end, where the target memory block belongs to the receiving end, according to the address information of the target memory block, the target data is written into the target memory block through a single-sided operation, and a confirmation message sent by the receiving end through the single-sided operation after the receiving end has processed the target data is received. Therefore, the transmitting end can transmit data only through unilateral operation without using bilateral operation, and transmission delay is low, so that transmission performance can be improved.
In addition, in the embodiment of the present disclosure, the sending end stores the address information of the data memory area of the receiving end, and the sending end can transmit data of any size not exceeding the capacity of the data memory area at a time, so that the data memory area is more flexibly used.
Based on the same technical concept, an embodiment of the present disclosure further provides a data transmission apparatus, which is applied to a sending end, where a memory area of the sending end includes a data memory area and a control memory area, and address information of the data memory area of a receiving end is stored in the control memory area of the sending end, as shown in fig. 11, the apparatus includes:
an obtaining module 1101, configured to obtain target data;
a storage module 1102, configured to store the target data in the data memory area;
the obtaining module 1101 is further configured to obtain, according to the data size of the target data, address information of a target memory block to which the target data is to be written in a control memory area of the sending end, where the target memory block belongs to the receiving end;
a writing module 1103, configured to write the target data into the target memory block through a single-side operation according to the address information of the target memory block;
a receiving module 1104, configured to receive an acknowledgement message sent by the receiving end through a single-side operation after the receiving end has processed the target data.
Optionally, as shown in fig. 12, the apparatus further includes:
an adding module 1105, configured to add a sending task of the target data to a first queue of a control memory area of the sending end, where the sending task includes address information of the target memory block;
the writing module 1103 is configured to:
when the sending task of the target data starts to be processed in the first queue, the target data is written into the target memory block through a single-side operation according to the address information of the target memory block.
Optionally, the obtaining module 1101 is further configured to:
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a second queue of a control memory area of the sending end, wherein the second queue is used for storing the address information of unallocated memories; deleting the address information of the target memory block from the second queue;
the adding module 1105 is further configured to:
after the completion of the processing of the sending task of the target data is detected, deleting the sending task of the target data in the first queue, and adding a waiting task corresponding to the target data to a third queue of a control memory area of the sending end, wherein the third queue is used for storing the sent sending task;
and after receiving the confirmation message, restoring the address information of the target memory block to the second queue.
Optionally, the adding module 1105 is further configured to:
after receiving the acknowledgment message, if the adjacent memory block of the target memory block exists in the third queue and the adjacent memory block corresponds to the acknowledgment message, merging the target memory block and the adjacent memory block, and restoring address information of the merged memory block to the second queue.
Optionally, the adding module 1105 is further configured to:
determining a memory grade to which the merged memory block belongs in the third queue based on the capacity of the merged memory block;
and updating the address information of the merged memory block to an address information area corresponding to the memory rank in the third queue.
Optionally, the adding module 1105 is further configured to:
and if the merging period is reached or the memory space of the second queue is insufficient, restoring the address information of the merged memory block to the second queue.
Based on the same technical concept, an embodiment of the present disclosure further provides a device for transmitting data, which is applied to a receiving end, where a memory area of the receiving end includes a data memory area and a control memory area, as shown in fig. 13, the device includes:
a processing module 1301, configured to process target data written by a sending end in a target memory block through a single-side operation after determining the target data;
a sending module 1302, configured to send, to the sending end, an acknowledgement message of the target memory block through a single-side operation after the target data is processed.
Optionally, as shown in fig. 14, the apparatus further includes:
an adding module 1303, configured to add a task record of the target memory block to a fourth queue of the control memory area of the receiving end when data is written in the target memory block;
the processing module 1301 is configured to:
after the data writing of the target memory block is completed, deleting the task record in the fourth queue, and adding the task record in a fifth queue of a control memory area of the receiving end;
when the target data is detected to be processed completely, deleting task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of the receiving end;
the sending module 1302, configured to:
after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
In the embodiment of the present disclosure, a memory area of a sending end includes a data memory area and a control memory area, address information of the data memory area of a receiving end is stored in the control memory area of the sending end, when sending data, target data is obtained and stored in the data memory area, according to a data amount of the target data, address information of a target memory block into which the target data is to be written is obtained in the control memory area of the sending end, where the target memory block belongs to the receiving end, according to the address information of the target memory block, the target data is written into the target memory block through a single-sided operation, and a confirmation message sent by the receiving end through the single-sided operation after the receiving end has processed the target data is received. Therefore, the transmitting end can transmit data only through unilateral operation without using bilateral operation, and transmission delay is low, so that transmission performance can be improved.
In the data transmission device provided in the above embodiment, only the division of the functional modules is used for illustration when data is transmitted, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus for transmitting data and the method for transmitting data provided by the above embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiments and are not described herein again.
Fig. 15 is a schematic structural diagram of a sender 1500 according to an embodiment of the present invention, where the sender 1500 may generate relatively large differences due to different configurations or performances, and may include one or more processors (CPUs) 1501 and one or more memories 1502, where the memory 1502 stores at least one instruction, and the at least one instruction is loaded and executed by the processor 1501 to implement the method steps for transmitting data.
Fig. 16 is a schematic structural diagram of a receiving end 1600 according to an embodiment of the present invention, where the receiving end 1600 may generate a relatively large difference due to different configurations or performances, and may include one or more processors (CPUs) 1601 and one or more memories 1602, where the memory 1602 stores at least one instruction, and the at least one instruction is loaded and executed by the processor 1601 to implement the method steps for transmitting data.
In an embodiment of the present disclosure, a system for transmitting data is provided, where the system includes a sending end and a receiving end, where:
the sending terminal is the sending terminal for transmitting data; the receiving end is the receiving end for transmitting data.
In the embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored, and when the computer program is executed by a processor, the method for transmitting data is implemented.
In the embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored, and when the computer program is executed by a processor, the method for transmitting data is implemented.
In an embodiment of the present disclosure, a sending end is provided, where the sending end includes a processor and a memory, where the memory is used to store a computer program; the processor is used for executing the program stored in the memory and realizing the data transmission method.
In an embodiment of the present disclosure, a receiving end is provided, where the receiving end includes a processor and a memory, where the memory is used to store a computer program; the processor is used for executing the program stored in the memory and realizing the data transmission method.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only exemplary of the present disclosure and is not intended to limit the present disclosure, so that any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (12)
1. A method for transmitting data is characterized in that the method is applied to a sending end, a memory area of the sending end comprises a data memory area and a control memory area, and address information of the data memory area of a receiving end is stored in the control memory area of the sending end, and the method comprises the following steps:
acquiring target data and storing the target data in the data memory area;
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a control memory area of the sending end, wherein the target memory block belongs to the receiving end;
writing the target data into the target memory block through unilateral operation according to the address information of the target memory block;
and receiving a confirmation message sent by the receiving end through unilateral operation after the target data is processed by the receiving end.
2. The method of claim 1, further comprising:
adding a sending task of the target data to a first queue of a control memory area of the sending end, wherein the sending task comprises address information of the target memory block;
the writing the target data into the target memory block through a single-side operation according to the address information of the target memory block includes:
when the sending task of the target data starts to be processed in the first queue, the target data is written into the target memory block through a single-side operation according to the address information of the target memory block.
3. The method according to claim 2, wherein the obtaining, according to the data size of the target data, address information of a target memory block into which the target data is to be written in a control memory area of the sending end includes:
according to the data volume of the target data, acquiring address information of a target memory block into which the target data are written in a second queue of a control memory area of the sending end, wherein the second queue is used for storing the address information of unallocated memories; deleting the address information of the target memory block from the second queue;
the method further comprises the following steps:
after the completion of the processing of the sending task of the target data is detected, deleting the sending task of the target data in the first queue, and adding a waiting task corresponding to the target data to a third queue of a control memory area of the sending end, wherein the third queue is used for storing the sent sending task;
and after receiving the confirmation message, restoring the address information of the target memory block to the second queue.
4. The method according to claim 3, wherein the restoring the address information of the target memory block to the second queue after receiving the acknowledgment message includes:
after receiving the acknowledgment message, if the adjacent memory block of the target memory block exists in the third queue and the adjacent memory block corresponds to the acknowledgment message, merging the target memory block and the adjacent memory block, and restoring address information of the merged memory block to the second queue.
5. The method of claim 4, further comprising:
determining a memory grade to which the merged memory block belongs in the third queue based on the capacity of the merged memory block;
and updating the address information of the merged memory block to an address information area corresponding to the memory rank in the third queue.
6. The method according to claim 4, wherein the restoring the address information of the merged memory block to the second queue includes:
and if the merging period is reached or the memory space of the second queue is insufficient, restoring the address information of the merged memory block to the second queue.
7. A method for transmitting data is applied to a receiving end, wherein a memory area of the receiving end comprises a data memory area and a control memory area, and the method comprises the following steps:
processing target data written in a target memory block by a sending end through unilateral operation after determining the target data;
and after the target data is processed, sending a confirmation message of the target memory block to the sending end through unilateral operation.
8. The method of claim 7, further comprising:
when the target memory block writes data, adding a task record of the target memory block in a fourth queue of a control memory area of the receiving end;
the processing the target data comprises:
after the data writing of the target memory block is completed, deleting the task record in the fourth queue, and adding the task record in a fifth queue of a control memory area of the receiving end;
when the target data is detected to be processed completely, deleting task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of the receiving end;
after the target data is processed, sending a confirmation message of the target memory block to the sending end through a unilateral operation, including:
after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
9. A device for transmitting data is characterized in that the device is applied to a sending end, a memory area of the sending end comprises a data memory area and a control memory area, address information of the data memory area of a receiving end is stored in the control memory area of the sending end, and the device comprises:
the acquisition module is used for acquiring target data;
the storage module is used for storing the target data to the data memory area;
the obtaining module is further configured to obtain, in a control memory area of the sending end, address information of a target memory block into which the target data is to be written according to the data size of the target data, where the target memory block belongs to the receiving end;
a write-in module, configured to write the target data into the target memory block through a single-side operation according to the address information of the target memory block;
and the receiving module is used for receiving the confirmation message sent by the receiving end through unilateral operation after the target data is processed by the receiving end.
10. An apparatus for transmitting data, wherein the apparatus is applied to a receiving end, a memory area of the receiving end includes a data memory area and a control memory area, and the apparatus includes:
the processing module is used for processing the target data after the target data written in the target memory block by the sending end through the unilateral operation is determined;
and a sending module, configured to send, to the sending end, a confirmation message of the target memory block through a single-side operation after the target data is processed.
11. The apparatus of claim 10, further comprising:
an adding module, configured to add a task record of the target memory block to a fourth queue of a control memory area of the receiving end when data is written in the target memory block;
the processing module is configured to:
after the data writing of the target memory block is completed, deleting the task record in the fourth queue, and adding the task record in a fifth queue of a control memory area of the receiving end;
when the target data is detected to be processed completely, deleting task records of the target data in the fifth queue, and adding the task records in a sixth queue of a control memory area of the receiving end;
the sending module is configured to:
after the target data is processed, if the number of the task records in the sixth queue reaches a first value or the space occupied by the task records in the sixth queue reaches a second value, sending confirmation messages of all the task records in the sixth queue to the sending end through unilateral operation.
12. A system for transmitting data, the system comprising a transmitting end and a receiving end, wherein:
the transmitter, the transmitter according to claim 9;
the receiving end, the receiving end of claim 15.
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