CN118227047A

CN118227047A - Read-write system, method and storage medium of DDR controller based on FPGA

Info

Publication number: CN118227047A
Application number: CN202410299550.1A
Authority: CN
Inventors: 张泽; 杨晨飞; 曹桂平; 董宁
Original assignee: Hefei Eko Photoelectric Technology Co ltd
Current assignee: Hefei Eko Photoelectric Technology Co ltd
Priority date: 2024-03-15
Filing date: 2024-03-15
Publication date: 2024-06-21

Abstract

The invention provides a read-write system, a read-write method and a storage medium of a DDR controller based on an FPGA. The system comprises: DDR controller and at least one DDR memory. The DDR controller is used for judging whether the use environment of any clock edge in the clock signal meets the transmission condition, if so, transmitting the DDR instruction in the current state, and then updating the DDR instruction again; otherwise, only updating the DDR instruction in the current state; based on sending the DDR instruction of the current state, the DDR controller performs a read/write operation. The DDR controller is realized based on the FPGA, the write/read processing module is arranged in the FPGA to judge the use signal of the clock edge signal, and a solution of high-efficiency read-write operation is provided, so that the problem that the realization of high-efficiency read-write in the prior art depends on the performance of the package IP of the FPGA is solved. The read-write method of the DDR controller is realized based on the FPGA, so that the read-write method can process and judge in real time, and the efficient and non-missing read-write operation is ensured.

Description

Read-write system, method and storage medium of DDR controller based on FPGA

Technical Field

The invention relates to the technical field of data transmission, in particular to a read-write system, a read-write method and a storage medium of a DDR controller based on an FPGA.

Background

Ddr=double Data Rate Double Rate, DDR sdram=double Rate synchronous dynamic random access memory, commonly referred to as DDR. DDR is a common buffer device, which has the advantage of large capacity, but is not as large as a hard disk, but is enough to hold the buffer data required by various computing devices (CPU/SOC/ASIC, etc.).

Part of the FPGA supports different command burst lengths (burst, burst transmission length, maximum continuous transmission data quantity each time) in the encapsulated DDR3 Controller IP, and can be continuously read or continuously written under specific conditions (i.e. idealized application scenes), for example, when the command burst is maximum, and the highest read-write transmission efficiency is possessed at the moment. However, for complex non-idealized scenarios, such as a read-write rotation, or a transmission of different data volumes across memory address boundaries, burst=1 is usually used at this time to ensure the correctness of reading and writing, but the read-write efficiency is greatly reduced, and efficient read-write operation cannot be performed.

The method and device for reading and writing commands provided by China patent CN 110910921A receive bus read/write commands. The patent adds a certain buffer area and cuts, and the control logic performs merging processing on the read/write commands of the bus interface, so that the DDR SRAM port executes the merged bus read/write commands to achieve the aim of improving the efficiency. For multiple small data volume accesses, a bus read/write command can be sent in a combined mode, and the efficiency is improved remarkably. The patent solves the technical problems of small burst length and low read-write efficiency, but the burst setting length is small, so that the patent is only one processing condition in practical application, and cannot provide a solution for other complex scenes.

Chinese patent CN 116841458A provides a memory read-write control method, system, terminal and storage medium. The method can buffer the requests of the thread and related data, and simultaneously forwards the buffered requests based on two factors of buffer time and data quantity, so as to solve the problem that a single thread occupies too long DDR control authority or the DDR frequently switches read-write instructions to cause data confusion in the method of setting the quantity threshold buffer requests in the DDR controller. The patent is set based on the cache time and the data volume, provides a corresponding solution for high-efficiency reading and writing of related application scenes, but does not provide a corresponding reading and writing method for other application scenes such as transmission across memory address boundaries.

Chinese patent CN 117093157B proposes a DDR high-speed read/write method and system for unidirectional optical transmission. According to the data writing method and device, correct data writing or reading operation is carried out according to the state of the DDR buffer area, the integrity and the correctness of data are ensured, meanwhile, the DDR read buffer area and the DDR write buffer area are isolated, and meanwhile, the parallelism of the reading operation and the writing operation is improved. Unlike the technical problems solved by the present solution.

Disclosure of Invention

The invention provides a reading and writing system, a reading and writing method and a storage medium of a DDR controller based on an FPGA, which can at least solve one of the technical problems.

In order to achieve the above object, the present invention provides a read-write system of a DDR controller based on an FPGA, including:

the DDR controller judges whether the use environment of any clock edge in the clock signal meets the transmission condition, if so, the DDR controller transmits the DDR instruction in the current state, and then updates the DDR instruction again; otherwise, only updating the DDR instruction in the current state;

based on sending the DDR command of the current state, the DDR controller executes a read operation/write operation;

wherein, the service environment includes: data existence state, data quantity, read instruction/write instruction existence state, instruction information state and instruction receiving time;

the sending situation is that the quantity of data contained in an instruction in any current clock edge is equal to the maximum command burst length and/or the read instruction/write instruction information state contained in the instruction is abnormal and/or the instruction is in a overtime receiving state;

And the DDR memory is connected with the DDR controller and receives and caches the write-in data.

Further, the read instruction/write instruction information state contained in the instruction has an exception, including: in the state where the read instruction/write instruction exists, at least one of an instruction change, an address discontinuity, and an address crossing boundary occurs.

Further, the instruction change includes: and when the read instruction/write instruction exists, the continuous read instruction is switched to the write instruction or the continuous write instruction is switched to the read instruction, the DDR instruction in the current state is sent, and the DDR instruction is updated to the write instruction/read instruction after the DDR instruction is sent, so that the switched write operation/read operation can be conveniently executed.

Further, the instruction is in a timeout receiving state, including: the current instruction is in a non-empty state, the arrival time of the next instruction exceeds the set signal receiving time, and the next instruction is in a overtime receiving state.

Further, the current state DDR instruction includes: and controlling a read instruction/write instruction, a read address/write address, a burst length and a read/write valid.

Further, the data amount includes: the number of read valid/write valid counts contained in the instruction.

On the other hand, the invention also provides a reading and writing method of the DDR controller based on the FPGA, which comprises the following steps:

judging whether the use environment of any clock edge in the clock signal meets the transmission condition, if so, transmitting the DDR instruction in the current state, and then updating the DDR instruction again; otherwise, only updating the DDR instruction in the current state;

the sending condition is that the quantity of data contained in the instruction in any current clock edge is equal to the maximum command burst length and/or the read instruction/write instruction information state contained in the instruction is abnormal and/or the instruction is in a overtime receiving state.

In yet another aspect, the present invention also proposes a computer readable storage medium storing a computer program which, when executed by a processor, implements a method for reading and writing a FPGA-based DDR controller as described above.

The beneficial effects of the invention are as follows:

according to the actual read-write operation complexity, the DDR instruction is selected to be updated by judging the use environment of the clock edge, or the DDR instruction (state 1) is sent and the DDR instruction (state 2) is updated, so that the corresponding read-write strategy is provided corresponding to the current use environment, and the read-write operation is executed with the highest efficiency.

The DDR controller is realized based on the FPGA, the write/read processing module is arranged in the FPGA to judge the use signal of the clock edge signal, and a solution of high-efficiency read-write operation is provided, so that the problem that the realization of high-efficiency read-write in the prior art depends on the performance of the package IP of the FPGA is solved.

The read-write method of the DDR controller is realized based on the FPGA, so that the read-write method can process and judge in real time, and the efficient and non-missing read-write operation is ensured.

Drawings

FIG. 1 is a schematic diagram of a read-write system in embodiment 1 of the present invention;

FIG. 2 is a schematic diagram of the W/R Process Module of FIG. 1;

FIG. 3 is a schematic diagram of a read-write system in embodiment 2 of the present invention;

FIG. 4 is a schematic diagram of a read-write system in embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of a judgment flow of the use environment of any clock edge in the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.

As shown in fig. 1, the present invention proposes a read-write system of a DDR controller based on an FPGA, the system comprising: DDR controller and at least one DDR memory.

And the DDR memory is connected with the DDR controller and receives the writing data.

Example 1

In order to facilitate the explanation of the processing procedure of the clock signal in the present system, a DDR memory is provided in the present embodiment. DDR memory includes SDRAM memory of various types such as DDRx. In this embodiment, the DDR memory is DDR3.

In this embodiment, the DDR controller cannot perform read and write operations simultaneously, that is, cannot handle the case of simultaneous read and write inputs, and cannot perform read and write operations simultaneously. In this embodiment, any clock edge of each clock signal may not have both read and write operations at the same time, that is, the DDR controller performs a read operation or a write operation on a single processing object, and the processing unit is a clock signal. In this embodiment, the DDR controller is implemented based on an FPGA.

In this embodiment, the instruction is fetched from any clock edge of the clock signal. The instruction includes a read instruction or a write instruction. The write instruction includes write data write_data, write effective write_valid, and write address write_addr. The read instruction includes a read valid_valid and a read address read_addr. In the application, if a read instruction is acquired, the data refers to the read valid; and acquiring a write instruction, and writing the data into a valid write_valid. Any one of the clock edges of the clock signal, including the rising edge and the falling edge, may be set as one or both, and the present application is not particularly limited.

As shown in fig. 1, based on the read/write settings, the DDR controller in this embodiment specifically includes:

Write Operation module Write Operation for enabling writing. If a write instruction exists in the current clock edge, a write operation module is entered, and write operation is executed.

And the Read Operation module is used for enabling the reading. If a read instruction exists in the current clock edge, a read operation module is entered, and a read operation is executed.

As shown in fig. 2, one end of a write/read processing Module (W/R Process Module) is connected to the write operation Module and the read operation Module, and the other end is connected to the DDR controller IP core through a prescribed port.

A write/read processing Module (W/R Process Module) judges whether the use environment of any clock edge in the clock signal meets the transmission condition, if so, the DDR instruction in the current state is transmitted, and then the DDR instruction is updated again; otherwise, only the DDR instruction of the current state is updated. Before sending the DDR instruction in the current state, the module stores the instruction, and then sends the instruction from the instruction cache module to the DDR controller IP core.

The write/read processing Module (W/R Process Module) includes a write cache Module WRITE DATA FIFO and a read data FIFO.

The write buffer module WRITE DATA FIFO is used for storing write data write_data and write valid_valid, and outputting write data write_ddr. Preferably, the write buffer module may be an asynchronous buffer async FIFO or a synchronous buffer sync FIFO.

The read cache module is used for storing read data data_read_DDR and outputting the read data read_data. Preferably, the read buffer module may be an async FIFO or a sync FIFO.

The write/read processing Module (W/R Process Module) also includes a processing Module (Process Module) and an instruction cache Module (IP Command FIFO).

A processing Module (Process Module) for judging whether the use environment of any clock edge in the clock signal meets the transmission condition, if so, transmitting the DDR instruction in the current state, and then updating the DDR instruction again; otherwise, only the DDR instruction of the current state is updated. The module sends the DDR instruction in the current state to the instruction cache module.

If a write instruction exists in the clock edge, the write effective write_valid and the write address write_addr enter a processing Module (Process Module) to carry out judgment processing.

If a read instruction exists in the clock edge, the read valid_valid and the read address read_addr enter a processing Module (Process Module) to perform judgment processing.

Wherein, the service environment includes: data existence state, data quantity, read instruction/write instruction existence state, instruction information state, instruction receiving time.

The method for judging the use environment of any clock edge in the current clock signal specifically comprises the following steps:

A first judging module: and judging the existence state of the data.

If a write command exists in the clock edge, whether the count for writing is valid is zero is judged. If a read command exists in the clock edge, whether the count for reading is valid is zero is judged.

If the count is zero, updating the DDR instruction; otherwise, the DDR instruction is updated or the next judging module is entered.

And a second judging module: and judging the data quantity. The number of counts that read/write is valid, i.e., the size relationship of burst length to the maximum one-time command burst length, is determined.

If the current DDR command is equal to the maximum primary command burst length, sending the DDR command in the current state to the command cache module, and updating the DDR command; otherwise, the DDR instruction is updated or the next judging module is entered.

The maximum primary command burst length is set according to the selected DDR memory and the current application scene, and the invention is not particularly limited.

And a third judging module: and judging whether the instruction exists, namely whether the read instruction/write instruction exists in the current clock edge.

If the read instruction/write instruction exists, whether the instruction content is changed, whether the address is discontinuous or not, whether the address crosses the boundary or not is further judged, and if the read instruction/write instruction information state is abnormal, namely at least one item is yes, a DDR instruction is sent to the instruction cache module; updating the DDR instruction based on the content of the read instruction/write instruction; if not, only the DDR instruction is updated.

If there is no read/write command, the timeout count is updated or the next decision block is entered. The timeout count is to record the number of clock edges without read/write instructions in the current clock signal and calculate the timeout time according to the number.

Wherein, the read instruction/write instruction information state contained in the instruction has abnormality, comprising: in the state where the read instruction/write instruction exists, at least one of an instruction change, an address discontinuity, and an address crossing boundary occurs.

The instruction content changes, which indicates that the currently received instruction is inconsistent with the last instruction, including switching from a continuous read instruction to a write instruction or from a continuous write instruction to a read instruction. The discontinuous addresses represent two consecutive read or write addresses, and the addresses are not accumulated according to the IP rule. Addresses cross boundaries, representing read or write addresses twice in succession, across page boundaries or other boundaries of the DDR memory to cause the DDR memory to invalidate stored data.

A fourth judging module: and judging whether the read instruction/write instruction is in a timeout receiving state.

If yes, sending the DDR instruction to an instruction cache module, and updating the DDR instruction; otherwise, the DDR instruction is updated or the next judging module is entered.

Wherein the instruction is in a timeout receiving state, comprising: the current instruction is in a non-empty state, the arrival time of the next instruction exceeds the set signal receiving time, and the next instruction is in a overtime receiving state.

The set signal receiving time is set according to the current hardware condition and the use scenario, and the invention is not limited in particular.

The order of the judging modules can be adjusted at will, the invention does not limit the front-to-back order of the judging modules, but any reading instruction/writing instruction must complete all the judging processing procedures in order to ensure that the judgment is not missed.

Any judging module relates to updating the selection content of the instruction cache module or entering the next judging module, if the current judging module is a final judging module, updating the DDR instruction and ending the judging process; and otherwise, entering a next judging module, and continuing judging processing. Furthermore, the determination modules described in the present invention are only exemplary, and do not represent all determination contents.

If the judging sequence of the third judging module is behind the first judging module and the second judging module, the following steps are needed:

in the first judging module, in order to ensure that the DDR controller executes high-efficiency reading and writing, before updating the DDR instruction, whether a reading instruction/writing instruction exists or not is also required to be judged.

In the second judging module, in order to ensure that the DDR controller executes high-efficiency reading and writing, before updating the DDR instruction, whether a reading instruction/writing instruction exists or not is also required to be judged.

Based on the judging process, the DDR instruction in any state is updated in real time, so that the reading operation/writing operation can be efficiently executed.

If the judging sequence of the third judging module is before the first judging module, after the judgment of the first judging module is finished, if the DDR instruction needs to be updated, the judgment of whether the read instruction/write instruction exists or not is not needed to be repeated. If the judging sequence of the third judging module is before the second judging module, after the judgment of the second judging module is finished, if the DDR instruction needs to be updated, whether the read instruction/write instruction exists or not does not need to be judged repeatedly.

The DDR instruction is an instruction set written into an IP core of the DDR controller and is used for controlling the DDR controller to execute read-write operation, and the instruction set comprises a read instruction/write instruction, a read address/write address, a burst length and a read valid/write valid. The control read command/write command is a control command for enabling the read operation/write operation based on the obtained read command/write command. The read address/write address is the read address/write address obtained based on the above-described determination result. burst length, based on the above judgment result, the obtained read valid/write valid burst length. And reading the validity/writing the validity, and based on the judging result, obtaining the reading the validity/writing the validity.

The instruction cache module is used for storing the DDR instruction in the current state sent by the processing module and outputting the instruction to the DDR controller IP core, so that the DDR controller IP core can mobilize the read-write width of the DDR memory with the highest efficiency, and high-efficiency read-write is realized.

In this embodiment, the instruction cache module is an IP Command FIFO. Preferably, it may be an async FIFO or a sync FIFO.

The IP Command FIFO is connected to the port of the DDR controller IP core.

When the DDR memory is in an idle state, the IP Command FIFO writes a plurality of stored DDR instructions into the port; and outputting a plurality of DDR instructions to the DDR memory through the DDR controller IP core.

Based on the above determination function of the W/R Process Module, the present embodiment provides the satisfied transmission situation in the determination of the use environment of any clock edge, so as to illustrate the use Process of the W/R Process Module:

The sending condition is that the quantity of data contained in the instruction in any current clock edge is equal to the maximum command burst length and/or the read instruction/write instruction information state contained in the instruction has an abnormality and/or the instruction is in a overtime receiving state.

1) And continuous reading/writing. The normal use environment of a read/write instruction is a single write operation or a single read operation.

After judging the use environment of any clock edge, the reading effective/writing effective count number in the current reading instruction/writing instruction, and the maximum command burst number is full, the Process Module sends a DDR instruction in the current state to the instruction cache Module, and the sent DDR instruction comprises the current starting address, burst length, reading instruction/writing instruction and other signals, and then updates the DDR instruction so as to be convenient for receiving the next clock signal.

2) And continuous reading/writing. The normal use environment of a read/write instruction is a single write operation or a single read operation.

After the use environment of any clock edge is judged, in a third judging Module, address discontinuity occurs, or even if the addresses are continuous but address page crossing boundaries occur, a Process Module sends a DDR instruction in the current state to an instruction cache Module, the sent DDR instruction contains address discontinuity, or all information (signals such as the current starting address, burst length, read or write instructions and the like) before the addresses cross the boundaries, and then the DDR instruction is updated so as to be convenient for receiving the next clock signal.

3) Switching from a continuous read instruction to a write instruction. When the read instruction is continuously acquired and the read operation is executed, the write instruction is acquired at the next clock edge, and after the Process Module is judged, the write operation can be performed.

The Process Module sends a DDR instruction in the current state to the instruction cache Module, the DDR instruction in the current state comprises signals of a current starting address, a burst length, a read instruction and the like, and then the DDR instruction is updated into a write instruction, so that the write operation is conveniently executed.

4) Switching from a continuous write instruction to a read instruction. When the write instruction is continuously acquired and the write operation is executed, the next clock edge acquires the read instruction, and after the Process Module judgment, the read operation can be performed.

The Process Module sends a DDR instruction in the current state to the instruction cache Module, the DDR instruction in the current state comprises signals such as a current starting address, burst length, a write instruction and the like, and then the DDR instruction is updated into a read instruction, so that the read operation is conveniently executed.

5) In the state that the current read instruction/write instruction is not empty, the arrival time of the next instruction exceeds the set signal receiving time, namely the next instruction is in a receiving overtime state.

And sending a DDR instruction in the current state as an efficient instruction set to store. The transmitted DDR instruction comprises signals such as a current starting address, burst length, a read instruction/write instruction and the like, and then the DDR instruction is updated so as to be convenient for receiving the next clock signal.

The system also includes a DDR controller IP core, which performs read/write operations based on the current status DDR instruction sent by the W/R Process Module, outputs write data to the DDR memory, or reads out read data.

In this embodiment, the DDR controller IP core is DDR3 SDRAM Controller IP. DDR3 SDRAM Controller IP is an FPGA package IP, and the interior can be generally subdivided into DDR3 memory controller (DDR 3 Memory Controller) and DDR3 physical layer (DDR 3 PHY).

The DDR3 Memory Controller is connected with the W/R Process Module, and the DDR3 PHY is connected with a DDR3 memory (DDR 3 SDRAM) outside the FPGA through a specified port.

Preferably, if the DDR instruction sent in the current state is a write operation, the write command is started to write to the address, the amount of data to be written (i.e., burst length), and the required data to be written data_ writre _ddr3. Read from WRITE DATA FIFO according to different data amount, and send to the port of DDR3 SDRAM Controller IP.

Preferably, if the current state DDR command is a read operation, a read command, a start read address, a read data amount (i.e., burst length), is sent to the port of DDR3 SDRAM Controller IP, and then data_read_dd3 is waited for and sequentially stored in the read data FIFO.

Example 2

Based on the same method concept, on the basis of the content of the above embodiment, the present embodiment proposes implementation content of a plurality of DDR memories.

As shown in fig. 3, this embodiment proposes a read-write system with multiple DDR memory T-type topology connections.

In this embodiment, the plurality of DDR memories are all the same SDRAM memory. The DDR memories are controlled by the same DDR controller, and the DDR controller is an FPGA.

The DDR memories and the DDR controllers are connected in a T-shaped topology, so that signal synchronization is kept between any DDR memory and the DDR controllers, and the signal quality is the same.

Example 3

As shown in fig. 4, this embodiment proposes a read-write system with a plurality of DDR memories Fly-by topology connection.

To be compatible with a larger number of DDR memories, the wiring scheme is simplified. And the DDR memories and the DDR controllers are connected in a Fly-by topology mode, so that the lengths of the DDR memories are ensured to be as short as possible, and the interference of branch signals on main signals is avoided.

Example 4

Based on the read-write system, the application provides a read-write method of a DDR controller based on an FPGA, which comprises the following steps:

Based on the read-write setting of the system, the method is only applicable to any clock edge of each clock signal, and only comprises a read instruction or a write instruction.

If a write instruction exists in the clock edge, judging and processing the write effective write_valid and the write address write_addr.

If a read instruction exists in the clock edge, the read valid_valid and the read address read_addr are judged to be processed.

As shown in fig. 5, determining a use environment of any clock edge in the current clock signal specifically includes:

judging a first use environment: and judging the existence state of the data.

If the count is zero, updating the DDR instruction; otherwise, the DDR instruction is updated or the next use environment judgment is carried out.

And judging a second use environment: and judging the data quantity. The number of counts that read/write is valid, i.e., the size relationship of burst length to the maximum one-time command burst length, is determined.

If the current DDR command is equal to the maximum primary command burst length, sending the DDR command in the current state to the command cache module, and updating the DDR command; otherwise, updating DDR instruction or entering next use environment judgment.

Third usage environment judgment: and judging whether the instruction exists, namely whether the read instruction/write instruction exists in the current clock edge.

If no read/write command exists, the timeout count is updated or the next use environment judgment is entered. The timeout count is to record the number of clock edges without read/write instructions in the current clock signal and calculate the timeout time according to the number.

Fourth, judgment of using environment: and judging whether the read instruction/write instruction is in a timeout receiving state.

If yes, sending the DDR instruction to an instruction cache module, and updating the DDR instruction; otherwise, the DDR instruction is updated or the next use environment judgment is carried out.

The judging sequence of the use environment can be adjusted at will, the invention does not limit the judging sequence, but any reading instruction/writing instruction must complete all the judging processing procedures in order to ensure that the judgment is not missed.

In any service environment judgment, the instruction cache module is updated or the selection content of the next service environment judgment is entered, if the current judgment module is a final judgment module, the DDR instruction is updated, and the judgment processing is ended; and otherwise, judging the next use environment, and continuing the judgment processing. Further, any judgment of the use environment described in the present invention is merely an exemplary illustration, and does not represent all judgment contents.

If the third usage environment determination is performed in the order of the first usage environment determination and the second usage environment determination, the following steps are:

In the first usage environment determination, in order to ensure that the DDR controller performs efficient reading and writing, it is further required to determine whether a read instruction/write instruction exists before updating the DDR instruction.

In the second usage environment determination, in order to ensure that the DDR controller performs efficient reading and writing, it is further required to determine whether a read command/write command exists before updating the DDR command.

If the third service environment judgment is performed in the judging order before the first service environment judgment, and if the DDR instruction needs to be updated after the first service environment judgment, the judgment of whether the read instruction/write instruction exists or not is not needed to be repeated. If the third usage environment is judged in the judging sequence before the second usage environment is judged, and if the DDR instruction needs to be updated after the second usage environment is judged, the judgment of whether the read instruction/write instruction exists or not is not needed to be repeated.

The DDR instruction is an instruction set for controlling the DDR controller to execute read-write operation, and comprises a read instruction/write instruction, a read address/write address, a burst length and a read valid/write valid. The control read command/write command is a control command for enabling the read operation/write operation based on the obtained read command/write command. The read address/write address is the read address/write address obtained based on the above-described determination result. burst length, based on the above judgment result, the obtained read valid/write valid burst length. And reading the validity/writing the validity, and based on the judging result, obtaining the reading the validity/writing the validity.

Based on the above-mentioned judging process, the present embodiment provides the transmission situation satisfied in the judgment of the use environment of any clock edge, which is specifically as follows:

After the use environment of the current read instruction/write instruction is judged, the number of counts which are effective in reading/writing in the current read instruction/write instruction is counted, and a DDR instruction (state 1) in the current state is sent every time the maximum command burst number is full. The transmitted DDR instruction comprises the current starting address, burst length, read instruction/write instruction and other signals, and then the DDR instruction is updated (state 2) so as to receive the next clock signal conveniently.

After the use environment of any clock edge is judged, in the third use environment judgment, address discontinuity occurs, or even if addresses are continuous, address page crossing boundaries occur, a DDR instruction (state 1) in the current state is sent. The DDR instruction sent contains all information (current start address, burst length, read or write instruction, etc.) before the address crosses the boundary, and then the DDR instruction is updated (state 2) to receive the next clock signal.

3) Switching from a continuous read instruction to a write instruction. When the read command is continuously acquired and the read operation is executed, the write command is acquired at the next clock edge, and after the judgment, the write operation can be performed.

A DDR command of the current state (state 1) is sent. The DDR instruction in the current state comprises signals such as a current starting address, burst length, a read instruction and the like, and then the DDR instruction (state 2) is updated to be a write instruction, so that write operation is conveniently executed.

4) Switching from a continuous write instruction to a read instruction. When the write command is continuously acquired and the write operation is executed, the next clock edge acquires the read command, and after the judgment, the read operation can be performed.

A DDR command of the current state (state 1) is sent. The DDR instruction in the current state comprises signals such as a current starting address, burst length, a write instruction and the like, and then the DDR instruction (state 2) is updated to be a read instruction, so that the read operation is conveniently executed.

5) When the current read command/write command is in a non-empty state, the arrival time of the next command exceeds the set signal receiving time, namely the next command is in a receiving timeout state.

A DDR command of the current state (state 1) is sent. The transmitted DDR instruction comprises the current start address, burst length, read instruction/write instruction and other signals, and then the DDR instruction is updated (state 2) so as to receive the next clock signal. The set signal receiving time is set according to the current hardware condition and the use scenario, and the invention is not limited in particular.

And the DDR controller executes the read operation/write operation through the DDR instruction in the current state sent by the judging process.

Preferably, if the DDR instruction sent in the current state is a write operation, the write command is started to write to the address, the amount of data to be written (i.e., burst length), and the required data to be written data_ writre _ddr3. The write data is output according to different data amounts.

Preferably, if the DDR command in the current state is a read operation, a read command is started to read an address and the read data amount (i.e., burst length) is obtained and stored, and the read data is read.

In yet another aspect, the present invention provides an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing a method for reading and writing an FPGA-based DDR controller as described above when executing the program.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A read-write system of a DDR controller based on an FPGA, comprising:

2. The FPGA-based DDR controller read-write system of claim 1, wherein the read instruction/write instruction information state contained in the instruction has an exception, comprising: in the state where the read instruction/write instruction exists, at least one of an instruction change, an address discontinuity, and an address crossing boundary occurs.

3. The FPGA-based DDR controller read-write system of claim 2, wherein the instruction change comprises: and when the read instruction/write instruction exists, the continuous read instruction is switched to the write instruction or the continuous write instruction is switched to the read instruction, the DDR instruction in the current state is sent, and the DDR instruction is updated to the write instruction/read instruction after the DDR instruction is sent, so that the switched write operation/read operation can be conveniently executed.

4. The FPGA-based DDR controller read-write system of claim 2, wherein the instruction is a timeout receipt state, comprising: the current instruction is in a non-empty state, the arrival time of the next instruction exceeds the set signal receiving time, and the next instruction is in a overtime receiving state.

5. The FPGA-based DDR controller read-write system of claim 3, wherein the current state DDR instruction comprises: and controlling a read instruction/write instruction, a read address/write address, a burst length and a read/write valid.

6. The FPGA-based DDR controller read-write system of claim 1, wherein the data amount comprises: the number of read valid/write valid counts contained in the instruction.

7. The reading and writing method of the DDR controller based on the FPGA is characterized by comprising the following steps of:

8. A computer readable storage medium storing a computer program which when executed by a processor implements the FPGA-based DDR controller read-write method of claim 7.