CN115549671A

CN115549671A - Low-power-consumption level shifter for ultra-wide range voltage conversion

Info

Publication number: CN115549671A
Application number: CN202211379510.5A
Authority: CN
Inventors: 焦海龙; 黄聪
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2022-11-04
Filing date: 2022-11-04
Publication date: 2022-12-30

Abstract

A low-power level shifter for ultra-wide range voltage shifting, wherein a pull-down circuit is used for pulling down a node Q1 to a low level when the level of a low-voltage power domain is high, and pulling down a node Q2 to a low level when the level of the low-voltage power domain is low, a first charging circuit is used for outputting current to the node Q2 in the process that the pull-down circuit pulls down the node Q1 to the low level, so that the potential of the node Q2 is increased, a second charging circuit is used for outputting current to the node Q1 in the process that the pull-down circuit pulls down the node Q2 to the low level, so that the potential of the node Q1 is increased, a complementary pull-up circuit is used for pulling up the node Q2 to the high level of the high-voltage power domain when the node Q1 is low, and the node Q1 is pulled up to the high level of the high-voltage power domain when the node Q2 is low. Because competition between the complementary pull-up circuit and the complementary pull-down circuit is eliminated or reduced, the voltage difference range of the level during level conversion is wider, and the conversion energy consumption during level conversion is reduced.

Description

Low-power-consumption level shifter for ultra-wide range voltage conversion

Technical Field

The invention relates to the technical field of signal processing, in particular to a low-power-consumption level converter for ultra-wide range voltage conversion.

Background

Modern complex systems on chip (SoC) have widely adopted multiple power domains to reduce power consumption while meeting performance requirements. While a level shifter may be added between multiple power domains to satisfy data transmission between multiple power domains, for example, in a multi-power voltage system, signal transmission from a low Voltage (VDDL) power domain to a high Voltage (VDDH) power domain is achieved through the level shifter. Conventional level shifter architectures include a wide variety of, for example, cross-coupled level shifters (CCLS) and Current Mirror Level Shifters (CMLS). The cross-coupled level shifter realizes nearly zero static power consumption through a complementary pull-up network (PUN) and a pull-down network (PDN), but has a limited range of voltage difference between shifted levels during level shifting switching and high shifting power consumption. The current mirror level shifter increases the voltage difference range of the level during level shifting through the current mirror circuit, but has higher static current during level shifting, thereby causing additional static power consumption.

Disclosure of Invention

The invention mainly solves the technical problem of how to improve the voltage difference range of the level during level conversion and reduce the quiescent current.

According to a first aspect, there is provided in one embodiment a low power level shifter for ultra wide range voltage conversion, comprising: the device comprises a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module;

the first control end of the pull-down circuit is used for inputting the level of a low-voltage power domain, the second control end of the pull-down circuit is used for inputting the level opposite to the level type of the low-voltage power domain, the first output end of the pull-down circuit is respectively connected with the first output end and the second control end of the complementary pull-up circuit and forms a node Q1, and the second output end of the pull-down circuit is respectively connected with the second output end and the first control end of the complementary pull-up circuit and forms a node Q2;

the control end of the first charging circuit is used for inputting the level of a low-voltage power supply domain, the output end of the first charging circuit is connected with a node Q2, the control end of the second charging circuit is used for inputting the level with the opposite type to the level of the low-voltage power supply domain, and the output end of the second charging circuit is connected with a node Q1;

the input end of the level output module is used for being connected with at least a node Q1 or a node Q2, the level output module is used for outputting the level of a high-voltage power supply domain according to the potential of the node Q1 or the node Q2, and the type of the level of the high-voltage power supply domain is the same as that of the level of a low-voltage power supply domain;

the pull-down circuit is configured to pull down the node Q1 to a low level when a level of a low-voltage power domain is a high level, and pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level, the first charging circuit is configured to output a current to the node Q2 so that a potential of the node Q2 rises during the pull-down circuit pulls down the node Q1 to the low level, the second charging circuit is configured to output a current to the node Q1 so that a potential of the node Q1 rises during the pull-down circuit pulls down the node Q2 to the low level, and the complementary pull-up circuit is configured to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is the low level, and pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is the low level.

According to a second aspect, an embodiment provides a low power level shifter for ultra wide range voltage shifting, comprising: the device comprises a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module;

the first control end and the second control end of the pull-down circuit are both used for inputting the level of a low-voltage power domain, the first output end of the pull-down circuit is respectively connected with the first output end and the second control end of the complementary pull-up circuit and forms a node Q1, and the second output end of the pull-down circuit is respectively connected with the second output end and the first control end of the complementary pull-up circuit and forms a node Q2;

the control ends of the first charging circuit and the second charging circuit are used for inputting the level of the low-voltage power supply domain, the output end of the first charging circuit is connected with a node Q2, and the output end of the second charging circuit is connected with a node Q1;

the input end of the level output module is at least used for connecting a node Q1 or a node Q2, the level output module is used for outputting the level of a high-voltage power supply domain according to the potential of the node Q1 or the node Q2, and the type of the level of the high-voltage power supply domain is the same as that of the level of a low-voltage power supply domain;

the pull-down circuit is configured to pull down the node Q1 to a low level when a level of a low-voltage power domain is a high level, and pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level, the first charging circuit is configured to output a current to the node Q2 so that a potential of the node Q2 rises in a process that the pull-down circuit pulls down the node Q1 to the low level, the second charging circuit is configured to output a current to the node Q1 so that a potential of the node Q1 rises in a process that the pull-down circuit pulls down the node Q2 to the low level, and the complementary pull-up circuit is configured to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is the low level, and pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is the low level.

According to the low-power-consumption level shifter for ultra-wide-range voltage shifting in the above embodiment, the node Q2 is charged by the first charging circuit, or the node Q1 is charged by the second charging circuit, so that competition between the complementary pull-up circuit and the pull-down circuit at the node Q1 or the node Q2 can be eliminated or reduced, the node Q1 or the node Q2 can be smoothly pulled to a low level by the pull-down circuit, and switching of level shifting is realized. Because competition between the complementary pull-up circuit and the complementary pull-down circuit is eliminated or reduced, the voltage difference range of the level during level conversion can be wider, and the conversion energy consumption during level conversion can be reduced. And because the first charging circuit and the second charging circuit charge the node Q1 or the node Q2 for a short time only in the process that the pull-down circuit pulls down the node Q1 or the node Q2 to a low level, the first charging circuit and the second charging circuit only consume less power consumption, and do not increase extra power consumption, so that the overall power consumption of the level converter is reduced.

Drawings

FIG. 1 is a cross-coupled level shifter of the prior art;

FIG. 2 is a circuit diagram of a low power level shifter for ultra-wide range voltage conversion according to one embodiment;

FIG. 3 is a diagram of an embodiment of a high-level shift to a low-level shift of a low-power level shifter for ultra-wide range voltage shifting;

FIG. 4 is a diagram of a low level shift to a high level shift of a low power level shifter for ultra wide range voltage shifting according to an embodiment;

fig. 5 is a circuit diagram of a low power level shifter for ultra-wide range voltage conversion in accordance with another embodiment.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

Referring to fig. 1, the cross-coupled level shifter includes a complementary pull-up network formed by transistors P9 and P10, and a pull-down network formed by transistor N9 and transistor N10, which can achieve a static power consumption close to zero. However, when level conversion is performed, for example, when level conversion is performed by high level conversion, there is current competition between the VDDL-driven weak pull-down network and the VDDH-driven strong complementary pull-up network, for example, the current competition between the transistor P9 and the transistor N9 at the node Q4, and the current competition between the transistor P10 and the transistor N10 at the node Q5, which may cause failure of level conversion, and also generate higher conversion power consumption.

In the embodiment of the invention, in the process of switching level conversion, the first charging circuit or the second charging circuit is used for charging the connection node between the pull-down circuit and the complementary pull-up circuit, so that the current competition between the pull-down circuit and the complementary pull-up circuit can be eliminated or reduced, the voltage difference range of the level during level conversion is improved, and the conversion energy consumption is reduced. And the charging time of the first charging circuit and the second charging circuit is short, so that more power consumption is not increased, and the overall power consumption of the level shifter can be reduced.

It should be noted that the transistor in the present invention may be a transistor of any structure, such as a Bipolar Junction Transistor (BJT), a Field Effect Transistor (FET), or a Thin Film Transistor (TFT), unless otherwise specified. When the transistor is a bipolar transistor, the control electrode of the transistor refers to the base electrode of the bipolar transistor, the first electrode can be the collector electrode or the emitter electrode of the bipolar transistor, the corresponding second electrode can be the emitter electrode or the collector electrode of the bipolar transistor, and in the practical application process, the emitter electrode and the collector electrode can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, the control electrode refers to a gate electrode of the field effect transistor, the first electrode may be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode may be a source electrode or a drain electrode of the field effect transistor, and in an actual application process, "source electrode" and "drain electrode" may be interchanged according to a signal flow direction.

The first embodiment is as follows:

the present embodiment provides a low power level shifter for ultra-wide range voltage shifting for shifting the level (IN) of a low voltage power domain to the level (OUT) of a high voltage power domain, such as shifting the high level VDDL of the low voltage power domain to the high level VDDH of the high voltage power domain, or shifting the low level of the low voltage power domain to the low level of the high voltage power domain. In the following embodiments, the high-voltage power domain and the low-voltage power domain share the same ground, that is, the ground potentials of the high-voltage power domain and the low-voltage power domain are the same. Referring to fig. 2, the low power consumption level shifter for ultra-wide range voltage conversion includes a pull-down circuit 10, a complementary pull-up circuit 20, a first charging circuit 30, a second charging circuit 40, and a level output module 50, which will be described in detail below.

The pull-down circuit 10 has a power supply terminal, a first control terminal, a second control terminal, a first output terminal, and a second output terminal. The first control terminal of the pull-down circuit 10 is configured to input a level (IN) of the low-voltage power domain, such as a low level or a high level, the second control terminal of the pull-down circuit 10 is configured to input a level (INB) with a type opposite to that of the low-voltage power domain, for example, when the level of the low-voltage power domain is a high level, the low level of the low-voltage power domain is input, and the power terminal of the pull-down circuit 10 is connected to a ground potential. The pull-down circuit 10 is configured to control the outputs of the first output terminal and the second output terminal according to the level of the control terminal thereof, for example, when the level of the input low-voltage power domain is a high level, the pull-down circuit 10 outputs a low level through the first output terminal thereof, and otherwise outputs a low level through the second output terminal thereof. Therefore, the pull-down circuit 10 can pull down the potential of the first output terminal or the second output terminal to a low level according to the level of the low voltage power domain. In some embodiments, the level of the low voltage power domain input to the first control terminal of the pull-down circuit 10 may be converted by an inverter and then input to the second control terminal of the pull-down circuit 10.

The complementary pull-up circuit 20 has a power supply terminal, a first control terminal, a second control terminal, a first output terminal and a second output terminal. The first output end and the second control end of the complementary pull-up circuit 20 are connected with the first output end of the pull-down circuit 10 to form a node Q1, the second output end and the first control end of the complementary pull-up circuit 20 are connected with the second output end of the pull-down circuit 10 to form a node Q2, and the power supply end of the complementary pull-up circuit 20 is connected with the high level VDDH of the high-voltage power supply domain. The complementary pull-up circuit 20 is configured to control the output of the first output terminal and the second output terminal according to the level of the control terminal thereof, for example, when the first control terminal thereof inputs a low level, the complementary pull-up circuit 20 outputs the high level VDDH of the high voltage power domain through the first output terminal thereof, and otherwise outputs the high level VDDH of the high voltage power domain through the second output terminal thereof. Therefore, the complementary pull-up circuit 20 can pull up the potential of the first output terminal or the second output terminal to the high level VDDH of the high voltage power supply domain according to the level of the control terminal.

The control terminal of the first charging circuit 30 is used for inputting the level of the low voltage power domain, and the output terminal of the first charging circuit 30 is connected to the node Q2. The first charging circuit 30 is configured to output a current to the node Q2 through an output terminal thereof to raise a potential thereof by charging the node Q2, in a process in which the pull-down circuit 10 pulls down the node Q1 to a low level, that is, when a level of the low-voltage power domain changes from a low level to a high level.

The control terminal of the second charging circuit 40 is used for inputting a level opposite to the level type of the low-voltage power domain, and the output terminal of the second charging circuit 40 is connected with the node Q1. In the process that the pull-down circuit 10 pulls down the node Q2 to the low level, that is, the level of the low-voltage power domain changes from the high level to the low level, the second charging circuit 40 is configured to output a current to the node Q1 through its output terminal to raise its potential by charging the node Q1. In some embodiments, the level of the low voltage power domain input to the control terminal of the first charging circuit 30 may be converted by an inverter and then input to the control terminal of the second charging circuit 40.

The level output module 50 is configured to output a level of the high voltage power domain according to a potential of the node Q1 or the node Q2, where the level of the high voltage power domain is the same type as the level of the low voltage power domain. In some embodiments, the input terminal of the level output module 50 is connected to the node Q1, when the node Q1 is pulled down to a low level by the pull-down circuit 10, the level output module 50 outputs a high level VDDH of the high voltage power domain, and when the node Q1 is pulled up to the high level VDDH of the high voltage power domain by the complementary pull-up circuit 20, the level output module 50 outputs a low level of the high voltage power domain, so that the level of the low voltage power domain is converted into the level of the high voltage power domain. In some embodiments, the input terminal of the level output module 50 is connected to the node Q2, and when the node Q2 is pulled up to the high level VDDH of the high voltage power domain by the complementary pull-up circuit 20, the level output module 50 outputs the high level VDDH of the high voltage power domain, and when the node Q2 is pulled down to the low level by the pull-down circuit 10, the level output module 50 outputs the low level of the high voltage power domain.

The operation of the low power level shifter for ultra wide range voltage shifting is described below.

Referring to fig. 2, when the level shifter performs a low level shift from the low voltage power domain to the high voltage power domain, the first control terminal of the pull-down circuit 10 inputs a low level of the low voltage power domain, and the second control terminal of the pull-down circuit 10 inputs a high level VDDL of the low voltage power domain, so that the node Q2 is pulled down to a low level, such that the first control terminal of the complementary pull-up circuit 20 inputs a low level, and the node Q1 is pulled up to a high level VDDH of the high voltage power domain. Then, the level output module 50 outputs the low level of the high-voltage power domain according to the potential of the node Q1 or the node Q2, so that when the level shifter inputs the low level of the low-voltage power domain, the low level of the high-voltage power domain can be output.

Referring to fig. 2, when the level shifter performs the high level shift from the low voltage power domain to the high voltage power domain, the first control terminal of the pull-down circuit 10 inputs the high level VDDL of the low voltage power domain, and the second control terminal of the pull-down circuit 10 inputs the low level of the low voltage power domain, so that the node Q1 is pulled down to the low level, so that the second control terminal of the complementary pull-up circuit 20 inputs the low level, and the node Q2 is pulled up to the high level VDDH of the high voltage power domain. Then, the level output module 50 outputs the high level VDDH of the high voltage power domain according to the potential of the node Q1 or the node Q2, so that when the level converter inputs the high level VDDL of the low voltage power domain, the high level VDDH of the high voltage power domain can be output,

referring to fig. 3, when the level shifter switches from the high level shift from the low voltage power domain to the high voltage power domain to the low level shift, VDDL of the low voltage power domain input to the first control terminal of the pull-down circuit 10 and the control terminal of the first charging circuit 30 changes to the low level, and VDDL of the low voltage power domain input to the second control terminal of the pull-down circuit 10 and the control terminal of the second charging circuit 40 changes to the high level. At this time, the node Q1 and the node Q2 are also maintained in the high level transition state, that is, the potential of the node Q1 is low, and the potential of the node Q2 is high VDDH of the high voltage power supply domain. Therefore, in the process that the second output terminal of the pull-down circuit 10 pulls down the potential of the node Q2 to the low level, it is necessary to compete with the second output terminal of the complementary pull-up circuit 20, and thus there is a possibility that the level transition fails. However, at this time, since the output terminal of the second charging circuit 40 can charge the node Q1, the potential of the node Q1 rises, for example, to a high level, so that the second control terminal of the complementary pull-up circuit 20 changes from a low level to a high level, and the second output terminal of the complementary pull-up circuit 20 cannot maintain the high level VDDH for pulling up the node Q2 to the high-voltage power supply domain, or the maintaining capability thereof is reduced. Therefore, the node Q2 is pulled down to the low level by the pull-down circuit 10, so that the first control terminal of the complementary pull-up circuit 20 inputs the low level, the output terminal of the second charging circuit 40 stops charging the node Q1, the node Q1 is pulled up to the high level VDDH of the high-voltage power domain by the complementary pull-up circuit 20, and finally the level output module 50 outputs the low level of the high-voltage power domain.

Referring to fig. 4, when the level shifter switches from the low level shift from the low voltage power domain to the high level shift, the low level of the low voltage power domain input by the first control terminal of the pull-down circuit 10 and the control terminal of the first charging circuit 30 changes to the high level, and the high level VDDL of the low voltage power domain input by the second control terminal of the pull-down circuit 10 and the control terminal of the second charging circuit 40 changes to the low level. At this time, the node Q1 and the node Q2 are also maintained in the state at the time of low level transition, that is, the potential of the node Q1 is at the high level VDDH of the high voltage power supply domain, and the potential of the node Q2 is at the low level. Therefore, in the process of pulling down the potential of the node Q1 to the low level by the first output terminal of the pull-down circuit 10, it is necessary to compete with the first output terminal of the complementary pull-up circuit 20, and thus there is also a possibility that the level transition will fail. In this regard, the node Q2 is charged by the output terminal of the first charging circuit 30, so that the potential of the node Q2 rises, for example, to a high level, and the first control terminal of the complementary pull-up circuit 20 changes from a low level to a high level, so that the first output terminal of the complementary pull-up circuit 20 cannot maintain the high level VDDH for pulling up the node Q1 to the high-voltage power supply domain, or reduce the maintaining capability thereof. As a result, the node Q1 is pulled down to the low level by the pull-down circuit 10, so that the second control terminal of the complementary pull-up circuit 20 inputs the low level, the output terminal of the first charging circuit 30 stops charging the node Q2, the node Q2 is pulled up to the high level VDDH of the high voltage power domain by the complementary pull-up circuit 20, and finally the level output module 50 outputs the high level VDDH of the high voltage power domain.

As can be seen from the above embodiments, when the level shifter maintains the low level shift or the high level shift from the low voltage power domain to the high voltage power domain, the potential of the node Q1 or the node Q2 may be made to be at the high level VDDH of the high voltage power domain by the complementary pull-up circuit 20, or the potential of the node Q1 or the node Q2 may be made to be at the low level by the pull-down circuit 10, and then the low level or the high level of the high voltage power domain may be output through the output module. Since the output terminal and the control terminal of the complementary pull-up circuit 20 are cross-coupled, so that the output terminal between the complementary pull-up circuit 20 and the pull-down circuit 10 is also cross-output, a lower static power consumption can be achieved.

As can be seen from the above embodiments, when the level shifter switches from the low level to the high level in the low voltage power domain, the node Q2 is charged by the first charging circuit 30 to eliminate or reduce the contention between the complementary pull-up circuit 20 and the pull-down circuit 10 at the node Q1, so that the node Q1 can be switched from the high level VDDH to the low level in the high voltage power domain smoothly. When the level shifter switches from the low-voltage power domain to the high-voltage power domain to the low-level, the node Q1 is charged by the second charging circuit 40 to eliminate or reduce the contention between the complementary pull-up circuit 20 and the pull-down circuit 10 at the node Q2, so that the node Q2 can be switched from the high-level VDDH of the high-voltage power domain to the low-level smoothly. Because the competition between the complementary pull-up circuit 20 and the pull-down circuit 10 is eliminated or reduced, the voltage difference range of the level during level conversion can be wider, for example, the voltage difference between the high level VDDH of the low-voltage power domain and the high-voltage power domain can be larger, and the conversion energy consumption during level conversion can also be reduced. And because the first charging circuit 30 and the second charging circuit 40 charge the node Q1 or the node Q2 only for a short time in the process that the pull-down circuit 10 pulls down the node Q1 or the node Q2 to the low level, the first charging circuit 30 and the second charging circuit 40 only consume small power consumption, and do not increase extra power consumption, so that the overall power consumption of the level shifter is reduced.

Referring to fig. 2, in some embodiments, the level output module 50 includes an inverting unit for inverting the type of the input level and outputting the inverted level. The power supply end of the inverting unit is connected with the high level VDDH of the high-voltage power supply domain, the input end of the inverting unit is connected with the node Q1, and the output end of the inverting unit is used for outputting the level of the high-voltage power supply domain. When the potential of the node Q1 is at the low level, the inverting unit inverts the low level and outputs the high level VDDH of the high voltage power domain, and when the potential of the node Q1 is at the high level VDDH of the high voltage power domain, the inverting unit inverts the high level VDDH of the high voltage power domain and outputs the low level of the high voltage power domain. In some embodiments, the inverting unit may be implemented by an inverter, and since the node Q1 may reach a full swing of the high level VDDH of the high voltage power domain, the inverter may not have a large quiescent current when performing inverting output, thereby implementing low power consumption inverting output.

In some embodiments, the inverting unit is configured to output the input level after inverting the input level twice. The power supply end of the inverting unit is connected with the high level VDDH of the high-voltage power supply domain, the input end of the inverting unit is connected with the node Q2, and the output end of the inverting unit is used for outputting the level of the high-voltage power supply domain. When the potential of the node Q2 is low, the inverting unit inverts the low level twice and outputs the ground level of the high voltage domain, and when the potential of the node Q2 is high level VDDH of the high voltage domain, the inverting unit inverts the high level VDDH of the high voltage domain twice and outputs the high level VDDH of the high voltage domain. In some embodiments, the inverting unit may be implemented using two cascaded inverters.

Referring to fig. 2, 3 and 4, in some embodiments, the pull-down circuit 10 includes a transistor N3 and a transistor N4, and the complementary pull-up circuit 20 includes a transistor P3 and a transistor P4. A first pole of transistor N3 is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, respectively, i.e., the second pole of transistor P3 and the control pole of transistor P4, to form node Q1. A first pole of transistor N4 is connected to the second output terminal and the first control terminal of the complementary pull-up circuit 20, i.e., the control pole of transistor P3 and the second pole of transistor P4, respectively, to form node Q2. The second poles of the transistors N3 and N4 are connected to the ground potential, and the first poles of the transistors P3 and P4 are connected to the high level VDDH of the high voltage power supply domain. The control electrode of the transistor N3 is used for inputting the level of the low voltage power domain, and the control electrode of the transistor N4 is used for inputting the level of the type opposite to the level of the low voltage power domain.

The transistor N3 is turned on when the level of the low voltage power domain is high to pull down the node Q1 to low level, and the transistor N4 is turned on when the level of the low voltage power domain is low to pull down the node Q2 to low level. Transistor P4 is configured to turn on when the node Q1 is low to pull up the node Q2 to the high level VDDH of the high voltage power supply domain, and transistor P3 is configured to turn on when the node Q2 is low to pull up the node Q1 to the high level VDDH of the high voltage power supply domain.

As described above, when the level of the low voltage power supply domain is low, the transistor N4 and the transistor P3 are turned on, so that the potential of the node Q2 is low while the potential of the Q1 is high VDDH of the high voltage power supply domain. When the level of the low voltage power domain is high, the transistors N3 and P4 are turned on, so that the potential of the node Q1 is low, and the potential of the node Q2 is high VDDH of the high voltage power domain. Because transistors N3, N4, P3, and P4 are all cross-coupled, a near-zero static power dissipation is achieved between pull-down circuit 10 and complementary pull-up circuit 20. Meanwhile, when the level of the low voltage power domain is switched from low level to high level or from high level to low level, there is current competition between the transistor P3 and the transistor N3 at the node Q1, and there is current competition between the transistor P4 and the transistor N4 at the node Q2, so that the first charging circuit 30 is required to charge the node Q2, thereby weakening the driving strength of the transistor P3 and reducing the pull-up strength thereof, so that the transistor N3 easily pulls the node Q1 to low level. And the second charging circuit 40 charges the node Q1, weakening the driving strength of the transistor P4, and reducing its pull-up strength, so that the transistor N4 easily pulls the node Q2 to a low level, thereby eliminating the contention between the complementary pull-up circuit 20 and the pull-down circuit 10.

In this embodiment, the transistors N3 and N4 are N-type transistors, and the first poles thereof are both source electrodes, the second poles thereof are both drain electrodes, and the control electrodes thereof are both gate electrodes. The transistors P3 and P4 are P-type transistors, the first poles of which are both drain electrodes, the second poles of which are both source electrodes, and the control electrodes of which are both grid electrodes. It will be appreciated that the type of transistor can be varied or the connection can be adapted as required, which will also achieve the same effect.

Referring to fig. 2 and 4, in some embodiments, the first charging circuit 30 includes a first current mirror circuit 32, a transistor N1 and a transistor N2, and in some embodiments, the first current mirror circuit 32 includes a transistor P1 and a transistor P2. The power supply terminal of the first current mirror circuit 32 is connected to the high level VDDH of the high voltage power supply domain, i.e., the first poles of the transistors P1 and P2. The first output terminal of the first current mirror circuit 32 is connected to the first pole of the transistor N1, i.e., the second pole of the transistor P1, and the second pole of the transistor P1 is also connected to the control pole thereof and the control pole of the transistor P2, respectively. A second output terminal of the first current mirror circuit 32 is connected to node Q2, which is a second pole of transistor P2. The second pole of the transistor N1 is connected to the first pole of the transistor N2, and the second pole of the transistor N2 is connected to the ground potential. The control electrode of the transistor N1 is connected to the node Q1, and the control electrode of the transistor N2 is used for inputting the level of the low-voltage power supply domain.

The transistor N2 is used for turning on when the level of the low-voltage power domain is high, and the transistor N1 is used for turning on when the node Q1 is high. When both the transistor N1 and the transistor N2 are turned on, both the transistor P1 and the transistor P2 are also turned on, and output a current to the node Q2 through the second pole of the transistor P2.

As can be seen from the above description, the transistor N1 and the transistor N2 are used to control the on/off of the first current mirror circuit 32, that is, only when the transistor N1 and the transistor N2 are turned on simultaneously, the first current mirror circuit 32 outputs current to the node Q2. In this embodiment, when the level shifter maintains the low level shift from the low voltage power domain to the high voltage power domain, only the transistor N1 is turned on, and the first current mirror circuit 32 is in the off state, and no static current is generated. When the level shifter switches from low level conversion from low voltage power domain to high level conversion, because there is competition between the pull-down circuit 10 and the complementary pull-up circuit 20, and the node Q1 and the node Q2 are respectively maintained at high level VDDH and low level of the high voltage power domain, at this time, the transistor N1 and the transistor N2 are both turned on, so that the first current mirror circuit 32 is turned on to charge the node Q2, so that the low level conversion from the low voltage power domain to the high voltage power domain of the level shifter is successfully switched to high level conversion, and after the successful switching, the node Q1 and the node Q2 are again maintained at high level VDDH of the low level and the high voltage power domain, respectively, so that no static current state of the complementary pull-up circuit and pull-down circuit is ensured, and at this time, only the transistor N2 is turned on, so that the first current mirror circuit 32 is turned off again, and no static current is generated. Therefore, the first charging circuit 30 can alleviate the competition between the complementary pull-up circuit 20 and the pull-down circuit 10, and at the same time, will not generate static current and will not generate much extra power consumption.

Referring to fig. 2 and 3, in some embodiments, the second charging circuit 40 includes a second current mirror circuit 42, a transistor N5, and a transistor N6, and in some embodiments, the second current mirror circuit 42 includes a transistor P5 and a transistor P6. The power supply terminal of the second current mirror circuit 42 is connected to the high level VDDH of the high voltage power supply domain, i.e., the first poles of the transistors P5 and P6. A first output terminal of the second current mirror circuit 42 is connected to a first pole of the transistor N5, i.e., a second pole of the transistor P6, and the second pole of the transistor P6 is further connected to a control pole thereof and a control pole of the transistor P5, respectively. A second output terminal of the second current mirror circuit 42 is connected to node Q1, which is a second pole of the transistor P5. A second pole of the transistor N5 is connected to the first pole of the transistor N6, a second pole of the transistor N6 is connected to the ground potential, a control pole of the transistor N5 is connected to the node Q2, and a control pole of the transistor N6 is used for inputting a level of a type opposite to that of the low-voltage power supply domain.

Transistor N6 is configured to turn on when the low voltage power domain is low, and transistor N5 is configured to turn on when node Q2 is high. When both the transistor N5 and the transistor N6 are turned on, both the transistor P5 and the transistor P6 are also turned on, and output a current to the node Q1 through the second pole of the transistor P5.

As can be seen from the above description, the working principle of the second charging circuit 40 in this embodiment is the same as that of the first charging circuit 30, so that the second charging circuit 40 can also relieve the competition of the complementary pull-up circuit 20 and pull-down circuit 10, and meanwhile, no static current is generated and no more extra power consumption is generated, which is not described herein again. In the present embodiment, the pull-up strength of the complementary pull-up circuit 20 is dynamically adjusted by the first charging circuit 30 and the second charging circuit 40, so that the level shifter has good delay scalability, and the delay is small even when the difference between the high level VDDL of the low-voltage power domain and the high level VDDH of the high-voltage power domain is small.

In this embodiment, the transistors N1, N2, N5, and N6 are N-type transistors, and the first poles thereof are all source electrodes, the second poles thereof are all drain electrodes, and the control poles thereof are all gate electrodes. The transistors P1, P2, P5 and P6 are P-type transistors, the first poles of which are all drains, the second poles of which are all sources, and the control poles of which are all gates. It will be appreciated that the transistor type can be changed or the connection can be adapted as desired, which can achieve the same effect.

Referring to fig. 2 and 5, in some embodiments, the pull-down circuit 10 includes a pull-down unit and a voltage drop unit, and in some embodiments, the pull-down unit includes a transistor N3 and a transistor N4. A first terminal of the voltage dropping unit is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, i.e., the second pole of the transistor P3 and the control pole of the transistor P4, respectively, to form a node Q1. The power supply terminals of the pull-down units are connected to ground potential, i.e. the second poles of transistors N3 and N4. The second terminal of the voltage dropping unit is connected to the first output terminal of the pull-down unit, i.e., the first pole of the transistor N3, to form a node Q3. A first control terminal of the pull-down unit is configured to input a level of the low-voltage power domain, i.e., a control electrode of the transistor N3, a second control terminal of the pull-down unit is configured to input a level of a type opposite to the level of the low-voltage power domain, i.e., a control electrode of the transistor N4, and second output terminals of the pull-down unit are respectively connected to a second output terminal and a first control terminal of the complementary pull-up circuit 20, i.e., a first electrode of the transistor N4 is respectively connected to a control electrode of the transistor P3 and a second electrode of the transistor P4, so as to form a node Q2.

The voltage dropping unit is used for generating preset voltage drop between the first end and the second end of the voltage dropping unit, and the transistor N3 is used for being conducted when the level of the low-voltage power supply domain is high level so as to pull down the node Q3 to low level and pull down the node Q1 to low level through the voltage dropping unit. The transistor N4 is turned on when the level of the low voltage power domain is low, so as to pull down the node Q2 to a low level.

As can be seen from the above description, since the voltage drop unit can generate a voltage drop between the node Q1 and the node Q3, so that the potential of the node Q1 is always greater than that of the node Q3, the transistor N3 and the transistor P3 can further weaken the transistor P3 when the node Q1 competes, thereby further increasing the speed of switching the level shifter from the low-level shift to the high-level shift of the low-voltage power domain. It is understood that the voltage drop unit may also be connected between the transistor P4 and the transistor N4, and then the node Q2 may be connected to the input terminal of the level output module 50.

In some embodiments, the voltage dropping unit includes a transistor N8. A first pole of transistor N8 is connected to its control pole, respectively, a second pole of transistor P3 and the control pole of transistor P4 to form node Q1, and a second pole of transistor N8 is connected to the first pole of transistor N3.

In some embodiments, the voltage drop unit comprises a resistor. A first terminal of the resistor is connected to the second pole of transistor P3 and the control pole of transistor P4, respectively, to form node Q1, and a second terminal of the resistor is connected to the first pole of transistor N3.

In some embodiments, the voltage drop unit comprises a diode. The anode of the diode is connected to the second pole of P3 and the control pole of transistor P4, respectively, to form node Q1, and the cathode of the diode is connected to the first pole of transistor N3.

Referring to fig. 2 and 5, in some embodiments, the level output module 50 includes a transistor P7 and a transistor N7. A first electrode of the transistor P7 is connected to the high level VDDH of the high voltage power supply domain, a control electrode of the transistor P7 is connected to the node Q1, a second electrode of the transistor P7 is connected to a first electrode of the transistor N7, a second electrode of the transistor N7 is connected to the ground potential, and a control electrode of the transistor N7 is connected to the node Q3. When the node Q1 is at the high level VDDH of the high voltage power domain, the transistor N7 is turned on, and the node between the transistor P7 and the transistor N7 outputs low, and when the node Q3 is at low level, the transistor P7 is turned on, and the node between the transistor P7 and the transistor N7 outputs the high level VDDH of the high voltage power domain.

Example two:

the present embodiment provides a low power consumption level shifter for ultra-wide range voltage conversion, which is different from the first embodiment IN that the first control terminal and the second control terminal of the pull-down circuit 10 are both used for inputting the level (IN) of the low voltage power domain, and the control terminals of the first charging circuit 30 and the second charging circuit 40 are both used for inputting the level (IN) of the low voltage power domain, and the differences are specifically described below.

Referring to fig. 5, in some embodiments, the pull-down circuit 10 includes a pull-down unit and a voltage drop unit, and in some embodiments, the pull-down unit includes a transistor N3 and a transistor N4. A first terminal of the voltage dropping unit is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, i.e., the second pole of the transistor P3 and the control pole of the transistor P4, respectively, to form a node Q1. The second terminal of the voltage dropping unit is connected to the first output terminal of the pull-down unit, i.e., the first pole of the transistor N3, to form a node Q3. The first control terminal of the pull-down unit is used for inputting the level of the low-voltage power domain, i.e. the control electrode of the transistor N3. The second control terminal of the pull-down unit is used for inputting the level of the low-voltage power domain, i.e. the second pole of the transistor N4. The second output terminal of the pull-down unit is connected to the second output terminal and the first control terminal of the complementary pull-up circuit 20, respectively, i.e., the first pole of the transistor N4 is connected to the control pole of the transistor P3 and the second pole of the transistor P4, respectively, to form a node Q2. The second terminal of the transistor N3 is connected to ground potential, and the control terminal of the transistor N4 is connected to the high level VDDL of the low voltage power supply domain.

As can be seen from the above description, since the voltage drop unit can generate a voltage drop between the node Q1 and the node Q3, so that the potential of the node Q1 is always greater than that of the node Q3, the transistor N3 and the transistor P3 can further weaken the transistor P3 when the node Q1 competes, thereby further increasing the speed of switching the level shifter from the low-voltage power domain to the high-voltage power domain. It is understood that the voltage drop unit may also be connected between the transistor P4 and the transistor N4, and then the node Q2 may be connected to the input terminal of the level output module 50

Referring to fig. 5, in some embodiments, the second charging circuit 40 includes a second current mirror circuit 42, a transistor N5, and a transistor N6, and in some embodiments, the second current mirror circuit 42 includes a transistor P5 and a transistor P6. The power supply terminal of the second current mirror circuit 42 is connected to the high level VDDH of the high voltage power supply domain, i.e., the first poles of the transistors P5 and P6. The first output terminal of the second current mirror circuit 42 is connected to the first pole of the transistor N5, i.e., the second pole of the transistor P6, and the second pole of the transistor P6 is also connected to the control pole thereof and the control pole of the transistor P5, respectively. A second output terminal of the second current mirror circuit 42 is connected to node Q1, which is a second pole of the transistor P5. The second pole of the transistor N5 is connected to the first pole of the transistor N6, the second pole of the transistor N6 is used for inputting the level of the low voltage power domain, the control pole of the transistor N5 is connected to the node Q2, and the control pole of the transistor N6 is connected to the high level VDDL of the low voltage power domain.

As can be seen from the above description, the high level VDDL of the low voltage power domain is input to the control electrodes of the transistors N4 and N6, and then the on and off are directly controlled by the level of the low voltage power domain input to the second electrode, so that the speed of switching from the high level conversion of the low voltage power domain to the high voltage power domain of the level shifter can be further increased.

Referring to fig. 5 and 2, in some embodiments, the transistors P1, P2, P3, P4, P5, and P6 are high threshold voltage (HVT) transistors. The transistor N2, the transistor N6, and the transistor N8 each employ a low threshold voltage (LVT) transistor. And transistors N1, N3, N4, N5, N7, and P7 all employ conventional threshold voltage (RVT) transistors. The present embodiment implements the proposed level shifter using multiple threshold voltage transistors with long channel lengths and a multi-finger structure, thereby achieving a better balance between switching speed, overall power and area efficiency.

The present invention has been described in terms of specific examples, which are provided to aid in understanding the invention and are not intended to be limiting. Numerous simple deductions, modifications or substitutions may also be made by those skilled in the art in light of the present teachings.

Claims

1. A low power consumption level shifter for ultra wide range voltage shifting, comprising: the device comprises a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module;

2. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 1, wherein said pull-down circuit comprises transistor N3 and transistor N4;

a first pole of the transistor N3 is connected to a first output terminal and a second control terminal of the complementary pull-up circuit, respectively, to form a node Q1, a first pole of the transistor N4 is connected to a second output terminal and a first control terminal of the complementary pull-up circuit, respectively, to form a node Q2, second poles of the transistor N3 and the transistor N4 are both connected to a ground potential, a control pole of the transistor N3 is used for inputting a level of the low-voltage power domain, and a control pole of the transistor N4 is used for inputting a level of a type opposite to that of the low-voltage power domain;

the transistor N3 is turned on when the level of the low-voltage power domain is a high level to pull down the node Q1 to a low level, and the transistor N4 is turned on when the level of the low-voltage power domain is a low level to pull down the node Q2 to a low level.

3. A low power level converter for ultra-wide range voltage conversion, as claimed in claim 1, wherein said second charging circuit comprises a second current mirror circuit, transistor N5 and transistor N6;

a first output end of the second current mirror circuit is connected with a first pole of a transistor N5, a second output end of the second current mirror circuit is connected with a node Q1, a second pole of the transistor N5 is connected with a first pole of a transistor N6, a second pole of the transistor N6 is connected with the ground potential, a control pole of the transistor N5 is connected with a node Q2, and a control pole of the transistor N6 is used for inputting a level which is opposite to the level type of the low-voltage power supply domain;

the transistor N6 is used for being turned on when the level of the low-voltage power domain is low level, the transistor N5 is used for being turned on when the node Q2 is high level, and the second current mirror circuit is used for outputting current to the node Q1 through the second output end when the transistor N5 and the transistor N6 are both turned on until the potential of the node Q2 is pulled down to low level by the pull-down circuit, so that the transistor N5 is turned off.

4. A low power consumption level converter for ultra-wide range voltage conversion as recited in claim 3, wherein said second current mirror circuit comprises a transistor P5 and a transistor P6;

first poles of the transistors P5 and P6 are both connected to a high level of the high voltage power supply domain, a second pole of the transistor P6 is connected to a control pole thereof, a control pole of the transistor P5 and a first pole of the transistor N5, respectively, a second pole of the transistor P5 is connected to the node Q1, and when the transistors N5 and N6 are both turned on, the transistors P5 and P6 are also turned on, and output a current to the node Q1 through the second pole of the transistor P5.

5. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 1, wherein said pull-down circuit comprises a pull-down unit and a voltage drop unit;

the first end of the voltage drop unit is respectively connected with the first output end and the second control end of the complementary pull-up circuit to form a node Q1, the second end of the voltage drop unit is connected with the first output end of the pull-down unit to form a node Q3, the first control end of the pull-down unit is used for inputting the level of a low-voltage power domain, the second control end of the pull-down unit is used for inputting the level opposite to the level type of the low-voltage power domain, and the second output end of the voltage drop unit is respectively connected with the second output end and the first control end of the complementary pull-up circuit to form a node Q2;

the voltage drop unit is used for generating preset voltage drop between the first end and the second end of the voltage drop unit, and the pull-down unit is used for pulling down the node Q3 to a low level when the level of the low-voltage power supply domain is a high level, pulling down the node Q1 to a low level through the voltage drop unit, and pulling down the node Q2 to a low level when the level of the low-voltage power supply domain is a low level.

6. A low power consumption level shifter for ultra wide range voltage conversion, as recited in claim 5, wherein said pull-down cell comprises transistor N3 and transistor N4;

a first pole of the transistor N3 is connected to the second end of the voltage drop unit, a first pole of the transistor N4 is respectively connected to the second output end and the first control end of the complementary pull-up circuit to form a node Q2, second poles of the transistor N3 and the transistor N4 are both connected to a ground potential, a control pole of the transistor N3 is used for inputting the level of the low-voltage power domain, and a control pole of the transistor N4 is used for inputting the level of the low-voltage power domain, wherein the level is of the opposite type to the level of the low-voltage power domain;

7. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 5, wherein said voltage dropping unit comprises a transistor N8, a first pole of said transistor N8 being connected to a control pole thereof, a first output terminal and a second control terminal of a complementary pull-up circuit, respectively, to form a node Q1, a second pole of said transistor N8 being connected to a first output terminal of a pull-down unit;

or the voltage drop unit comprises a resistor, a first end of the resistor is connected with a first output end and a second control end of the complementary pull-up circuit respectively to form a node Q1, and a second end of the resistor is connected with a first output end of the pull-down unit;

or, the voltage drop unit includes a diode, anodes of the diodes are respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and a cathode of the diode is connected to the first output terminal of the pull-down unit.

8. A low power level shifter for ultra wide range voltage conversion, comprising: the device comprises a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module;

9. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 8, wherein said pull-down circuit comprises a pull-down unit and a voltage drop unit;

a first end of the voltage drop unit is connected with a first output end and a second control end of the complementary pull-up circuit respectively to form a node Q1, a second end of the voltage drop unit is connected with a first output end of the pull-down unit to form a node Q3, the first control end and the second control end of the pull-down unit are both used for inputting the level of a low-voltage power domain, and the second output end is connected with the second output end and the first control end of the complementary pull-up circuit respectively to form a node Q2;

10. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 9, wherein said pull-down unit comprises transistor N3 and transistor N4;

a first pole of the transistor N3 is connected to the second end of the voltage drop unit to form a node Q3, a second pole of the transistor N3 is connected to the ground potential, a first pole of the transistor N4 is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit to form a node Q2, a control pole of the transistor N3 and a second pole of the transistor N4 are both used for inputting the level of the low-voltage power domain, and a control pole of the transistor N4 is connected to the high level of the low-voltage power domain;

the transistor N3 is turned on when the level of the low-voltage power domain is a high level to pull down the node Q3 to a low level, and the transistor N4 is turned on when the level of the low-voltage power domain is a low level to pull down the node Q2 to a low level.

11. A low power consumption level shifter for ultra-wide range voltage conversion as recited in claim 9 or 5, wherein said level output module comprises a transistor P7 and a transistor N7;

a first pole of the transistor P7 is connected to a high level of the high voltage power supply domain, a control pole is connected to the node Q1, a second pole is connected to a first pole of the transistor N7, a second pole of the transistor N7 is connected to a ground potential, and a control pole is connected to the node Q3, when the node Q1 is a high level of the high voltage power supply domain, the transistor N7 is turned on, so that a node between the transistor P7 and the transistor N7 outputs a low level, and when the node Q3 is a low level, the transistor P7 is turned on, so that a node between the transistor P7 and the transistor N7 outputs a high level of the high voltage power supply domain.

12. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 9, wherein said voltage dropping unit comprises a transistor N8, a first pole of said transistor N8 being connected to a control pole thereof, a first output terminal and a second control terminal of a complementary pull-up circuit, respectively, to form a node Q1, a second pole of said transistor N8 being connected to a first output terminal of a pull-down unit to form a node Q3;

or, the voltage drop unit includes a resistor, a first end of the resistor is connected to the first output end and the second control end of the complementary pull-up circuit, respectively, to form a node Q1, and a second end of the resistor is connected to the first output end of the pull-down unit, to form a node Q3;

or, the voltage drop unit includes a diode, anodes of the diodes are respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and a cathode of the diode is connected to the first output terminal of the pull-down unit to form a node Q3.

13. A low power consumption level shifter for ultra-wide range voltage conversion as recited in claim 8 or 10, wherein said second charging circuit comprises a second current mirror circuit, transistor N5 and transistor N6;

a first output end of the second current mirror circuit is connected with a first pole of a transistor N5, a second output end of the second current mirror circuit is connected with a node Q1, a second pole of the transistor N5 is connected with a first pole of a transistor N6, a second pole of the transistor N6 is used for inputting the level of a low-voltage power supply domain, a control pole of the transistor N5 is connected with a node Q2, and a control pole of the transistor N6 is connected with the high level of the low-voltage power supply domain;

14. A low power consumption level converter for ultra-wide range voltage conversion as recited in claim 13, wherein said second current mirror circuit comprises a transistor P5 and a transistor P6;

first poles of the transistors P5 and P6 are both connected to a high level of the high voltage power supply domain, a second pole of the transistor P6 is connected to a control pole thereof, a control pole of the transistor P5 and a first pole of the transistor N5, respectively, a second pole of the transistor P5 is connected to the node Q1, when the transistors N5 and N6 are both turned on, the transistors P5 and P6 are also turned on, and a current is output to the node Q1 through the second pole of the transistor P5.

15. A low power consumption level shifter for ultra-wide range voltage conversion as recited in claim 1 or 8, wherein said complementary pull-up circuit comprises a transistor P3 and a transistor P4;

first poles of the transistors P3 and P4 are both connected to a high level of the high voltage power supply domain, a second pole of the transistor P3 and a control pole of the transistor P4 are connected to a first output end of the pull-down circuit to form a node Q1, and a control pole of the transistor P3 and a second pole of the transistor P4 are connected to a second output end of the pull-down circuit to form a node Q2;

the transistor P4 is configured to be turned on when the node Q1 is low to pull up the node Q2 to a high level of a high voltage power supply domain, and the transistor P3 is configured to be turned on when the node Q2 is low to pull up the node Q1 to a high level of the high voltage power supply domain.

16. A low power consumption level shifter for ultra-wide range voltage conversion as recited in claim 1 or 8, wherein said first charging circuit comprises a first current mirror circuit, a transistor N1 and a transistor N2;

a first output end of the first current mirror circuit is connected with a first pole of a transistor N1, a second output end of the first current mirror circuit is connected with a node Q2, a second pole of the transistor N1 is connected with a first pole of a transistor N2, a second pole of the transistor N2 is connected with a ground potential, a control pole of the transistor N1 is connected with the node Q1, and a control pole of the transistor N2 is used for inputting the level of the low-voltage power supply domain;

the transistor N2 is used for being conducted when the level of a low-voltage power domain is high level, the transistor N1 is used for being conducted when the node Q1 is high level, the first current mirror circuit is used for outputting current to the node Q2 through the second output end when the transistor N1 and the transistor N2 are both conducted until the potential of the node Q1 is pulled to low level by the pull-down circuit, and therefore the transistor N1 is cut off.

17. A low power consumption level converter for ultra-wide range voltage conversion as recited in claim 16, wherein said first current mirror circuit comprises a transistor P1 and a transistor P2;

first poles of the transistors P1 and P2 are both connected to a high level of the high voltage power supply domain, a second pole of the transistor P1 is connected to a control pole thereof, a control pole of the transistor P2 and a first pole of the transistor N1, respectively, a second pole of the transistor P2 is connected to the node Q2, and when the transistors N1 and N2 are both turned on, the transistors P1 and P2 are also turned on, and output a current to the node Q2 through the second pole of the transistor P2.

18. A low power consumption level shifter for ultra-wide range voltage conversion, as recited in claim 1 or 8, wherein said level output module comprises an inverting unit;

the power supply end of the phase-inverting unit is connected with a high level of a high-voltage power supply domain, the input end of the phase-inverting unit is connected with a node Q1, the output end of the phase-inverting unit is used for outputting the level of the high-voltage power supply domain, and the phase-inverting unit is used for outputting the type of the level of the node Q1 after inverting;

or the input end of the inverting unit is connected with the node Q2, the output end of the inverting unit is used for outputting the level of the high-voltage power supply domain, and the inverting unit is used for outputting the level of the node Q2 after twice inversion.