CN114172509A - Pure depletion type logic circuit based on compound and composite logic circuit - Google Patents
Pure depletion type logic circuit based on compound and composite logic circuit Download PDFInfo
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Abstract
A pure depletion type logic circuit and a composite logic circuit based on a compound belong to the field of semiconductors, an input signal is accessed through a level conversion circuit, and the input signal is subjected to voltage division and level shift to output a first logic signal; the inverting circuit inverts the first logic signal based on the depletion mode HEMT transistor to output a second logic signal; the inverting circuit is powered by a single power supply; the peripheral power supply circuit of the compound-based pure depletion type logic circuit is simplified.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a pure depletion type logic circuit and a composite logic circuit based on a compound.
Background
In a microwave integrated circuit, a control logic circuit is an indispensable unit circuit and is used for realizing digital logic control functions such as on-off of a switch, attenuation/phase shift switching and the like. Compound-based High Electron Mobility Transistor (HEMT) Transistors and Metal Semiconductor Field Effect Transistors (MESFETs) have the remarkable characteristics of High characteristic frequency, High switching speed, good noise performance, High output power and the like, and are widely applied.
Related compound-based pure depletion mode logic circuits as shown in fig. 1, a first diode D1, a second diode D2 and a third diode D3 are connected in series in phase in sequence, the positive electrode of the first diode D1 is connected to an input signal, the negative electrode of the third diode D3 is connected to the drain of the third depletion mode MESFET transistor M3 and the gate of the first depletion mode MESFET transistor M1, the source of the third depletion mode MESFET transistor M3 and the gate of the third depletion mode MESFET transistor M3 are connected to a negative voltage power supply Vss, the drain of the first depletion mode MESFET transistor M1, the source of the second depletion mode MESFET transistor M2 and the gate of the second depletion mode MESFET transistor M2 are used together as an output terminal of the pure depletion mode logic circuit, the drain of the second depletion mode MESFET transistor M2 is connected to a positive voltage power supply, and the source of the first depletion mode MESFET transistor M1 is connected to a power supply ground. It follows that the related compound-based pure depletion logic circuits require dual power supplies, resulting in complex peripheral power supply circuits.
Disclosure of Invention
The present application aims to provide a compound-based pure depletion logic circuit and a composite logic circuit, and aims to solve the problem of complex peripheral power supply circuit of the related compound-based pure depletion logic circuit.
The embodiment of the application provides a pure depletion type logic circuit based on a compound, which comprises:
the level conversion circuit is configured to access an input signal, and perform voltage division and level shift on the input signal to output a first logic signal;
an inverting circuit connected to the level conversion circuit and configured to invert the first logic signal based on a depletion mode HEMT transistor to output a second logic signal; the inverting circuit is powered by a single power supply.
In one embodiment, the single power supply is a positive voltage power supply, the inverter circuit is connected with the positive voltage power supply, and the positive voltage power supply is configured to provide a positive voltage;
the inverting circuit is specifically configured to invert the first logic signal according to the positive voltage based on the depletion mode HEMT transistor to output the second logic signal.
In one embodiment, the inverter circuit includes a first load, a first depletion mode HEMT transistor, a first diode, and a first resistor;
a first end of the first resistor is used as an input end of the inverter circuit and is connected with the level conversion circuit so as to input the first logic signal;
the second end of the first resistor is connected with the grid electrode of the first depletion mode HEMT transistor, the source electrode of the first depletion mode HEMT transistor is connected with the anode of the first diode, and the cathode of the first diode is connected with the power ground;
the drain electrode of the first depletion type HEMT transistor and the first end of the first load are jointly used as the output end of the inverter circuit to output the second logic signal;
and the second end of the first load is used as a positive voltage input end of the inverter circuit and is connected with the positive voltage power supply to input the positive voltage.
In one embodiment, the level shift circuit includes n first level shift elements, a second resistor, and a third resistor;
the n first level shifting elements are connected in series in phase in sequence; n is a positive integer;
the anode of the 1 st first level shift element is used as an input signal input end of the level shift circuit to access the input signal;
the negative electrode of the nth first level shift element is connected with the first end of the second resistor;
the second end of the second resistor and the first end of the third resistor are jointly used as a first logic signal output end of the level conversion circuit and connected with the inverter circuit so as to output the first logic signal;
and the second end of the third resistor is connected with the power ground.
In one embodiment, the first level-shifting element comprises a compound-based diode and/or a compound-based HEMT transistor;
when the first level-shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted with the source of the compound-based HEMT transistor as the negative electrode of the first level-shifting element, and the gate of the compound-based HEMT transistor as the positive electrode of the first level-shifting element.
In one embodiment, the single power supply is a negative voltage power supply, the inverter circuit and the level conversion circuit are both connected with the negative voltage power supply, and the negative voltage power supply is configured to provide a negative voltage;
the inverting circuit is specifically configured to invert the first logic signal according to the negative voltage based on the depletion mode HEMT transistor to output the second logic signal;
the level shift circuit is specifically configured to access the input signal and the negative voltage, and perform voltage division and level shift on the input signal according to the negative voltage to output the first logic signal.
In one embodiment, the inverter circuit includes a second load, a second depletion mode HEMT transistor, a third diode, and a fourth resistor;
a first end of the fourth resistor is used as an input end of the inverter circuit and is connected with the level conversion circuit so as to input the first logic signal;
a second end of the fourth resistor is connected with a grid electrode of the second depletion mode HEMT transistor, and a source electrode of the second depletion mode HEMT transistor is connected with the anode of the third diode;
the negative electrode of the third diode is used as a negative voltage input end of the inverter circuit and is connected with a negative voltage power supply to access negative voltage;
the drain electrode of the second depletion mode HEMT transistor and the first end of the second load are jointly used as the output end of the inverter circuit to output the second logic signal;
the second terminal of the second load is connected to a power ground.
In one embodiment, the level shift circuit includes n second level shift elements, a fifth resistor, and a sixth resistor;
the n second level shifting elements are connected in series in phase in sequence; n is a positive integer;
the anode of the 1 st second level shift element is used as an input signal input end of the level shift circuit to access the input signal;
the negative electrode of the nth second level shift element is connected with the first end of the fifth resistor;
a second end of the fifth resistor and a first end of the sixth resistor are used as a first logic signal output end of the level shift circuit together, and are connected with the inverter circuit to output the first logic signal;
and the second end of the sixth resistor is used as a negative voltage input end of the level conversion circuit and is connected with the negative voltage power supply so as to be connected with the negative voltage.
In one embodiment, the second level-shifting element comprises a compound-based diode and/or a compound-based HEMT transistor;
when the second level-shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted with the source of the compound-based HEMT transistor as the negative electrode of the second level-shifting element, and the gate of the compound-based HEMT transistor as the positive electrode of the second level-shifting element.
In one embodiment, the compound comprises GaAs, GaN, and InP.
Embodiments of the present application also provide an inverter including an odd number of cascaded pure compound-based depletion mode logic circuits as described above.
Embodiments of the present application also provide a follower including an even number of cascaded compound-based pure depletion mode logic circuits as described above.
The embodiment of the present application further provides a composite logic circuit, which includes a first logic circuit, a second logic circuit, and a third logic circuit, wherein an output end of the first logic circuit is connected to an input end of the second logic circuit and an input end of the third logic circuit, and an input end of the first logic circuit is connected to the input signal;
the first logic circuit comprises K cascaded pure depletion type logic circuits based on the compound;
the second logic circuit comprises L cascaded pure depletion type logic circuits based on the compound;
the third logic circuit comprises M cascaded pure depletion type logic circuits based on the compound;
wherein the sum of K and L is an odd number; the sum of K and M is an even number; the K, the L and the M are all positive integers.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the level conversion circuit is connected with an input signal, and performs voltage division and level displacement on the input signal to output a first logic signal; the inverting circuit inverts the first logic signal based on the depletion mode HEMT transistor to output a second logic signal, and the inverting circuit is powered by a single power supply; the peripheral power supply circuit of the compound-based pure depletion type logic circuit is simplified.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is an exemplary circuit schematic of a related art compound-based pure depletion mode logic circuit;
FIG. 2 is a schematic diagram of a compound-based pure depletion logic circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another structure of a compound-based pure depletion logic circuit according to an embodiment of the present application;
FIG. 4 is an exemplary circuit schematic of a compound-based pure depletion mode logic circuit provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of another structure of a compound-based pure depletion logic circuit according to an embodiment of the present application;
FIG. 6 is another exemplary circuit schematic of a compound-based pure depletion mode logic circuit provided by an embodiment of the present application;
fig. 7 is a schematic structural diagram of a complex logic circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 2 shows a schematic structure diagram of a compound-based pure depletion logic circuit provided in a preferred embodiment of the present application, and for convenience of illustration, only the parts related to this embodiment are shown, which are detailed as follows:
the above-described compound-based pure depletion type logic circuit includes a level conversion circuit 11 and an inverter circuit 12.
The level shift circuit 11 is configured to access an input signal, and divide and level shift the input signal to output a first logic signal.
An inverting circuit 12 connected to the level conversion circuit 11 and configured to invert the first logic signal based on the depletion mode HEMT transistor to output a second logic signal; the inverter circuit 12 is powered by a single power supply.
In a specific implementation, the inverting circuit 12 is configured to invert and amplify the first logic signal based on the depletion mode HEMT transistor to output the second logic signal.
By way of example, and not limitation, compounds include GaAs, GaN, and InP.
In a specific implementation, as shown in fig. 3, the single power supply is a positive voltage power supply VDD, and the inverter circuit 12 may be connected to the positive voltage power supply VDD only, where the positive voltage power supply VDD is configured to provide a positive voltage; the inverting circuit 12 is specifically configured to invert the first logic signal according to the positive voltage based on the depletion mode HEMT transistor to output the second logic signal.
The second logic signal output according to the positive voltage is a positive voltage signal, so that the compound-based pure depletion type logic circuit connected to the positive voltage power supply VDD can be used to construct various logic gate circuits, and can also be used as a control circuit for driving a compound-based switching device and/or can be used as a gate driving circuit for an active transistor in an active circuit.
Fig. 4 shows an exemplary circuit structure of a compound-based pure depletion logic circuit provided by an embodiment of the present invention, and for convenience of illustration, only the parts related to the embodiment of the present invention are shown, which are detailed as follows:
the inverter circuit 12 includes a first load X1, a first depletion mode HEMT transistor M1, a first diode D1, and a first resistor R1;
a first end of the first resistor R1, serving as an input end of the inverter circuit 12, is connected to the level shifter circuit 11 to input a first logic signal; a second end of the first resistor R1 is connected to the gate of the first depletion mode HEMT transistor M1, the source of the first depletion mode HEMT transistor M1 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the power ground; the drain of the first depletion mode HEMT transistor M1 and the first terminal of the first load X1 function together as an output terminal of the inverter circuit 12 to output a second logic signal; a second terminal of the first load X1 serves as a positive voltage input terminal of the inverter circuit 12, and is connected to the positive voltage power supply VDD to input a positive voltage.
The first load X1 may have two embodiments, the first embodiment is shown in fig. 4, and includes a third depletion mode HEMT transistor M3 and a seventh resistor R7; the gate of the third depletion mode HEMT transistor M3 and the first terminal of the seventh resistor R7 together serve as the first terminal of the first load X1, the source of the third depletion mode HEMT transistor M3 is connected to the second terminal of the seventh resistor R7, and the drain of the third depletion mode HEMT transistor M3 serves as the second terminal of the first load X1. The second embodiment comprises only the first load resistor Rz1 (not shown in this embodiment).
Since the choke device (the first resistor R1) is provided, power consumption is small and the first depletion type HEMT transistor M1 is protected.
The level shift circuit 11 includes n first level shift elements D2, a second resistor R2, and a third resistor R3.
The n first level shift elements D2 are connected in series in phase; n is a positive integer; the positive electrode of the 1 st first level shift element is used as an input signal input end of the level conversion circuit 11 to access an input signal; the negative pole of the nth first level shift element is connected with the first end of the second resistor R2; a second terminal of the second resistor R2 and a first terminal of the third resistor R3 are commonly used as a first logic signal output terminal of the level shift circuit 11, and are connected to the inverter circuit 12 to output a first logic signal; a second terminal of the third resistor R3 is connected to power ground. In a specific implementation, the arrangement order of the second resistor R2 and the n first level shift elements D2 may also be determined according to design requirements.
Since the choke devices (the second resistor R2 and the third resistor R3) are provided, power consumption can be optimized by adjusting the resistance of the second resistor R2 and the resistance of the third resistor R3.
The first level shifting element D2 includes a compound based diode and/or a compound based HEMT transistor.
When the first level-shifting element D2 includes a compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted to the source of the compound-based HEMT transistor as the cathode of the first level-shifting element D2, and the gate of the compound-based HEMT transistor as the anode of the first level-shifting element D2.
The description of fig. 4 is further described below in conjunction with the working principle:
the first logic voltage is a voltage VA at the node a, and when Vin is greater than or equal to n × Von, the voltage VA at the node a satisfies the following formula:
VA ═ v (Vin-n × Von) × R3/(R2+ R3), where Von is the on voltage of the first level shifting element D2 and n is a positive integer; vin is the voltage of the input signal.
Since the current flowing through the first resistor R1 is small, the voltage VB at the node B is approximately equal to the voltage VA at the node a; therefore, the voltage transmission characteristics of the inverter circuit are as follows: when the voltage VA at the node a increases, when it is larger than the sum of the threshold voltage of the first depletion mode HEMT transistor M1 and the on voltage of the first diode D1, the first depletion mode HEMT transistor M1 and the first diode D1 are simultaneously turned on, and the voltage of the second logic signal Vout1 output by the inverter circuit 12 starts to fall. When the voltage VA at the node a is gradually increased after being greater than the turning point, the voltage of the second logic signal Vout1 output from the inverter circuit 12 gradually approaches the turn-on voltage (low level) of the first diode D1.
For example, the positive voltage VDD is 3.3V, the number of the first level shifter D2 is 1, the first resistor R1 is 384 ohms, the second resistor R2 is 4921 ohms, the third resistor R3 is 9780 ohms, the seventh resistor R7 is 257 ohms, and the circuit design parameters are as follows:
when the input signal Vin is high, such as 3.3V, the voltage VA at the node a is 1.518V, the voltage VB at the node B is 1.518V, and the second logic signal Vout1 is 1.141V, so that the low-level output is realized.
When the input signal Vin is at a low level, such as 0V, the voltage VA at the node a is 0V, the voltage VB at the node B is 0V, and the second logic signal Vout1 is 3.276V, so as to realize a high level output.
It should be noted that when the output signal Vout1 of the first depletion mode HEMT transistor M1 drops by 10%, the voltage VA at the node a is about 0.4V, and the noise tolerance is low, so that the noise tolerance is improved by providing n first level shift elements D2, and the adjustable turning point of the input signal is realized by setting the voltage division ratio of the second resistor R2 and the third resistor R3.
When Vin is smaller than n × Von, VA is 0V, and the output signal Vout1 of the inverter circuit is at high level.
It should be noted that the input signal of the embodiment of the present application is compatible with the TTL signal, the high level of the input signal is a TTL high level, and the low level of the input signal is a TTL low level; the low level of the second logic signal Vout1 is the turn-on voltage of the first diode D1, and the high level of the second logic signal Vout1 is a positive voltage close to VDD.
In a specific implementation, as shown in fig. 5, the single power supply is a negative voltage power supply Vss, and both the inverter circuit 12 and the level shifter circuit 11 may be connected to the negative voltage power supply Vss only, and the negative voltage power supply Vss is configured to provide a negative voltage; the inverter circuit 12 is specifically configured to invert the first logic signal according to the negative voltage based on the depletion mode HEMT transistor to output the second logic signal. The level shift circuit 11 is specifically configured to access the input signal and the negative voltage, and divide the input signal and perform level shift according to the negative voltage to output a first logic signal.
The second logic signal output according to the negative voltage is a negative voltage signal, so that the compound-based pure depletion type logic circuit connected to the negative voltage power supply Vss can be used to construct various logic circuits, and can also be used as a control circuit for driving a compound-based switching device and/or can be used as a gate drive circuit for an active transistor in an active circuit.
Fig. 6 shows another exemplary circuit structure of a compound-based pure depletion logic circuit provided in an embodiment of the present invention, and for convenience of illustration, only the portions related to the embodiment of the present invention are shown, which is detailed as follows:
the inverter circuit 12 includes a second load X2, a second depletion mode HEMT transistor M2, a third diode D3, and a fourth resistor R4.
A first end of the fourth resistor R4, serving as an input end of the inverter circuit 12, is connected to the level shifter circuit 11 to input the first logic signal; a second end of the fourth resistor R4 is connected to the gate of the second depletion mode HEMT transistor M2, and the source of the second depletion mode HEMT transistor M2 is connected to the anode of the third diode D3; the negative electrode of the third diode D3 is used as the negative voltage input end of the inverter circuit 12, and is connected with the negative voltage power supply Vss to access the negative voltage; the drain of the second depletion mode HEMT transistor M2 and the first terminal of the second load X2 function together as the output terminal of the inverter circuit 12 to output a second logic signal; a second terminal of the second load X2 is connected to power ground.
The second load X2 may have two embodiments, the first embodiment is shown in fig. 6, and includes a fourth depletion mode HEMT transistor M4 and an eighth resistor R8; the gate of the fourth depletion mode HEMT transistor M4 and the first terminal of the eighth resistor R8 together serve as the first terminal of the second load X2, the source of the fourth depletion mode HEMT transistor M4 is connected to the second terminal of the eighth resistor R8, and the drain of the fourth depletion mode HEMT transistor M4 serves as the second terminal of the second load X2. The second embodiment comprises only the second load resistor Rz2 (not shown in this embodiment).
Since the choke device (the fourth resistor R4) is provided, it is possible to optimize power consumption and protect the second depletion mode HEMT transistor M2 by adjusting the resistance value of the fourth resistor R4.
The level shift circuit 11 includes n second level shift elements D4, a fifth resistor R5, and a sixth resistor R6.
The n second level shift elements D4 are connected in series in phase; n is a positive integer; the positive electrode of the 1 st second level shift element is used as an input signal input end of the level conversion circuit 11 to access an input signal; the negative pole of the nth second level shift element is connected with the first end of the fifth resistor R5; a second end of the fifth resistor R5 and a first end of the sixth resistor R6 are commonly used as a first logic signal output end of the level shift circuit 11, and are connected to the inverter circuit 12 to output a first logic signal; a second end of the sixth resistor R6 serves as a negative voltage input end of the level shift circuit 11, and is connected to the negative voltage power supply Vss to receive the negative voltage. In a specific implementation, the arrangement order of the fifth resistor R5 and the n second level shift elements D4 may also be determined according to design requirements.
Since the choke devices (the fifth resistor R5 and the sixth resistor R6) are provided, power consumption can be optimized by adjusting the resistance of the fifth resistor R5 and the resistance of the sixth resistor R6.
The second level shifting element D4 includes a compound based diode and/or a compound based HEMT transistor.
When the second level-shifting element D4 includes a compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted to the source of the compound-based HEMT transistor as the cathode of the second level-shifting element D4, and the gate of the compound-based HEMT transistor as the anode of the second level-shifting element D4.
The description of fig. 6 is further described below in conjunction with the working principle:
the first logic voltage is the voltage VC of the node C, and the voltage VC of the node C satisfies the following formula:
VC＝(Vin-n*Von-Vss)R6/(R5+R6)+Vss
wherein Von is the turn-on voltage of the second level shift element D4, Vss is the negative voltage, and n is a positive integer; vin is the voltage of the input signal.
Since the current flowing through the fourth resistor R4 is small, the voltage VD at the node D is approximately equal to the voltage VC at the node C.
The voltage transfer characteristics of the inverter circuit are as follows: when the voltage VC of the node C increases, when the voltage difference between the voltage VC and the negative voltage Vss is greater than the sum of the threshold voltage of the second depletion mode HEMT transistor M2 and the turn-on voltage of the third diode D3, the second depletion mode HEMT transistor M2 and the third diode D3 are simultaneously turned on, and the voltage of the second logic signal Vout2 output by the inverter circuit 12 starts to drop. When the voltage VC of the node C gradually increases after being greater than the turning point, the voltage of the second logic signal Vout2 output from the inverter circuit 12 gradually approaches the sum (low level) of the turn-on voltage of the third diode D3 and the negative voltage Vss.
When (Vin-Vss) is smaller than n × Von, VC is Vss, and the output signal Vout2 of the inverter circuit is high (about 0V).
It should be noted that the input signal of the embodiment of the present application is compatible with the TTL signal, the voltage of the low level of the second logic signal Vout2 is the sum of the turn-on voltage of the third diode D3 and the negative voltage Vss (the voltage of the low level of the second logic signal Vout2 is a negative voltage value), and the voltage of the high level of the second logic signal Vout2 is about 0V.
For example, the negative voltage Vss is-4V, the number of the second level-shifting elements D4 is 4, the number of the fourth resistor R4 is 384 ohms, the number of the fifth resistor R5 is 1464 ohms, the number of the sixth resistor R6 is 5731 ohms, the number of the eighth resistor R8 is 257 ohms, and the circuit design parameters are as follows:
when the input signal Vin is at a high level, such as 3.3V, the voltage VC at the node C is-3.1V, the voltage VD at the node D is-3.1V, and the second logic signal Vout2 is-2.84V, thereby realizing low-level output.
When the input signal Vin is at a low level, such as 0V, the voltage VC at the node C is-3.9V, the voltage VD at the node D is-3.9V, and the second logic signal Vout2 is-0.1V, thereby realizing high-level output.
It should be noted that when the output signal of the second depletion mode HEMT transistor M2 drops by 10%, the input signal is about 1V, and the voltage VC at the node C is about-3.6V, so that the n second level shift elements D4 are provided to adapt the level of the TTL signal, and the fifth resistor R5 and the sixth resistor R6 are provided to adjust the turning point of the input signal.
The embodiment of the application also provides an inverter, and the inverter comprises an odd number of cascaded pure depletion type logic circuits based on the compound.
Embodiments of the present application also provide a follower including an even number of cascaded compound-based pure depletion mode logic circuits as described above.
The embodiment of the present application further provides a composite logic circuit, as shown in fig. 7, which includes a first logic circuit 10, a second logic circuit 20, and a third logic circuit 30, where an output end of the first logic circuit 10 is connected to an input end of the second logic circuit 20 and an input end of the third logic circuit 30, and an input end of the first logic circuit 10 is connected to an input signal.
The first logic circuit 10 includes K cascaded pure compound-based depletion type logic circuits described above; the second logic circuit 20 includes L cascaded pure depletion type logic circuits based on the above-described compound; the third logic circuit 30 includes M cascaded pure compound-based depletion type logic circuits described above; wherein the sum of K and L is an odd number; the sum of K and M is an even number; K. l and M are positive integers.
The composite logic circuit can not only invert the input signal, but also follow the input signal, thereby enriching the functions of the composite logic circuit. And through a plurality of cascaded pure depletion type logic circuits based on the compound, the transition time of inversion and following is reduced (the time of a rising edge and the time of a falling edge are reduced), and the response speed of inversion and following is improved.
The embodiment of the invention accesses an input signal through a level conversion circuit, and performs voltage division and level displacement on the input signal to output a first logic signal; the inverting circuit inverts the first logic signal based on the depletion mode HEMT transistor to output a second logic signal; the inverting circuit is powered by a single power supply; the peripheral power supply circuit of the compound-based pure depletion type logic circuit is simplified.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (13)
1. A compound-based pure depletion mode logic circuit, comprising:
the level conversion circuit is configured to access an input signal, and perform voltage division and level shift on the input signal to output a first logic signal;
an inverting circuit connected to the level conversion circuit and configured to invert the first logic signal based on a depletion mode HEMT transistor to output a second logic signal; the inverting circuit is powered by a single power supply.
2. The compound-based pure depletion mode logic circuit according to claim 1, wherein the single power supply is a positive voltage power supply, the inverter circuit is connected to the positive voltage power supply, and the positive voltage power supply is configured to provide a positive voltage;
the inverting circuit is specifically configured to invert the first logic signal according to the positive voltage based on the depletion mode HEMT transistor to output the second logic signal.
3. The compound-based pure depletion mode logic circuit according to claim 2, wherein the inverter circuit includes a first load, a first depletion mode HEMT transistor, a first diode, and a first resistor;
a first end of the first resistor is used as an input end of the inverter circuit and is connected with the level conversion circuit so as to input the first logic signal;
the second end of the first resistor is connected with the grid electrode of the first depletion mode HEMT transistor, the source electrode of the first depletion mode HEMT transistor is connected with the anode of the first diode, and the cathode of the first diode is connected with the power ground;
the drain electrode of the first depletion type HEMT transistor and the first end of the first load are jointly used as the output end of the inverter circuit to output the second logic signal;
and the second end of the first load is used as a positive voltage input end of the inverter circuit and is connected with the positive voltage power supply to input the positive voltage.
4. The compound-based pure depletion mode logic circuit according to claim 2, wherein the level shift circuit comprises n first level-shifting elements, a second resistor, and a third resistor;
the n first level shifting elements are connected in series in phase in sequence; n is a positive integer;
the anode of the 1 st first level shift element is used as an input signal input end of the level shift circuit to access the input signal;
the negative electrode of the nth first level shift element is connected with the first end of the second resistor;
the second end of the second resistor and the first end of the third resistor are jointly used as a first logic signal output end of the level conversion circuit and connected with the inverter circuit so as to output the first logic signal;
and the second end of the third resistor is connected with the power ground.
5. The compound-based pure depletion mode logic circuit according to claim 4, wherein the first level-shifting element comprises a compound-based diode and/or a compound-based HEMT transistor;
when the first level-shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted with the source of the compound-based HEMT transistor as the negative electrode of the first level-shifting element, and the gate of the compound-based HEMT transistor as the positive electrode of the first level-shifting element.
6. The compound-based pure depletion mode logic circuit according to claim 1, wherein the single power supply is a negative voltage power supply, the inverting circuit and the level shifting circuit are both connected to the negative voltage power supply, and the negative voltage power supply is configured to supply a negative voltage;
the inverting circuit is specifically configured to invert the first logic signal according to the negative voltage based on the depletion mode HEMT transistor to output the second logic signal;
the level shift circuit is specifically configured to access the input signal and the negative voltage, and perform voltage division and level shift on the input signal according to the negative voltage to output the first logic signal.
7. The compound-based pure depletion mode logic circuit according to claim 6, wherein the inverting circuit includes a second load, a second depletion mode HEMT transistor, a third diode, and a fourth resistor;
a first end of the fourth resistor is used as an input end of the inverter circuit and is connected with the level conversion circuit so as to input the first logic signal;
a second end of the fourth resistor is connected with a grid electrode of the second depletion mode HEMT transistor, and a source electrode of the second depletion mode HEMT transistor is connected with the anode of the third diode;
the negative electrode of the third diode is used as a negative voltage input end of the inverter circuit and is connected with a negative voltage power supply to access negative voltage;
the drain electrode of the second depletion mode HEMT transistor and the first end of the second load are jointly used as the output end of the inverter circuit to output the second logic signal;
the second terminal of the second load is connected to a power ground.
8. The compound-based pure depletion mode logic circuit according to claim 6, wherein the level shift circuit comprises n second level-shifting elements, a fifth resistor, and a sixth resistor;
the n second level shifting elements are connected in series in phase in sequence; n is a positive integer;
the anode of the 1 st second level shift element is used as an input signal input end of the level shift circuit to access the input signal;
the negative electrode of the nth second level shift element is connected with the first end of the fifth resistor;
a second end of the fifth resistor and a first end of the sixth resistor are used as a first logic signal output end of the level shift circuit together, and are connected with the inverter circuit to output the first logic signal;
and the second end of the sixth resistor is used as a negative voltage input end of the level conversion circuit and is connected with the negative voltage power supply so as to be connected with the negative voltage.
9. The compound-based pure depletion mode logic circuit according to claim 8, wherein the second level-shifting element comprises a compound-based diode and/or a compound-based HEMT transistor;
when the second level-shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted with the source of the compound-based HEMT transistor as the negative electrode of the second level-shifting element, and the gate of the compound-based HEMT transistor as the positive electrode of the second level-shifting element.
10. The compound-based pure depletion mode logic circuit according to claim 1, wherein the compound comprises GaAs, GaN, and InP.
11. An inverter, characterized in that it comprises an odd number of cascaded pure compound-based depletion mode logic circuits according to any of claims 1 to 10.
12. A follower, characterized in that it comprises an even number of cascaded pure compound-based depletion mode logic circuits according to any of claims 1 to 10.
13. A composite logic circuit is characterized by comprising a first logic circuit, a second logic circuit and a third logic circuit, wherein the output end of the first logic circuit is connected with the input end of the second logic circuit and the input end of the third logic circuit, and the input end of the first logic circuit is connected with an input signal;
the first logic circuit comprises K cascaded pure compound-based depletion mode logic circuits according to any one of claims 1 to 10;
the second logic circuit comprises L cascaded pure compound-based depletion mode logic circuits according to any one of claims 1 to 10;
the third logic circuit comprises M cascaded pure compound-based depletion mode logic circuits according to any one of claims 1 to 10;
wherein the sum of K and L is an odd number; the sum of K and M is an even number; the K, the L and the M are all positive integers.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111676412.3A CN114172509A (en) | 2021-12-31 | 2021-12-31 | Pure depletion type logic circuit based on compound and composite logic circuit |
| PCT/CN2022/144171 WO2023125978A1 (en) | 2021-12-31 | 2022-12-30 | Logic circuit, phase inverter, follower, and composite logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111676412.3A CN114172509A (en) | 2021-12-31 | 2021-12-31 | Pure depletion type logic circuit based on compound and composite logic circuit |
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| Publication Number | Publication Date |
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| CN114172509A true CN114172509A (en) | 2022-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111676412.3A Pending CN114172509A (en) | 2021-12-31 | 2021-12-31 | Pure depletion type logic circuit based on compound and composite logic circuit |
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| Country | Link |
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| CN (1) | CN114172509A (en) |
| WO (1) | WO2023125978A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114710149A (en) * | 2022-04-22 | 2022-07-05 | 西安微电子技术研究所 | Full N-channel depletion type D latch based on feedback type level conversion technology |
| WO2023125978A1 (en) * | 2021-12-31 | 2023-07-06 | 深圳市晶准通信技术有限公司 | Logic circuit, phase inverter, follower, and composite logic circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2795049B2 (en) * | 1992-05-14 | 1998-09-10 | 日本電気株式会社 | Logic circuit |
| JP2000165227A (en) * | 1998-11-26 | 2000-06-16 | Hitachi Ltd | Logical output circuit |
| JP5590257B2 (en) * | 2012-02-07 | 2014-09-17 | 株式会社村田製作所 | Level conversion circuit and logic circuit with level conversion function |
| CN104682967B (en) * | 2015-01-30 | 2018-12-14 | 天津中科海高微波技术有限公司 | GaAs logic unit and its serial-parallel conversion circuit based on differential configuration |
| CN114172509A (en) * | 2021-12-31 | 2022-03-11 | 深圳市晶准通信技术有限公司 | Pure depletion type logic circuit based on compound and composite logic circuit |
| CN217508742U (en) * | 2022-05-24 | 2022-09-27 | 深圳市晶准通信技术有限公司 | Composite logic gate circuit, chip comprising same and electronic device |
-
2021
- 2021-12-31 CN CN202111676412.3A patent/CN114172509A/en active Pending
-
2022
- 2022-12-30 WO PCT/CN2022/144171 patent/WO2023125978A1/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023125978A1 (en) * | 2021-12-31 | 2023-07-06 | 深圳市晶准通信技术有限公司 | Logic circuit, phase inverter, follower, and composite logic circuit |
| CN114710149A (en) * | 2022-04-22 | 2022-07-05 | 西安微电子技术研究所 | Full N-channel depletion type D latch based on feedback type level conversion technology |
| CN114710149B (en) * | 2022-04-22 | 2024-05-07 | 西安微电子技术研究所 | All-N-channel depletion type D latch based on feedback type level conversion technology |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023125978A1 (en) | 2023-07-06 |
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