CN217508742U

CN217508742U - Composite logic gate circuit, chip comprising same and electronic device

Info

Publication number: CN217508742U
Application number: CN202221264684.2U
Authority: CN
Inventors: 刘石生
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-05-24
Filing date: 2022-05-24
Publication date: 2022-09-27
Anticipated expiration: 2032-05-24

Abstract

A composite logic gate circuit comprises a driving circuit and is provided with a signal output end and K signal input ends, the first end of the driving circuit is connected to the signal output end of the composite logic gate circuit and is connected to a high-level power supply through a load circuit, the second end of the driving circuit is connected to a low-level power supply, the driving circuit comprises K first depletion type HEMT devices and L clamping devices, the K first depletion type HEMT devices are arranged into M clamping units, the L clamping devices are arranged into M clamping units, each clamping unit corresponds to one clamping unit, M and L are positive integers, and K is an integer larger than or equal to 2. According to the embodiment of the application, the depletion type field effect transistor based on the compound semiconductor substrate is used for constructing the composite logic gate circuit, the performance density and the function density of a high-end radio frequency system of a compound hybrid circuit can be improved, and the method is beneficial to reducing the cost and improving the reliability.

Description

Composite logic gate circuit, chip comprising same and electronic device

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to a composite logic gate circuit, a chip comprising the same and an electronic device.

Background

The existing high-performance radio frequency or microwave millimeter wave devices or circuits mostly adopt compound devices as cores. For example, a high-performance switch in mobile communication equipment adopts a GaAs pHEMT process, a high-performance power amplifier adopts a GaAs pHEMT process, a power amplifier and a switch of a 5G base station mostly adopt a GaN HEMT, a high-end high-frequency instrument mostly adopts an InP pHEMT process device or a chip as a core device, and a high-performance radar system also mainly adopts a GaAs depletion type pHEMT or GaN depletion type HEMT and the like as a core radio frequency device. With the development of civil high-frequency mobile communication, internet of vehicles and large satellite constellations, radio frequency systems are developing towards higher performance density, higher functional integration level and more flexibility.

However, in the prior art, the driving control for compound devices or circuits (e.g., controlling the gate voltage of a fet in a switching circuit or the gate voltage of a fet in an amplifier) is usually based on additional Si-based or GeSi BiCMOS chips or circuits, which requires high cost packaging techniques and more complex process flow. In addition, since the compound and Si or GeSi have different material characteristics such as a thermal expansion coefficient, a variation tendency of a device with temperature, and the like, it is difficult to achieve improvement of both performance density and function density. The high cost, system complexity, etc. brought by the control of the rf circuit based on the compound device are becoming short boards that affect the development of its application.

Therefore, it is advantageous to find a function of integrated driving or control based on a high-performance radio frequency or microwave/millimeter wave compound device to solve the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a composite logic gate circuit, a chip comprising the same and an electronic device.

According to an aspect, an embodiment of the present application provides a complex logic gate circuit, including a driving circuit, and having a signal output terminal and K signal input terminals, a first terminal of the driving circuit being connected to the signal output terminal of the complex logic gate circuit and to a high-level power supply through a load circuit, and a second terminal of the driving circuit being connected to a low-level power supply, wherein the first terminal of the load circuit is connected to the first terminal of the driving circuit and the signal output terminal of the complex logic gate circuit, and the second terminal of the load circuit being connected to the high-level power supply, wherein the driving circuit includes K first depletion type HEMT devices arranged on a compound semiconductor substrate and arranged in M and structures, and L clamp devices arranged in M clamp units, wherein each corresponds to a clamping unit, M and L are positive integers, K is an integer greater than or equal to 2, wherein:

each AND structure comprises one or more first depletion mode HEMT devices, wherein the 1 st to Mth AND structures respectively comprise K ₁ 、……、K _M A first depletion mode HEMT device, K ₁ 、……、K _M Are the same or different positive integers, K ₁ 、……、K _M The sum is equal to K;

the grid electrodes of the K first depletion mode HEMT devices correspond to the K signal input ends of the composite logic gate circuit one by one, and the grid electrode of each first depletion mode HEMT device in the K first depletion mode HEMT devices is connected to one corresponding signal input end in the K signal input ends;

in an and structure including a plurality of first depletion mode HEMT devices, the plurality of first depletion mode HEMT devices in the and structure are connected in series, wherein a drain of a first depletion mode HEMT device in the and structure is connected to a first end of the driving circuit, a source of a last first depletion mode HEMT device in the and structure is connected to a head end of a corresponding one of the clamping units, a drain of each other first depletion mode HEMT device in the and structure is connected to a source of a previous first depletion mode HEMT device in the and structure, and a source of each other first depletion mode HEMT device in the and structure is connected to a drain of a next first depletion mode HEMT device in the and structure; in the structure comprising a first depletion mode HEMT device, the drain electrode of the first depletion mode HEMT device is connected to the first end of the driving circuit, and the source electrode of the first depletion mode HEMT device is connected to the head end of a corresponding clamping unit;

each clamping unit comprises one or more clamping devices, each clamping device is provided with a first end and a second end, wherein the 1 st clamping deviceEach of the M-th clamping units comprises L ₁ 、……、L _M A clamping device, L ₁ 、……、L _M Are the same or different positive integers, L ₁ 、……、L _M The sum is equal to L;

in a clamping unit comprising a plurality of clamping devices, the plurality of clamping devices in the clamping unit are connected in series, wherein a first end of a first clamping device in the clamping unit serves as a head end of the clamping unit, a second end of a last clamping device in the clamping unit serves as a tail end of the clamping unit, a first end of each other clamping device in the clamping unit is connected to a second end of a previous clamping device in the clamping unit, a second end of each other clamping device in the clamping unit is connected to a first end of a next clamping device in the clamping unit, and the tail end of the clamping unit is connected to a second end of the driving circuit; in a clamping unit comprising one clamping device, a first end of the clamping device is used as a head end of the clamping unit, and a second end of the clamping device is used as a tail end of the clamping unit and is connected to a second end of the driving circuit.

According to another aspect, an embodiment of the present application provides a chip including a composite logic gate circuit as described in any one of the above embodiments.

According to yet another aspect, an electronic device is provided, which includes the chip according to any one of the above embodiments.

The embodiment of the application provides a composite logic gate circuit, a chip comprising the same and an electronic device, wherein the composite logic gate circuit uses a depletion type field effect transistor arranged on a compound semiconductor substrate, and the purposes of simple structure and small size are achieved. In addition, the depletion type field effect transistor of the compound semiconductor substrate is used for constructing the logic gate circuit, so that the logic gate circuit is convenient to integrate with a mainstream compound radio frequency circuit or a microwave/millimeter wave circuit, the performance density and the function density of a high-end radio frequency system of a compound mixed circuit can be improved, the cost is reduced, and the reliability is improved.

Drawings

In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive work.

FIG. 1 is a schematic diagram of a complex logic gate circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a composite logic gate circuit according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a driving circuit according to an embodiment of the present application;

FIGS. 4A-4D are schematic structural diagrams of a clamp unit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a level shift circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a load circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a nor gate logic circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a nand gate logic circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of an AND OR logic circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a chip according to an embodiment of the present application;

fig. 11 is a schematic view of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application more clearly apparent, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of some, and not restrictive, of the current application, and that these specific embodiments described herein are intended to be illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or be indirectly connected to the other element, for example, through a third element or a connecting medium such as a cable.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 is a schematic diagram of a composite logic gate circuit according to an embodiment of the present application. In this embodiment, the complex logic gate circuit 100 includes a driver circuit 1 and a load circuit 2, and has a signal output terminal P _out And K signal input terminals P _in-1 、……、P _in-K And K is an integer of 2 or more. The first terminal 10 of the driving circuit 1 is connected to the output terminal P _out And is connected to a high level power supply VH via a load circuit 2, wherein a first terminal 20 of the load circuit 2 is connected to a first terminal 10 of the driving circuit 1 and a signal output terminal P of the complex logic gate circuit 100 _out The second terminal 21 of the load circuit 2 is connected to a high level power supplyVH. The second terminal 11 of the driving circuit 1 is connected to a low level power supply, i.e. the low level power supply VL shown in fig. 1. Input signal at K signal input terminals P _in-1 、……、P _in-K Is connected to the driving circuit 1 via the ports 12-1, … …, 12-K, respectively, and is provided at the output terminal P _out Outputs an output signal. The complex logic gate circuit 100 has two or more signal inputs and constitutes multivariable boolean function logic and is therefore referred to as a complex logic gate circuit.

In some embodiments, the level of the input signal generated by the external signal source may not be suitable for the driving circuit 1, and cannot be directly input to the driving circuit 1, and a level conversion circuit needs to be added between the driving circuit 1 and the K signal input terminals to convert the input signal into a suitable input logic signal. Fig. 2 shows such an embodiment. As shown in fig. 2, the complex logic gate circuit 100 further comprises K level shifting circuits 3-1, … …, 3-K in one-to-one correspondence with the K signal inputs of the complex logic gate circuit (and the K ports 12-1, … …, 12-K of the driver circuit 1), wherein each level shifting circuit 3-i (i ═ 1, 2, … …, K) is connected to the corresponding port 12-i (i ═ 1, 2, … …, K) of the driver circuit 1 and to the corresponding signal input P _in-i (i-1, 2, … …, K) for converting the signal input to the signal input terminal into an input logic signal suitable for the driver circuit 1.

Fig. 3 shows a schematic structural diagram of a driving circuit according to an embodiment of the present application. As shown in fig. 3, the drive circuit 1 includes K depletion mode HEMT devices (to distinguish them in name from depletion mode HEMTs in other blocks, it is referred to as a first depletion mode HEMT device, i.e., T shown in fig. 3 _1-1 、……、T _1-K1 、……、T _M-1 、……、T _M-KM ) And L clamp devices (D shown in FIG. 3) _1-1 、……、D _1-L1 、……、D _M-1 、……、D _M-LM ). K first depletion mode HEMT devices are arranged on a compound semiconductor substrate and arranged into M AND structures 13-1, … …, 13-M, and L clamp devices are arranged into M clamp units 14-1, … …, 14-M, each of which is provided with a gate electrode and a source electrodeAnd each clamping unit corresponds to a structure, M and L are positive integers, and K is an integer greater than or equal to 2.

The K first depletion mode HEMTs correspond to the K signal input terminals of the complex logic gate circuit 100 one-to-one, and also correspond to the K level shift circuits (shown in fig. 2) one-to-one, respectively, in the presence of the level shift circuits. The gate of each of the K first depletion mode HEMT devices is connected to a corresponding one of the K signal input terminals or is connected to the corresponding signal input terminal through a corresponding level shift circuit. For example, each level conversion circuit is connected between the gate of the corresponding first depletion mode HEMT device and the signal input terminal corresponding to the first depletion mode HEMT device, and is configured to convert a signal input to the signal input terminal into an input logic signal (i.e., a gate drive signal) suitable for the first depletion mode HEMT device.

Each and structure 13-i (

i ═

1, 2, … …, M) includes one or more first depletion mode HEMT devices, where the 1 st to mth and structures each include K ₁ 、……、K _M A first depletion mode HEMT device, K ₁ 、……、K _M Are the same or different positive integers, K ₁ 、……、K _M The sum is equal to K. That is, each and structure may include a different number of depletion mode HEMT devices, and may also include the same number of depletion mode HEMT devices. Each and structure is shown in fig. 3 as including a column of depletion mode HEMT devices, but this is not intended to limit the physical location distribution of the depletion mode HEMT devices in each and structure, and it will be understood that the depletion mode HEMT devices in each and structure do not have to be arranged in a column, but may be distributed in any suitable location as long as their connection relationship satisfies the following description.

When the and-structure includes a plurality of first depletion mode HEMT devices, the and-structure first depletion mode HEMT devices are connected in series. The drains and sources of the plurality of first depletion mode HEMTs in the structure are sequentially connected together in series, except for the gates connected to the corresponding signal input terminals, and two depletion mode HEMTs at the front and rear ends of the series of depletion mode HEMTs are respectively connected to the first end 10 of the driving circuit 1 and the corresponding clamping units. Here, the first depletion mode HEMT device of the and structure connected to the first terminal 10 of the driver circuit 1 is referred to as a first depletion mode HEMT device, the first depletion mode HEMT device of the and structure connected to the corresponding clamp unit is referred to as a last first depletion mode HEMT device, a direction toward the first depletion mode HEMT device is referred to as "front", and a direction toward the last first depletion mode HEMT device is referred to as "rear". It is to be understood that the above definitions are for ease of description only and that other suitable definitions may be used.

Specifically, the drain of the first depletion mode HEMT device in the and structure is connected to the first terminal 10 of the driving circuit 1, the source of the last first depletion mode HEMT device in the and structure is connected to the head end of a corresponding one of the clamping units (e.g., terminal 141-i (i ═ 1, 2, … …, M)) as shown in fig. 3 and described below), the drain of each other first depletion mode HEMT device in the and structure is connected to the source of the previous first depletion mode HEMT device in the and structure, and the source of each other first depletion mode HEMT device in the and structure is connected to the drain of the next first depletion mode HEMT device in the and structure.

Taking structure 13-1 as an example, it includes K ₁ A first depletion mode HEMT device T _1-1 、……、T _1-K1 This K is ₁ The first depletion type HEMT devices are sequentially connected in series to form a string. First depletion mode HEMT device T _1-1 Is connected to a first terminal 10 of the drive circuit 1, and a last first depletion mode HEMT device T _1-K1 Is connected to the head end 141-1 of the corresponding clamping unit 14-1. And the drain and source of the other first depletion mode HEMT device (not shown in fig. 3) in the structure 13-1 are connected in series in that order.

When the and-structure comprises a first depletion mode HEMT device, the first depletion mode HEMT device and the last first depletion mode HEMT device of the and-structure are both the first depletion mode HEMT device, and no other first depletion mode HEMT device exists, the drain electrode of the first depletion mode HEMT device is connected to the first end of the driving circuit, and the source electrode of the first depletion mode HEMT device is connected to the head end of a corresponding clamping unit.

In one embodiment, the K first depletion type HET devices included in the drive circuit 1 are formed on the same compound semiconductor substrate. The compound semiconductor substrate may include at least one of GaAs, GaN, and InP.

And similar to the structure, each clamping unit also comprises one or more clamping devices, each clamping device is provided with a first end and a second end, wherein the 1 st to Mth clamping units respectively comprise L ₁ 、……、L _M A clamping device, L ₁ 、……、L _M Are the same or different positive integers, L ₁ 、……、L _M The sum is equal to L. That is, each clamping unit may include a different number of clamping devices, and may also include the same number of clamping devices. Likewise, each clamping unit is shown in fig. 3 as including a column of clamping devices, but this is not intended to limit the physical location distribution of the clamping devices in each clamping unit, and it will be understood that the clamping devices in each clamping unit need not be arranged in a column, but may be distributed at any suitable location as long as their connection relationship satisfies the following description.

When the clamping unit includes a plurality of clamping devices, the plurality of clamping devices in the clamping unit are connected in series. The first and second ends of the clamping devices in the clamping unit are connected in series in turn, wherein the two clamping devices at the two ends of the series of clamping devices are connected to the second end 11 of the corresponding and structure and driving circuit 1, respectively. Here, the clamp device connected to the corresponding and structure is referred to as a first clamp device of the clamp unit, the clamp device connected to the second end 11 of the driver circuit 1 is referred to as a last clamp device of the clamp unit, a first end of the first clamp device is referred to as a head end of the clamp unit, a second end of the last clamp device is referred to as a tail end of the clamp unit, a direction toward the first clamp device is referred to as "front", and a direction toward the last clamp device is referred to as "rear". It is to be understood that the above definitions are for ease of illustration only and that other suitable definitions may be used. As shown in fig. 3, for a clamping unit including a plurality of clamping devices, except for a first clamping device and a last clamping device, a first end of each other clamping device in the clamping unit is connected to a second end of a previous clamping device in the clamping unit, a second end of each other clamping device in the clamping unit is connected to a first end of a next clamping device in the clamping unit, wherein a head end of the clamping unit is connected to a source of a corresponding last first depletion mode HEMT device in the structure, and a tail end of the clamping unit is connected to the second end 11 of the driving circuit 1.

Taking clamp unit 14-1 as an example, it includes L ₁ A clamping device D _1-1 、……、D _1-L1 . As shown in fig. 3, a first clamping device D _1-1 As a head end 141-1 of the clamping unit 14-1 and connected to the corresponding last first depletion mode HEMT device T of the structure 13-1 _1-K1 Of the substrate. Last clamping device D _1-L1 Is connected to the second terminal 11 of the driver circuit 1. A second terminal of each other clamp device (not shown in fig. 3) of clamp unit 14-1 is connected to a first terminal of a subsequent clamp device in clamp unit 14-1.

In a clamping unit comprising one clamping device, a first terminal of the clamping device is used as a head end of the clamping unit, and a second terminal of the clamping device is used as a tail end of the clamping unit and is connected to a second terminal 11 of the driving circuit 1.

In some embodiments, the clamping device may be a compound-based diode, with an anode of the diode as a first end of the clamping device and a cathode of the diode as a second end of the clamping device. Fig. 4A shows a clamping unit 14-i (i ═ 1, 2, … …, L) composed of a plurality of diodes as clamping devices, where the anode of the first diode is the head end 141-i of the clamping unit 14-i and the cathode of the last diode is the tail end 142-i of the clamping unit 14-i.

In some embodiments, the clamp device may also be a depletion mode HEMT device (e.g., fig. 4B-4D), referred to as a second depletion mode HEMT device, to distinguish it from depletion mode HEMT devices in other modules, where the first end of the clamp device is the gate of the second depletion mode HEMT device and the second end of the clamp device may be either:

the drain electrode of the second depletion mode HEMT device is used as a second end of the clamping device; or

The source electrode of the second depletion mode HEMT device is used as a second end of the clamping device; or

The drain and source of the second depletion mode HEMT device are shorted together as a second terminal of the clamp device.

Fig. 4B shows an embodiment in which the drain of each of the second depletion mode HEMT devices serves as the second terminal of the clamp device, where the gate of each of the second depletion mode HEMT devices in clamp unit 14-i (i ═ 1, 2, … …, L) serves as the first terminal of the clamp device, the drain serves as the second terminal, and the source may be floating.

Fig. 4C shows an embodiment in which the source of each of the second depletion mode HEMT devices in the clamping unit 14-i (i ═ 1, 2, … …, L) has the gate as the first end of the clamping device, the source as the second end, and the drain as the second end, which can be floating.

Fig. 4D shows an embodiment in which the drain and source of the second depletion mode HEMT devices are shorted together as the second end of the clamp device, with the gate of each of the second depletion mode HEMT devices in the clamp unit 14-i (

i

1, 2, … …, L) as the first end of the clamp device and the drain and source are shorted together as the second end of the clamp device.

Fig. 5 shows a schematic structure diagram of a level shift circuit 3-i (i ═ 1, 2, … …, K) according to an embodiment of the present application. As previously described with reference to fig. 2, a level shift circuit may be provided between the signal input of the complex logic gate circuit 100 and the gate of the corresponding first depletion mode HEMT device. As shown in fig. 5, in this embodiment, each of the level conversion circuits 3-i includes: n is a radical of _i (i ═ 1, 2, … …, K) level shift elements Z ₁ 、……、Z _Ni First resistance R _1i A second resistance R _2i And a third resistor R _3i In which N is _i (i-1, 2, … …, K) is a positive integer, and N is ₁ 、……、N _K And may be the same or different positive integers. That is, each level shifting circuit may include the same or a different number of level shifting elements as the other level shifting circuits. In addition, different level shift circuits may have different resistances of the first resistor, the second resistor, or the third resistor.

N _i A level shift element for shifting the level of the input signal, R _1i 、R _2i And R _3i The partial pressure is acted. N is a radical of _i A level shift element and a first resistor R _1i Are connected in series to form a series circuit, N _i A level shift element and a first resistor R _1i As a series unit of the series circuit, thereby forming N _i +1 series units. A first resistor R _1i May be connected at the head end (i.e. as the first series unit) or tail end (i.e. as the last series unit) of the series circuit, or may be connected at N _i Between any two of the level shifting elements. In some embodiments, the first resistance R _1i And N _i The positional relationship of the individual level shifting elements may vary according to design requirements. In the embodiment shown in fig. 5, the first resistor R _1i Connected at the end of the series circuit as the last series unit, i.e. the first resistor R _1i Second terminal and second resistor R _2i And a third resistor R _3i Are connected together.

In particular, N _i The first end of the first of the +1 series units is connected to a corresponding signal input terminal P of the K signal input terminals of the complex logic gate circuit 100 _in-i ，N _i The second end of the last series unit in the +1 series units is connected to the second resistor R _2i First terminal and third resistor R _3i First end of, N _i The first end of each other series unit of the +1 series units is connected to the second end of the previous series unit, N _i The second end of each other series unit of the +1 series units is connected to the first end of the following series unit. Third resistor R _3i Is connected to a reference level signal Vf, and a second resistor R _2i To (1) aTwo ends of the first depletion mode HEMT device are connected to the grid of the corresponding first depletion mode HEMT device so as to input the converted grid driving signal to the first depletion mode HEMT device. The level shift circuit 3-i divides and level-shifts the input signal according to the reference level signal Vf to convert into an appropriate gate driving signal.

In some embodiments, the level-shifting element is a compound-based diode having an anode as the first end of the series cell and a cathode as the second end of the series cell.

In some embodiments, the level-shifting element is a depletion mode HEMT device, referred to as a third depletion mode HEMT device, in distinction from depletion mode HEMT devices in other modules. The gate of the third depletion mode HEMT device serves as a first end of the series unit, and a second end of the series unit is any one of the following cases:

the drain electrode of the third depletion mode HEMT device is used as a second end of the series unit; or

The source electrode of the third depletion mode HEMT device is used as a second end of the series unit; or

And the drain electrode of the third depletion mode HEMT device is in short circuit with the source electrode thereof to serve as a second end of the series unit.

In some embodiments, the plurality of level shift circuits included in the driving circuit 1 may be respectively connected to the corresponding reference level signals Vf, or may share one reference level signal Vf. The reference level signal Vf may be a level signal that is the same as or different from the low-level power supply VL, and may be a signal of ground, VL, or other negative voltage power supply, for example.

In some embodiments, the first resistance R may be adjusted _1i Resistance value of, the second resistor R _2i And the third resistor R _3i To optimize power consumption.

In a specific application, the specific structure of the plurality of level shift circuits included in the complex logic gate circuit 100 may be designed to be the same or different according to the application scenario or user requirements. For example, the same structure as the level shift circuit to which the gate of the first depletion mode HEMT device in the structure is connected.

Fig. 6 shows a schematic structural diagram of a load circuit according to an embodiment of the present application. As described above with reference to fig. 2, the first terminal 10 of the driving circuit 1 may be connected to the high level power supply VH through the load circuit 2, and the first terminal 20 of the load circuit 2 is connected to the first terminal 10 of the driving circuit 1 and the signal output terminal P of the complex logic gate circuit 100 _out The second terminal 21 of the load circuit 2 is connected to the high-level power supply VH. The load circuit 2 may include a fourth depletion mode HEMT device 22 and a clamp choke resistor 23. The drain of the fourth depletion mode HEMT device 22 is connected to the second terminal 21 of the load circuit 2, the source of the fourth depletion mode HEMT device 22 is connected to the first terminal of the clamp choke resistor 23, and the gate of the fourth depletion mode HEMT device and the second terminal of the clamp choke resistor 23 are connected to the first terminal 20 of the load circuit 2.

By connecting the clamp choke resistor 23 between the fourth depletion mode HEMT device 22 and the depletion mode HEMT device of the drive circuit 1, the clamp choke resistor 23 can adjust the voltage difference between the source of the fourth depletion mode HEMT device 22 and the drain of the depletion mode HEMT device of the drive circuit 1, and reduce the source current of the fourth depletion mode HEMT device 22, thereby realizing dynamic adjustment of the impedance value of the load circuit 2.

When any one of the driving circuits 1 is conducted with the structure, a current is generated in the clamp choke resistor 23, and along with the increase of the current, the voltage at the two ends of the clamp choke resistor 23 causes the increase of the negative absolute value of the gate-source voltage of the fourth depletion type HEMT device 22, so that the load impedance is improved, and the load impedance and the driving circuit 1 act together to enable the radio-frequency signal output end P to be connected with the power supply circuit, so that the power supply circuit can be used for supplying power to the power supply circuit _out The voltage of the signal output decreases as the impedance ratio of the load circuit and the drive circuit increases.

In the above embodiments, the high-level power supply or the low-level power supply is relatively general, and the combined embodiment of the high-level power supply and the low-level power supply suitable for the present application is listed as follows:

the high-level power supply is a positive-voltage power supply, and the low-level power supply is ground; or

The high-level power supply is grounded, and the low-level power supply is a negative-voltage power supply; or

The high-level power supply is a positive-voltage power supply, and the low-level power supply is a negative-voltage power supply.

In addition, in some embodiments, the first, second, third, and fourth depletion mode HEMT devices are all compound semiconductor substrate based depletion mode field effect transistors.

In various embodiments of the present application, a composite logic gate circuit may be constructed by a depletion-mode based compound field effect transistor, where the composite logic gate circuit has different operational logic when M and K are different values. For example, when M ≧ 1 and K ≧ 2 are, the composite logic gate described in connection with FIGS. 1-6 becomes an NAND gate logic circuit, and when M ≧ 2, K is ₁ ＝K ₂ ＝……＝K _M When the value is 1, the composite logic gate circuit described in conjunction with fig. 1-6 becomes a nor gate logic circuit, and when M is greater than or equal to 2, K is ₁ ，K ₂ ，……，K _M When any of the above is also equal to or greater than 2, the composite logic gate circuit described in connection with fig. 1-6 is an and nor gate logic circuit, and so on. More complex combinational logic and sequential logic circuits can be constructed based on the logic gates, and the simple control TTL signals input from the outside can be used for realizing the control of the working state of the compound circuit. Furthermore, the composite logic gate circuit or the combined logic/sequential logic circuit and the compound radio frequency microwave circuit can be integrated on the same chip. By way of example, and not limitation, the compound semiconductor substrate may comprise GaAs, GaN, or InP.

Fig. 7 is a schematic diagram of a nor gate logic circuit according to an embodiment of the present application. For the embodiment of the driving circuit in FIG. 3, when M ≧ 2, K ₁ ＝K ₂ ＝……＝K _M The driver circuit becomes as shown in fig. 7, such a driver circuit 1 together with a load circuit 2 and level shifting circuits 3-1, … …, 3-M make up the nor logic circuit embodiment of fig. 7, with the load circuit 2 as described above with reference to fig. 6 and the level shifting circuits 3-1, … …, 3-M as described above with reference to fig. 5. As shown in fig. 7, the drive circuit 1 includes M depletion mode HEMT devices T _1-1 、T _2-1 、……、T _M-1 Wherein each and structure 13-1, … …, 13-M includes only one depletion mode HEMT device.The driver circuit 1 further comprises clamping units 14-1, … …, 14-M corresponding to the structures 13-1, … …, 13-M, respectively. The clamping units 14-1, … …, 14-M are illustratively shown in fig. 7 as each including only one clamping device, it being understood that they may include multiple clamping devices as well.

In the embodiment of FIG. 7, the complex logic gate circuit is a NOR gate logic circuit, with each input terminal P being provided with a positive or negative voltage _in-1 、……、P _in-M All have a corresponding input signal V _in-1 、……、V _in-M The complex logic gate circuit according to the embodiment of fig. 7 performs nor logic processing and outputs P _out Outputs as output signals a boolean function of the corresponding input logic signal:

when inputting signal V _in-1 、……、V _in-M When either of them is at high level, the output V of the nor gate logic circuit of fig. 7 _out At low level when the input signal V is _in-1 、……、V _in-M The output V of the NOR gate logic circuit of FIG. 7 when both are low _out Is high. The operation principle thereof will be explained below.

As shown in fig. 7, in any of the level conversion circuits 3-i (i is 1, … …, M), the first resistor R is provided _1i Second terminal, second resistor R _2i First terminal and third resistor R _3i The common junction point of the first terminal of (A) _i Point, second resistance R _2i The common junction of the second end of the second transistor and the corresponding first depletion mode HEMT device is B _i . Suppose A _i The voltage signal at a point is V _Ai And assume any signal input terminal P _in-i (i-1, … …, M) is V _in ，V _on And if N is the number of the level shift elements and is a positive integer, then:

V _Ai ＝(V _in -N*V _on -V _f )*R _3i /(R _1i +R _3i )+V _f ，

wherein R is _1i And R _3i Respectively, the resistance values V of the first resistor and the third resistor of the level conversion circuit _f Is the voltage value of the reference level signal Vf.

Due to the flow through the second resistor R _2i Is small, so point B _i Voltage V of _Bi Approximately equal to point A _i Voltage V of _Ai 。

When inputting a voltage signal V _in At a low level, the voltage V _Ai And when the voltage difference with the VL is less than the sum of the threshold voltage of the corresponding first depletion mode HEMT device and the threshold voltage of the clamping device, the first depletion mode HEMT device is turned off. When all the first depletion mode HEMTs devices/and structures in fig. 7 are off (i.e., all the input voltage signals are low), the signal output terminal P is off _out Output voltage signal V of _out Is high.

When inputting a voltage signal V _in At increasing time, V _Ai Also increases when V _Ai When the voltage difference with VL increases to be greater than the sum of the threshold voltage of the corresponding first depletion mode HEMT device and the threshold voltage of the clamp device, the corresponding first depletion mode HEMT device and clamp device are turned on simultaneously. When any one or more of the first depletion mode HEMT devices in FIG. 7 and its corresponding clamp device are turned on, a voltage signal V is output _out And begins to fall. With V _Ai Continued increase of V _out Down to a voltage value gradually approaching the sum of the threshold voltage of the clamp device and VL.

Specifically, on the one hand, when the gate of the first depletion mode HEMT device corresponding to any one of the signal input terminals is connected to the input logic signal of high level, the first depletion mode HEMT device is turned on, and the gate voltage of the fourth depletion mode HEMT device 22 in the load circuit 2 is low-level voltage, that is, the output signal is low-level. The voltage difference between the gate and the source of the fourth depletion mode HEMT device 22 can be adjusted to be equal to the threshold voltage of the fourth depletion mode HEMT device 22 by the clamp choke resistor 23 to ensure that the quiescent current between the source of the fourth depletion mode HEMT device 22 and the drain of the first depletion mode HEMT device is small and so that the fourth depletion mode HEMT device 22 does not have to be clampedOn, the gate of the fourth depletion mode HEMT device 22 outputs a low-level signal V _out 。

On the other hand, when the gate of the first depletion mode HEMT device corresponding to any one of the signal input terminals inputs a low-level input logic signal, the first depletion mode HEMT device is turned off. When all the first depletion mode HEMT devices/and structures are turned off, the voltage difference between the gate and the source of the fourth depletion mode HEMT device 22 is 0V and is greater than the threshold voltage of the fourth depletion mode HEMT device 22, the fourth depletion mode HEMT device 22 is turned on, and the gate of the fourth depletion mode HEMT device 22 outputs a high-level signal V _out 。

In some embodiments, the low level voltage may be 0V and the high level voltage may be 3.3V.

It should be noted that the input signal of the embodiment of the present application is compatible with the TTL signal, the high level of the input signal is a TTL high level, and the low level of the input signal is a TTL low level; the high-low level criterion of the output signal Vout varies with the settings of the high-level power supply VH and the low-level power supply VL:

(1) when VH is a positive voltage source with the voltage VDD and VL is the ground, the signal V is output _out The low level of (1) is the turn-on voltage of the clamp device, and the high level is a positive voltage close to VDD.

For example, the voltage of the high level power supply VH is set to 3.3V, the low level power supply is set to ground, the number of level shift elements is 1, and the second resistor R is set _2i Is 384 ohm, the first resistor R _1i 4921 ohm, third resistor R _3i 9780 ohms and the clamp choke 23 is 257 ohms. When inputting signal V _in At a high level, e.g. 3.3V, point A _i Voltage V of _Ai 1.518V, point B _i Voltage V of _Bi Is 1.518V, and outputs a signal V _out Is 1.141V, and low level output is realized. When inputting signal V _in At a low level, e.g. 0V, point A _i Voltage V of _A Is 0V, point B _i Voltage V of _Bi Is 0V, outputs a signal V _out At 3.276V, a high output is achieved.

Notably, the output signal V of the NOR gate logic circuit _out Point A at 10% reduction _i Voltage V of _Ai About 0.4V, the noise margin is low, so by setting N _i The noise margin is improved by a level shift element, and by setting a first resistor R _1i And a third resistor R _3i The voltage division ratio of (a) realizes the turning point (i.e. V) of the input signal _out The point at which the high and low level flip occurs) is adjustable.

(2) When VH is ground and VL is a negative voltage source with Vss, a signal V is output _out The low level of (V) is the sum of the on-voltage of the clamp device and the negative voltage Vss _out Low level of (V) is a negative voltage value), the output signal V is _out Is about 0V.

For example, the high-level power supply VH is set to ground, the low-level power supply VL is set to a negative voltage source with a voltage of Vss, the negative voltage Vss is set to-4V, the number of level shift elements is 4, and the second resistor R is set to _2i Is 384 ohm, the first resistance R _1i 1464 ohms, third resistor R _3i At 5731 ohm and the clamp choke resistor 23 at 257 ohm. When inputting signal V _in At a high level, e.g. 3.3V, voltage V _Ai is-3.1V, the same voltage V _Bi is-3.1V, the output signal V _out And is-2.84V, and low level output is realized. When inputting signal V _in At a low level, e.g. 0V, voltage V _Ai is-3.9V, the same voltage V _Bi is-3.9V, the output signal V _out is-0.1V, and realizes high-level output.

It should be noted that when the output signal of the first depletion mode HEMT device drops by 10%, the input signal V is _in About 1V, voltage V _Bi about-3.6V, so the level of TTL signal can be adjusted by setting N level shift elements and setting a second resistor R _2i And a third resistor R _3i The adjustable turning point of the input signal is realized.

(3) When VH is a positive voltage power supply and VL is a negative voltage power supply, a signal V is output _out VH and VL plus about 1V.

Fig. 8 is a schematic diagram of a nand gate logic circuit according to an embodiment of the present application. For the drive circuit embodiment of fig. 3, when M is 1,K ₁ at ≧ 2, the driver circuit becomes that shown in FIG. 8, such driver circuit 1 together with load circuit 2 and level shift circuits 3-1, … …, 3-K1 constitute the NAND logic circuit embodiment in FIG. 8, with load circuit 2 as described previously with reference to FIG. 6 and level shift circuits as described previously with reference to FIG. 5. As shown in FIG. 8, the driving circuit 1 includes K ₁ A first depletion mode HEMT device T _1-1 、T _1-2 、……、T _1-K1 These first depletion mode HEMT devices are connected in series to form a and structure 13-1. The drive circuit 1 further comprises a clamping unit 14-1 corresponding to the structure 13-1. The clamping units 14-1 are exemplarily shown in fig. 8 to each include only one clamping device, and it is understood that it may include a plurality of clamping devices.

In the embodiment of fig. 8, at each input terminal P _in-1 、……、P _in-K1 All have a corresponding input signal V _in-1 、……、V _in-K1 When these input signals V are _in-1 、……、V _in-K1 When any one or more of them is not high, the corresponding first depletion mode HEMT device is not conductive, and the whole is not conductive with the structure 13-1, so that the operation principle of fig. 7 is described, and the output signal V is outputted at this time _out Is high. When inputting signal V _in-1 、……、V _in-K1 When all the first depletion mode HEMTs are high, all the first depletion mode HEMTs are turned on, and the whole is turned on with the structure 13-1, so that the output signal V is now obtained as described with reference to the operation principle of fig. 7 _out Is low. It can be seen that the operation logic of the composite logic gate circuit of fig. 8 is nand gate logic, which has a pair of inputs P _in-1 、……、P _in-K1 An input signal V of _in-1 、……、V _in-K1 Performing NAND logic processing, and outputting at output terminal P _out Outputs as output signals a boolean function of the corresponding input logic signal:

FIG. 9 shows a structural example of an AND NOR gate logic circuit according to an embodiment of the present applicationIntention is. For the embodiment of the driving circuit in fig. 3, when M is 2, K ₁ ＝K ₂ When 2, the driver circuit becomes that shown in fig. 9, such a driver circuit 1 together with a load circuit 2 and level shifting circuits 3-1, … …, 3-4, each as described above with reference to fig. 5, constitute the and nor logic circuit embodiment in fig. 9, with the load circuit 2 as described above with reference to fig. 6. It should be understood that fig. 9 is an exemplary, but not exclusive, embodiment of an and nor logic circuit according to the present application. As shown in fig. 9, the drive circuit 1 includes four depletion mode HEMT devices T _1-1 、T _1-2 、T _2-1 、T _2-2 Wherein T is _1-1 And T _1-2 Are connected in series to form a structure 13-1, T _2-1 And T _2-2 Connected in series to form structure 13-2. The driver circuit 1 further comprises clamping units 14-1 and 14-2 corresponding to the structures 13-1, 13-2, respectively. The clamping units 14-1 and 14-2 are exemplarily shown in fig. 9 to each include only one clamping device, and it is understood that they may include a plurality of clamping devices.

In the embodiment of fig. 9, at each input terminal P _in-1 、P _in-2 、P _in-3 、P _in-4 All have a corresponding input signal V _in-1 、V _in-2 、V _in-3 、V _in-4 When V is _in-1 And V _in-2 Is conducted with the structure 13-1 when both are high, and when V is high _in-3 And V _in-4 Is conducted with structure 13-2 when both are high, so V _in-1 And V _in-2 In a relationship of _in-3 And V _in-4 Also in an and relationship. When at least one of the two and structures 13-1 and 13-2 is conductive, the signal V is output as described above with reference to fig. 7 _out Is low. When both AND structures 13-1 and 13-2 are non-conductive, signal V is output as described above with reference to FIG. 7 _out Is high. It can be seen that the operation logic of the composite logic gate circuit of fig. 9 is and nor gate logic, which is applied to the input terminal P _in-1 、P _in-2 、P _in-3 、P _in-4 An input signal V of _in-1 、V _in-2 、V _in-3 、V _in-4 Performing AND-OR logic processing, and outputting at output terminal P _out Outputs as output signals a boolean function of the corresponding input logic signal:

the composite logic gate circuit provided by the embodiment of the application uses a depletion type field effect transistor of a compound semiconductor substrate, and the purposes of simple structure and small volume are achieved. In addition, a depletion type field effect transistor of the compound semiconductor substrate is used for constructing a logic gate circuit, so that the logic gate circuit is convenient to integrate with a mainstream compound radio frequency circuit or a microwave/millimeter wave circuit, and the performance density and the function density of a high-end radio frequency system of a compound hybrid circuit can be improved. In addition, the composite logic gate circuit according to the embodiment of the application can be integrated with a compound radio frequency circuit or a microwave/millimeter wave circuit, so that the composite logic gate circuit can be directly used for driving and controlling the compound circuit, and chips or circuits such as an additional Si base or GeSi BiCMOS (Bipolar complementary Metal oxide semiconductor) circuit are not needed, thereby being beneficial to reducing the cost of the compound radio frequency circuit or the microwave/millimeter wave circuit and improving the reliability of the compound radio frequency circuit or the microwave/millimeter wave circuit.

Embodiments of the present application also provide chips comprising composite logic gate circuits as described above, and electronic devices comprising such chips. Fig. 10 and 11 show their schematic views, respectively. As shown in fig. 10, chip 1000 may include a composite logic gate circuit 100, where composite logic gate circuit 100 may be any embodiment of a composite logic gate circuit as described above. In an example, chip 1000 may include one or more complex logic gate circuits 100.

The chip including the composite logic gate embodiments of the present application may be used in an electronic device. As shown in fig. 11, the electronic device 1100 includes the chip 1000 shown in fig. 10. The electronic device 1100 may be a wireless device or any other electronic device that may use a composite logic gate circuit according to embodiments of the present application.

A wireless device may be a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device may also be a cellular phone, a smart phone, a tablet, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop, a smartbook, a netbook, a cordless phone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, and the like. The wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

Those of skill in the art would understand that information and signals may be represented or processed using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits (bits), symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Unless the context indicates otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in a generic and inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is meant to "include, but not limited to". Conditional language such as "may," "for example," and the like, as used herein, unless specifically stated otherwise or otherwise understood in accordance with the context in which it is used, is generally intended to indicate that some embodiments include some features, elements, and/or states while other embodiments do not. Moreover, the words "herein," "above," "below," and words of similar importance, when used in this application, shall refer to the entire application, rather than to any particular portions of the application. Where the context permits, words in the above detailed description using the singular or plural form may also include the plural or singular form respectively.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A composite logic gate circuit comprising a driver circuit having a signal output terminal and K signal input terminals, a first terminal of the driver circuit connected to the signal output terminal of the composite logic gate circuit and to a high-level power supply through a load circuit, a second terminal of the driver circuit connected to a low-level power supply, wherein the first terminal of the load circuit is connected to the first terminal of the driver circuit and to the signal output terminal of the composite logic gate circuit, and the second terminal of the load circuit connected to the high-level power supply, wherein the driver circuit comprises K first depletion mode HEMT devices arranged on a compound semiconductor substrate and arranged in M AND structures, and L clamp devices arranged in M clamp units, one for each of the M clamp units, m and L are positive integers, K is an integer greater than or equal to 2, wherein:

the grid electrodes of the K first depletion type HEMT devices correspond to the K signal input ends of the composite logic gate circuit one by one, and the grid electrode of each first depletion type HEMT device in the K first depletion type HEMT devices is connected to one corresponding signal input end in the K signal input ends;

each clamping unit comprises one or more clamping devices, each clamping device is provided with a first end and a second end, wherein the 1 st to Mth clamping units respectively comprise L ₁ 、……、L _M A clamping device, L ₁ 、……、L _M Are the same or different positive integers, L ₁ 、……、L _M The sum is equal to L;

2. The composite logic gate circuit of claim 1, wherein the clamping device is a compound based diode, wherein an anode of the diode serves as a first terminal of the clamping device and a cathode of the diode serves as a second terminal of the clamping device.

3. The composite logic gate circuit of claim 1, wherein the clamp device is a second depletion mode HEMT device, wherein the gate of the second depletion mode HEMT device serves as the first end of the clamp device, and wherein:

the drain of the second depletion mode HEMT device is used as a second end of the clamping device; or

4. The composite logic gate circuit of claim 1, wherein:

The high-level power supply is ground, and the low-level power supply is a negative-voltage power supply; or

5. The composite logic gate circuit of claim 1, wherein the K first depletion mode HEMT devices are formed on the same compound substrate.

6. The composite logic gate circuit of claim 1, further comprising K level shifting circuits in one-to-one correspondence with the K first depletion mode HEMT devices, wherein each level shifting circuit is connected between the gate of a corresponding first depletion mode HEMT device and the signal input terminal corresponding to the first depletion mode HEMT device for converting a signal input to the signal input terminal into an input logic signal suitable for the first depletion mode HEMT device.

7. The complex logic gate circuit of claim 6, wherein the ith level shift circuit of the K level shift circuits comprises N _i A level shift element, a first resistor R _1i A second resistor R _2i And a third resistor R _3i Where i is 1, … …, K, N ₁ 、……、N _K Are the same or different positive integers, wherein:

said N is _i A level shift element and a first resistor R _1i Connected in series to form a series circuit, wherein the first resistor R _1i Connected at the head, tail, or N of the series circuit _i Between any two level shift elements of the level shift elements, N _i A level shift element and a first resistor R _1i Each of which forms N as a series unit of the series circuit _i +1 serial units, said N _i A first end of a first one of the +1 series units is connected to a corresponding one of the K signal input terminals, the N _i The second end of the last series unit in the +1 series units is connected to the second resistor R _2i And the third resistor R _3i A first terminal of (2), said N _i A first end of each other of the +1 series units is connected to a second end of a previous series unit, the N _i The second end of each other series unit in the +1 series units is connected to the first end of the following series unit;

the third resistor R _3i Is connected to a reference level signal, the second resistor R _2i Is connected to the gate of the corresponding first depletion mode HEMT device to input the converted input logic signal to the first depletion mode HEMT device.

8. The composite logic gate circuit of claim 7, wherein the level shifting element is a compound based diode having an anode as the first end of the series cell and a cathode as the second end of the series cell.

9. The compound logic gate circuit of claim 7, wherein the level-shifting element is a third depletion mode HEMT device, wherein the gate of the third depletion mode HEMT device serves as the first end of the series cell, and wherein:

10. The compound logic gate circuit of claim 1, wherein the load circuit comprises a fourth depletion mode HEMT device and a clamp choke resistor, wherein the drain of the fourth depletion mode HEMT device is connected to the second terminal of the load circuit, the source of the fourth depletion mode HEMT device is connected to the first terminal of the clamp choke resistor, and the gate of the fourth depletion mode HEMT device and the second terminal of the clamp choke resistor are connected to the first terminal of the load circuit.

11. A chip comprising a composite logic gate circuit according to any of claims 1 to 10.

12. An electronic device comprising the chip of claim 11.