CN211908766U - Level conversion circuit - Google Patents
Level conversion circuit Download PDFInfo
- Publication number
- CN211908766U CN211908766U CN202020738651.1U CN202020738651U CN211908766U CN 211908766 U CN211908766 U CN 211908766U CN 202020738651 U CN202020738651 U CN 202020738651U CN 211908766 U CN211908766 U CN 211908766U
- Authority
- CN
- China
- Prior art keywords
- electronic switch
- terminal
- electrically connected
- level
- voltage domain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a level shift circuit, level shift circuit electricity is connected between level input end and level output for convert the first voltage domain level signal of level input end input into second voltage domain level signal, and output second voltage domain level signal to level output. The level conversion circuit comprises a control module, a conversion module and a processing module, wherein the control module is used for receiving a first voltage domain level signal input by a level input end and outputting a corresponding pulse electric signal to the conversion module according to the first voltage domain level signal. The conversion module receives the pulse electrical signal and generates a corresponding second voltage domain level signal to the processing module according to the pulse electrical signal. The processing module is used for processing the second voltage domain level signal and transmitting the processed second voltage domain level signal to the level output end. Thus, the level conversion speed can be improved and the power consumption is low.
Description
Technical Field
The utility model relates to an integrated circuit field especially relates to a level shift circuit.
Background
In an integrated circuit chip, the voltage domains of circuit modules are often inconsistent, so a level conversion circuit is used for communication between the modules. In the prior art, in the process of level signal conversion, in order to achieve a faster conversion speed and meet a lower transmission delay requirement, a problem of high power consumption generally exists.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is desirable to provide a level shift circuit capable of realizing high-speed level shift and low power consumption.
The utility model discloses a reach the technical scheme that above-mentioned purpose proposed as follows:
a level conversion circuit is electrically connected between a level input end and a level output end and used for converting a first voltage domain level signal input by the level input end into a second voltage domain level signal and outputting the second voltage domain level signal to the level output end, the level conversion circuit comprises a control module, a conversion module and a processing module, the control module is electrically connected with the level input end, the conversion module is electrically connected between the control module and the processing module, the processing module is electrically connected with the level output end, the control module is used for receiving the first voltage domain level signal input by the level input end and outputting a corresponding pulse electrical signal to the conversion module according to the first voltage domain level signal, the conversion module receives the pulse electrical signal and generates a corresponding second voltage domain level signal to the processing module according to the pulse electrical signal, the processing module is used for processing the second voltage domain level signal and transmitting the processed second voltage domain level signal to the level output end.
Further, the first voltage domain level signal is a low voltage domain level signal, and the second voltage domain level signal is a high voltage domain level signal.
Further, the pulse electric signal is a pulse current signal.
Further, the control module comprises a first delayer, a second delayer, a first inverter and a second inverter, an and gate, a nor gate, a first electronic switch and a second electronic switch, wherein an input end of the first delayer is electrically connected to the level input end, an output end of the first delayer is electrically connected to an input end of the first inverter, an output end of the first inverter is electrically connected to a first input end of the and gate, a second input end of the and gate is electrically connected to the level input end, an output end of the and gate is electrically connected to a first end of the first electronic switch, a second end of the first electronic switch is grounded, a third end of the first electronic switch is electrically connected to an input end of the conversion module, an input end of the second delayer is electrically connected to the level input end, and an output end of the second delayer is electrically connected to an input end of the second inverter, the output end of the second phase inverter is electrically connected with the first input end of the NOR gate, the second input end of the NOR gate is electrically connected with the level input end, the output end of the NOR gate is electrically connected with the first end of the second electronic switch, the second end of the second electronic switch is grounded, and the third end of the second electronic switch is electrically connected with the input end of the conversion module.
Further, the conversion module includes a third electronic switch, a fourth electronic switch, a fifth electronic switch and a sixth electronic switch, a first end of the third electronic switch is electrically connected to a third end of the electronic switch, a second end of the third electronic switch is electrically connected to the first power supply, a third end of the third electronic switch is electrically connected to a third end of the second electronic switch, a first end of the fourth electronic switch is electrically connected to a third end of the third electronic switch, a second end of the fourth electronic switch is electrically connected to a third end of the first electronic switch, a third end of the fourth electronic switch is electrically connected to a second end of the third electronic switch, a first end of the fifth electronic switch is electrically connected to a second end of the fourth electronic switch, a second end of the fifth electronic switch is electrically connected to the second power supply, a third end of the fifth electronic switch is electrically connected to a third end of the third electronic switch, the first end of the sixth electronic switch is electrically connected with the third end of the third electronic switch, the second end of the sixth electronic switch is electrically connected with the second end of the fourth electronic switch, and the third end of the sixth electronic switch is electrically connected with the second end of the fifth electronic switch.
Further, the processing module includes a seventh electronic switch and an eighth electronic switch, a first end of the seventh electronic switch is electrically connected to a second end of the fourth electronic switch, a first end of the seventh electronic switch is also electrically connected to a first end of the eighth electronic switch, a second end of the seventh electronic switch is electrically connected to the level output terminal, a second end of the seventh electronic switch is also electrically connected to a third end of the eighth electronic switch, a third end of the seventh electronic switch is electrically connected to the first power supply, and a second end of the eighth electronic switch is electrically connected to the second power supply.
Further, the first electronic switch, the second electronic switch, the fifth electronic switch, the sixth electronic switch and the eighth electronic switch are all N-channel field effect transistors, the first end, the second end and the third end of the first electronic switch, the second electronic switch, the fifth electronic switch, the sixth electronic switch and the eighth electronic switch respectively correspond to the gate, the source and the drain of the N-channel field effect transistor, the third electronic switch, the fourth electronic switch and the seventh electronic switch are all P-channel field effect transistors, and the first end, the second end and the third end of the third electronic switch, the fourth electronic switch and the seventh electronic switch respectively correspond to the gate, the source and the drain of the P-channel field effect transistor.
Above-mentioned level shift circuit is through passing through the pulse current that control module produced, control conversion module realizes that low-voltage domain level compares with the continuous current that prior art used to high-voltage domain level shift, the utility model has the advantages of high-speed low-power consumption.
Drawings
Fig. 1 is a block diagram of a preferred embodiment of the level shift circuit and the level input terminal and the level output terminal of the present invention.
Fig. 2 is a circuit diagram of a preferred embodiment of the level shift circuit of the present invention.
Description of the main elements
Time delay devices BUF1 and BUF2
Inverters INV1, INV2
AND gate AND
NOR gate NOR
Electronic switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8
Power supplies VDD _ HV, GND _ HV
The following detailed description of the invention will be further described in conjunction with the above-identified drawings.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention provides a level shift circuit 10. The level shift circuit 10 is electrically connected between a level input terminal 20 and a level output terminal 30, and configured to convert a first voltage domain level signal input by the level input terminal 20 into a second voltage domain level signal and output the second voltage domain level signal to the level output terminal 30. In this embodiment, the level shift circuit 10 is applied in an integrated circuit to provide different level requirements for different circuit modules in the integrated circuit, where the first voltage domain level signal is a low voltage domain level signal, and the second voltage domain level signal is a high voltage domain level signal.
The level shift circuit 10 includes a control module 11, a shift module 12, and a processing module 13. The control module 11 is electrically connected to the level input terminal 20. The conversion module 12 is electrically connected between the control module 11 and the processing module 13. The processing module 13 is electrically connected to the level output terminal 30.
The control module 11 is configured to receive a first voltage domain level signal input by the level input end 20, and output a corresponding pulse electrical signal to the conversion module 12 according to the first voltage domain level signal. In this embodiment, the pulse electrical signal is a pulse current signal. The conversion module 12 receives the pulse electrical signal and generates a corresponding second voltage domain level signal to the processing module 13 according to the pulse electrical signal. The processing module 13 is configured to process the second voltage domain level signal, and transmit the processed second voltage domain level signal to the level output terminal 30, so as to meet level requirements of different circuit modules in the integrated circuit. Because control module 11 transmit extremely what conversion module 12 is the pulse signal of telecommunication, compare the signal of telecommunication that lasts among the prior art, the utility model discloses the consumption has greatly reduced.
Referring to fig. 2, fig. 2 is a circuit diagram of a preferred embodiment of the present invention. In this embodiment, the control module 11 includes two time delay units BUF1-BUF2, two inverters INV1-INV2, an AND gate AND, a NOR gate NOR, AND two electronic switches Q1-Q2. The input end of the time delay BUF1 is electrically connected to the level input end 20, and the output end of the time delay BUF1 is electrically connected to the input end of the inverter INV 1. An output end of the inverter INV1 is electrically connected to a first input end of the AND gate AND. A second input terminal of the AND gate AND is electrically connected to the level input terminal 20, AND an output terminal of the AND gate AND is electrically connected to a first terminal of the electronic switch Q1. The second terminal of the electronic switch Q1 is grounded, and the third terminal of the electronic switch Q1 is electrically connected to the input terminal of the conversion module 12. The input end of the time delay BUF2 is electrically connected to the level input end 20, and the output end of the time delay BUF2 is electrically connected to the input end of the inverter INV 2. An output end of the inverter INV2 is electrically connected to a first input end of the NOR gate NOR. A second input of the NOR gate NOR is electrically connected to the level input 20, and an output of the NOR gate NOR is electrically connected to a first terminal of the electronic switch Q2. The second terminal of the electronic switch Q2 is grounded, and the third terminal of the electronic switch Q2 is electrically connected to the input terminal of the conversion module 12.
The conversion module 12 includes four electronic switches Q3-Q6. The first terminal of the electronic switch Q3 is electrically connected to the third terminal of the electronic switch Q1, the second terminal of the electronic switch Q3 is electrically connected to the power supply VDD _ HV, and the third terminal of the electronic switch Q3 is electrically connected to the third terminal of the electronic switch Q2. The first terminal of the electronic switch Q4 is electrically connected to the third terminal of the electronic switch Q3, the second terminal of the electronic switch Q4 is electrically connected to the third terminal of the electronic switch Q1, and the third terminal of the electronic switch Q4 is electrically connected to the second terminal of the electronic switch Q3. The first terminal of the electronic switch Q5 is electrically connected to the second terminal of the electronic switch Q4, the second terminal of the electronic switch Q5 is electrically connected to the power GND _ HV, and the third terminal of the electronic switch Q5 is electrically connected to the third terminal of the electronic switch Q3. The first terminal of the electronic switch Q6 is electrically connected to the third terminal of the electronic switch Q3, the second terminal of the electronic switch Q6 is electrically connected to the second terminal of the electronic switch Q4, and the third terminal of the electronic switch Q6 is electrically connected to the second terminal of the electronic switch Q5. In this embodiment, the electronic switches Q3-Q6 together form a latch unit, and when no current is input to the input terminal of the conversion module 12, the state of the level signal output by the conversion module 12 is locked by the latch unit formed by the electronic switches Q3-Q6; when there is an input current at the input of the switching module 12, a new latch state is re-established, which is completely determined by the input current. Thus, the voltage output by the conversion module 12 ranges between the voltages U1 and U2 provided by the power supply VDD _ HV and the power supply GND _ HV, respectively, and is not pulled down by the input current signal to be less than U2.
In this embodiment, the time required to reestablish a new latch state after the latch state of the latch unit formed by the electronic switches Q3-Q6 is broken depends on the aspect ratio of the electronic switches Q3-Q6. The larger the width-to-length ratio, the shorter the time required to establish a new latch state; once the new latch state is completed, the power consumption by the Q3-Q4 will be 0, while the electronic switches Q5-Q6 will only consume power when there is input current, and will also consume 0 when there is no input current.
The processing module 13 comprises two electronic switches Q7-Q8. The first terminal of the electronic switch Q7 is electrically connected to the second terminal of the electronic switch Q4, and the first terminal of the electronic switch Q7 is also electrically connected to the first terminal of the electronic switch Q8. The second terminal of the electronic switch Q7 is electrically connected to the level output terminal 30, and the second terminal of the electronic switch Q7 is also electrically connected to the third terminal of the electronic switch Q8. The third terminal of the electronic switch Q7 is electrically connected with the power supply VDD _ HV. The second terminal of the electronic switch Q8 is electrically connected to the power supply GND _ HV.
In operation, when the low-voltage level signal input by the level input terminal 20 remains unchanged, the level signals of the first input terminal and the second input terminal of the NOR gate NOR are opposite, and the NOR gate NOR outputs a low-level signal; the first input end of the AND gate AND is opposite to the second input end of the AND gate AND in level, the AND gate AND outputs a low level signal, AND the electronic switch Q1 AND the electronic switch Q2 are kept turned off.
When the low voltage domain level signal inputted from the level input terminal 20 changes from low level to high level, the second input terminal of the AND gate AND changes to high level, the first input terminal of the AND gate AND does not change immediately due to the presence of the delay device BUF1, AND remains at high level, AND at this time, the AND gate AND outputs high level. However, when the high level signal input from the level input terminal 20 is delayed by the delay device BUF1, AND is inverted by the inverter INV1 AND transmitted to the first input terminal of the AND gate AND, the first input terminal of the AND gate AND becomes a low level, AND at this time, the AND gate AND outputs a low level. In summary, when the signal inputted from the level input terminal 20 changes from low level to high level, the AND gate AND outputs a short high level signal, AND the duration of the high level signal is determined by the time delay BUF 1. Thus, the electronic switch Q1 turns on for a short time, and generates a short-time pulse current I1. The conversion module 12 outputs a high-voltage domain high-level signal. The processing module 13 performs phase inversion and current amplification output on the high-voltage domain high-level signal.
When the low-voltage level signal inputted from the level input terminal 20 changes from high level to low level, the second input terminal of the NOR gate NOR changes to low level, and the first input terminal of the NOR gate NOR does not change immediately due to the presence of the delay device BUF2, and thus remains at low level, at which time the NOR gate NOR will output high level. However, when the low level signal inputted from the level input terminal 20 is delayed by the delay BUF2, and is inverted by the inverter INV2 and transmitted to the first input terminal of the NOR gate NOR, the first input terminal of the NOR gate NOR becomes high level, and at this time, the NOR gate NOR outputs low level. In summary, when the signal inputted from the level input terminal 20 changes from high level to low level, the NOR gate NOR outputs a short high signal, and the duration of the high signal is determined by the time delay BUF 2. Thus, the electronic switch Q2 turns on for a short time, and generates a short-time pulse current I2. The conversion module 12 outputs a high-voltage domain low-level signal. The processing module 13 performs phase inversion and current amplification output on the high-voltage domain low-level signal. In this way, the conversion module 12 can realize the conversion from the low-voltage domain level to the high-voltage domain level signal through the pulse current signal generated by the control module 11.
In the present embodiment, the pulse currents I1 and I2 are relatively short in duration, and the average power consumption caused thereby is relatively low, which allows the width-to-length ratios of the electronic switches Q3 to Q6 to be larger, and the time required for the latch unit formed by the electronic switches Q3 to Q6 to reestablish a new state is shorter, and the signal transmission rate is faster.
In this embodiment, the electronic switches Q1, Q2, Q5, Q6 and Q8 are all N-channel fets, and the first, second and third terminals of the electronic switches Q1, Q2, Q5, Q6 and Q8 correspond to the gate, source and drain of the N-channel fets, respectively. The electronic switches Q3, Q4 and Q7 are P-channel field effect transistors, and the first end, the second end and the third end of each of the electronic switches Q3, Q4 and Q7 respectively correspond to the grid electrode, the source electrode and the drain electrode of the P-channel field effect transistor.
The level shift circuit is through passing through the pulse current that control module 11 produced controls conversion module 12 realizes that low-voltage domain level compares with the continuous current that prior art used to high-voltage domain level shift, the utility model has the advantages of high-speed low-power consumption.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A level conversion circuit is electrically connected between a level input end and a level output end and used for converting a first voltage domain level signal input by the level input end into a second voltage domain level signal and outputting the second voltage domain level signal through the level output end, and is characterized in that the level conversion circuit comprises a control module, a conversion module and a processing module, wherein the control module is electrically connected with the level input end, the conversion module is electrically connected between the control module and the processing module, the processing module is electrically connected with the level output end, the control module is used for receiving the first voltage domain level signal input by the level input end and outputting a corresponding pulse electric signal to the conversion module according to the first voltage domain level signal, the conversion module receives the pulse electric signal and generates a corresponding second voltage domain level signal to the processing module according to the pulse electric signal, the processing module is used for processing the second voltage domain level signal and transmitting the processed second voltage domain level signal to the level output end.
2. The level shift circuit of claim 1, wherein the first voltage domain level signal is a low voltage domain level signal and the second voltage domain level signal is a high voltage domain level signal.
3. The level shift circuit of claim 1, wherein the pulsed electrical signal is a pulsed current signal.
4. The level shifter circuit of claim 1, wherein the control module comprises a first delay, a second delay, a first inverter and a second inverter, an AND gate, a NOR gate, a first electronic switch and a second electronic switch, wherein an input terminal of the first delay is electrically connected to the level input terminal, an output terminal of the first delay is electrically connected to an input terminal of the first inverter, an output terminal of the first inverter is electrically connected to a first input terminal of the AND gate, a second input terminal of the AND gate is electrically connected to the level input terminal, an output terminal of the AND gate is electrically connected to a first terminal of the first electronic switch, a second terminal of the first electronic switch is grounded, a third terminal of the first electronic switch is electrically connected to the input terminal of the conversion module, and an input terminal of the second delay is electrically connected to the level input terminal, the output end of the second delayer is electrically connected with the input end of the second phase inverter, the output end of the second phase inverter is electrically connected with the first input end of the NOR gate, the second input end of the NOR gate is electrically connected with the level input end, the output end of the NOR gate is electrically connected with the first end of the second electronic switch, the second end of the second electronic switch is grounded, and the third end of the second electronic switch is electrically connected with the input end of the conversion module.
5. The circuit according to claim 4, wherein the converting module comprises a third electronic switch, a fourth electronic switch, a fifth electronic switch and a sixth electronic switch, a first terminal of the third electronic switch is electrically connected to a third terminal of the electronic switch, a second terminal of the third electronic switch is electrically connected to a first power source, a third terminal of the third electronic switch is electrically connected to a third terminal of the second electronic switch, a first terminal of the fourth electronic switch is electrically connected to a third terminal of the third electronic switch, a second terminal of the fourth electronic switch is electrically connected to a third terminal of the first electronic switch, a third terminal of the fourth electronic switch is electrically connected to a second terminal of the third electronic switch, a first terminal of the fifth electronic switch is electrically connected to a second terminal of the fourth electronic switch, and a second terminal of the fifth electronic switch is electrically connected to a second power source, the third terminal of the fifth electronic switch is electrically connected to the third terminal of the third electronic switch, the first terminal of the sixth electronic switch is electrically connected to the third terminal of the third electronic switch, the second terminal of the sixth electronic switch is electrically connected to the second terminal of the fourth electronic switch, and the third terminal of the sixth electronic switch is electrically connected to the second terminal of the fifth electronic switch.
6. The circuit according to claim 5, wherein the processing module comprises a seventh electronic switch and an eighth electronic switch, a first terminal of the seventh electronic switch is electrically connected to a second terminal of the fourth electronic switch, the first terminal of the seventh electronic switch is further electrically connected to the first terminal of the eighth electronic switch, the second terminal of the seventh electronic switch is electrically connected to the level output terminal, the second terminal of the seventh electronic switch is further electrically connected to a third terminal of the eighth electronic switch, the third terminal of the seventh electronic switch is electrically connected to the first power supply, and the second terminal of the eighth electronic switch is electrically connected to the second power supply.
7. The circuit of claim 6, wherein the first electronic switch, the second electronic switch, the fifth electronic switch, the sixth electronic switch, and the eighth electronic switch are all N-channel fets, first terminals, second terminals, and third terminals of the first electronic switch, the second electronic switch, the fifth electronic switch, the sixth electronic switch, and the eighth electronic switch respectively correspond to gates, sources, and drains of the N-channel fets, the third electronic switch, the fourth electronic switch, and the seventh electronic switch are all P-channel fets, and first terminals, second terminals, and third terminals of the third electronic switch, the fourth electronic switch, and the seventh electronic switch respectively correspond to gates, sources, and drains of the P-channel fets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020738651.1U CN211908766U (en) | 2020-05-07 | 2020-05-07 | Level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020738651.1U CN211908766U (en) | 2020-05-07 | 2020-05-07 | Level conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211908766U true CN211908766U (en) | 2020-11-10 |
Family
ID=73270142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020738651.1U Active CN211908766U (en) | 2020-05-07 | 2020-05-07 | Level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211908766U (en) |
-
2020
- 2020-05-07 CN CN202020738651.1U patent/CN211908766U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111342834A (en) | Level conversion circuit | |
| CN101562449B (en) | High-speed current switch driver based on MOS current-mode logic | |
| CN113691249B (en) | Work cycle correction circuit and method thereof | |
| US6369632B1 (en) | CMOS switching circuitry | |
| CN211908766U (en) | Level conversion circuit | |
| CN107222198B (en) | Level shift circuit | |
| CN115225078B (en) | Level detection circuit and level conversion circuit | |
| CN107181481B (en) | Input/output receiving circuit | |
| CN110518903B (en) | Level shift circuit | |
| CN112532230A (en) | Level conversion circuit | |
| KR20170057101A (en) | Level conversion device and method | |
| US5999017A (en) | CMOS implemented output buffer circuit for providing ECL level signals | |
| CN113810042A (en) | Low-voltage differential signal driver | |
| CN110545098A (en) | CMOS level converter, operation method, device and equipment | |
| CN110798201A (en) | High-speed withstand voltage level conversion circuit | |
| CN110855285B (en) | High frequency level shifter | |
| CN117434340B (en) | Voltage detection circuit and chip | |
| CN116827333B (en) | Level shift circuit | |
| CN112383298B (en) | DDR (double data Rate) sending circuit | |
| WO2023112506A1 (en) | Electronic circuit | |
| US20230170885A1 (en) | Voltage conversion circuit and memory | |
| CN115001477B (en) | Signal interface circuit for positive and negative voltage input | |
| CN109450435B (en) | LVDS interface circuit | |
| CN214228233U (en) | Level conversion circuit | |
| US11294416B1 (en) | Differential clock generator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |