CN115548042A - Method for manufacturing semiconductor element - Google Patents
Method for manufacturing semiconductor element Download PDFInfo
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- CN115548042A CN115548042A CN202211303585.5A CN202211303585A CN115548042A CN 115548042 A CN115548042 A CN 115548042A CN 202211303585 A CN202211303585 A CN 202211303585A CN 115548042 A CN115548042 A CN 115548042A
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- dielectric layer
- blocking structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title abstract description 32
- 238000000034 method Methods 0.000 title description 38
- 230000000903 blocking effect Effects 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 121
- 239000000463 material Substances 0.000 description 19
- 238000005530 etching Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention discloses a semiconductor element, which comprises a substrate, a first dielectric layer structure, a second dielectric layer structure, a first light blocking structure, a second light blocking structure, a dielectric layer and a bonding pad layer. The substrate is provided with a first surface, a second surface opposite to the first surface and a first opening. The first dielectric layer structure is arranged on the first surface and is provided with a conductor layer and a second opening. The second opening exposes the conductor layer and is connected with the first opening. The second dielectric layer structure is arranged on the second surface and is provided with a third opening. The third opening exposes a portion of the substrate and connects to the first opening. The first light blocking structure is arranged on the second dielectric layer structure. The second light blocking structure is arranged on the side wall of the third opening. The dielectric layer is arranged on the light blocking structure and in the third opening, and is provided with a fourth opening connected with the first opening. The pad layer is disposed on the dielectric layer and in the fourth opening, and is electrically connected to the conductive layer. The semiconductor element can prevent the damage of the cushion layer caused by the manufacturing process for forming the light blocking structure.
Description
The present application is a divisional application of an invention patent application having an application number of 201810449833.4 and an invention name of "method for manufacturing semiconductor device" filed on 11/05/2018.
Technical Field
The present invention relates to a semiconductor, and more particularly, to a semiconductor device.
Background
Currently, in the fabrication process of a photo-dependent semiconductor device, a light blocking structure is fabricated. For example, in the fabrication process of the image sensor, the pad is fabricated first, and then the light blocking structure (e.g., metal grid) is fabricated. As a result, the manufacturing process (e.g., etching process) for forming the light blocking structure is prone to damage the landing pad.
Disclosure of Invention
The present invention provides a semiconductor device, which can prevent the damage of the light blocking structure to the pad layer in the manufacturing process.
The invention provides a semiconductor element, which comprises a substrate, a first dielectric layer structure, a second dielectric layer structure, a first light blocking structure, a second light blocking structure, a dielectric layer and a bonding pad layer. The substrate is provided with a first surface, a second surface opposite to the first surface and a first opening. The first dielectric layer structure is disposed on the first surface and has a conductive layer and a second opening. The second opening exposes the conductor layer and is connected with the first opening. The second dielectric layer structure is arranged on the second surface and is provided with a third opening. The third opening exposes a portion of the substrate and is connected to the first opening. The first light blocking structure is arranged on the second dielectric layer structure. The second light-blocking structure is arranged on the side wall of the third opening. The dielectric layer is arranged on the light blocking structure and in the third opening, and is provided with a fourth opening connected with the first opening. The pad layer is disposed on the dielectric layer and in the fourth opening, and is electrically connected to the conductive layer.
According to an embodiment of the present invention, in the semiconductor device, the first light blocking structure is not connected to the second light blocking structure.
According to an embodiment of the present invention, in the semiconductor device, the first light blocking structure and the second light blocking structure are metal grids.
According to an embodiment of the present invention, in the semiconductor device, the second light blocking structure and the pad layer are separated from each other.
In the semiconductor device according to an embodiment of the present invention, the second light blocking structure and the dielectric layer are disposed on a portion of the substrate.
In the semiconductor device according to an embodiment of the present invention, the dielectric layer in the third opening covers the second light blocking structure.
According to an embodiment of the present invention, in the semiconductor device, the pad layer is further disposed in the first opening and the second opening.
According to an embodiment of the present invention, in the semiconductor device, the second dielectric layer structure further has a fifth opening. The fifth opening exposes a portion of the substrate. The semiconductor assembly further includes a third light-blocking structure. The third light blocking structure is disposed in the fifth opening.
According to an embodiment of the present invention, in the semiconductor device, the first light blocking structure is connected to the third light blocking structure.
In view of the above, in the semiconductor device of the present invention, since the pad layer is formed after the light blocking structure is formed, the pad layer can be prevented from being damaged by the manufacturing process for forming the light blocking structure. In addition, the photomask can reduce the number of photomasks required by the manufacturing process of the semiconductor element through the manufacturing method of the semiconductor element, thereby reducing the production cost.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention;
fig. 2A to fig. 2G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.
Description of the symbols
100. 200: substrate
102. 104, 202, 204: dielectric layer structure
106. 206: conductive layer
108. 110, 116, 208, 212, 218: opening of the container
112. 214: light blocking structure
114. 216: dielectric layer
118. 220, and (2) a step of: connecting pad layer
210: patterned photoresist layer
S1, S3: first side
S2, S4: first side
W1, W2: width of
Detailed Description
Fig. 1A to fig. 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention.
Referring to fig. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. The substrate 100 may have a photosensitive element (not shown), such as a photodiode. The substrate 100 has a dielectric layer structure 102 on a first surface S1, a dielectric layer structure 104 on a second surface S2 of the substrate 100 opposite to the first surface S1, and a conductive layer 106 in the dielectric layer structure 102. In this embodiment, the first surface S1 is a front surface of the substrate 100, and the second surface S2 is a back surface of the substrate 100, but the invention is not limited thereto.
The dielectric layer structures 102, 104 may be a multi-layer structure or a single-layer structure. The material of the dielectric layer structures 102, 104 is, for example, silicon oxide, silicon nitride, a high dielectric constant material (e.g., hafnium oxide (HfO) or tantalum oxide (TaO)), or a combination thereof. One of ordinary skill in the art can select the number of layers and materials of the dielectric layer structure according to the product requirement.
In addition, although only the conductive layer 106 of the dielectric layer structure 102 is shown, the dielectric layer structure 102 may include other interconnect structures. The conductive layer 106 may be the interconnect structure closest to the substrate 100. The material of the conductor layer 106 is, for example, a metal such as aluminum, tungsten, or copper.
An opening 108 is formed in the dielectric layer structure 104 to expose the substrate 100 and to be located above the conductive layer 106. The opening 108 is formed, for example, by using a photolithographic etching process using a photomask. In addition, an opening 110 exposing the substrate 100 may be formed in the dielectric layer structure 104. The opening 110 and the opening 108 may be formed by the same photolithography and etching process.
Referring to fig. 1B, a light blocking structure 112 is formed on the dielectric layer structure 104. The light blocking structure 112 is, for example, a metal grid. In addition, the light blocking structure 112 may also be formed on the sidewall of the opening 108 and in the opening 110. The material of the light blocking structure 112 is, for example, a metal such as tungsten or aluminum. The light blocking structure 112 is formed, for example, by forming a light blocking material layer (not shown) on the dielectric layer structure 104 through a deposition process using a photomask, and then patterning the light blocking material layer through a photolithography and etching process using the photomask.
Referring to fig. 1C, a dielectric layer 114 is formed to cover the light blocking structure 112 and fill the opening 108. The material of the dielectric layer 114 is, for example, silicon oxide. The dielectric layer 114 is formed by, for example, chemical vapor deposition. In addition, a planarization process, such as a chemical mechanical polishing process, may be performed on the dielectric layer 114.
Referring to fig. 1D, an opening 116 exposing the conductive layer 106 is formed in the dielectric layer 114 and the substrate 100. Furthermore, the opening 116 may also extend into the dielectric layer structure 102. The opening 108 is formed by a photolithographic etching process using, for example, a photomask. Opening 116 and opening 108 (fig. 1A) may be formed by the same or different photomask. In this embodiment, the opening 116 and the opening 108 are formed by a photomask through different photomasks, but the invention is not limited thereto.
In another embodiment, in the case where the opening 116 and the opening 108 are formed by the same photomask, the etching process for forming the opening 116 may simultaneously etch at the position of the opening 110. In this case, the material of the light blocking structure 112 is preferably selected to have high etching resistance (e.g., aluminum) for the etching process, so as to prevent the light blocking structure 112 from being damaged during the etching process.
Referring to fig. 1E, a pad layer 118 electrically connected to the conductive layer 106 is formed in the opening 116. The material of the pad layer 118 is, for example, a metal such as aluminum, tungsten, or copper. The pad layer 118 is formed by, for example, forming a pad material layer (not shown) on the dielectric layer 114 through a deposition process using a photomask, and patterning the pad material layer through a photolithography process using the photomask.
Based on the above embodiments, in the method for manufacturing the semiconductor device, since the pad layer 118 is formed after the light blocking structure 112 is formed, the pad layer 118 is prevented from being damaged by a manufacturing process (e.g., an etching process) for forming the light blocking structure 112. In addition, the number of photomasks used in the manufacturing process of the semiconductor device can be reduced by the method for manufacturing the semiconductor device according to the above embodiment, and thus the cost can be reduced.
Fig. 2A to fig. 2G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.
Referring to fig. 2A, a substrate 200 is provided. The substrate 200 has a dielectric layer structure 202 on a first surface S3, a dielectric layer structure 204 on a second surface S4 of the substrate 200 opposite to the first surface S3, and a conductive layer 206 in the dielectric layer structure 202. For the substrate 200, the dielectric layer structure 202, the dielectric layer structure 204 and the conductive layer 206, reference is made to the description of the substrate 100, the dielectric layer structure 102, the dielectric layer structure 104 and the conductive layer 106 in fig. 1A, and the description is not repeated herein.
A patterned photoresist layer 210 having an opening 208 is formed on the dielectric layer structure 204. The opening 208 may have a width W1. The patterned photoresist layer 210 is formed by a photolithography process using, for example, a photomask.
Referring to fig. 2B, a trimming process may be performed on the patterned photoresist layer 210 to expand the width W1 of the opening 208 to a width W2, which is helpful for expanding a Critical Dimension (CD) of a subsequently formed pad layer. The trimming process includes, for example, a chemical trim process (chemical trim process) and a plasma trim process (plasma trim process)
Referring to fig. 2C, a portion of the dielectric layer structure 204 is removed by using the patterned photoresist layer 210 as a mask, and an opening 212 exposing the substrate 200 and located above the conductive layer 206 is formed in the dielectric layer structure 204. In this embodiment, the opening 212 is not formed at the same time as the opening 110 in FIG. 1A.
Next, the patterned photoresist layer 210 is removed. The patterned photoresist layer 210 is removed by, for example, a dry photoresist stripping method or a wet photoresist stripping method.
Referring to fig. 2D, a light blocking structure 214 is formed on the dielectric layer structure 204. The light blocking structure 214 is, for example, a metal grid. In addition, the light blocking structure 214 may also be formed on the sidewall of the opening 212. The material of the light blocking structure 214 is, for example, a metal such as tungsten or aluminum. The light blocking structure 214 is formed, for example, by forming a light blocking material layer (not shown) on the dielectric layer structure 204 through a deposition process using a photomask, and then patterning the light blocking material layer through a photolithography and etching process using the photomask.
Referring to fig. 2E, a dielectric layer 216 is formed to cover the light blocking structure 214 and fill the opening 212. The material of the dielectric layer 216 is, for example, silicon oxide. The dielectric layer 216 is formed by, for example, chemical vapor deposition. In addition, the dielectric layer 216 may be subjected to a planarization process, such as a chemical mechanical polishing process.
Referring to fig. 2F, an opening 218 is formed in the dielectric layer 216 and the substrate 200 to expose the conductive layer 206. Furthermore, the opening 218 may also extend into the dielectric layer structure 202. The opening 212 is formed by a photolithographic etching process using, for example, a photomask. Opening 218 and opening 212 (fig. 2C) may be formed with the same or different photomask. In this embodiment, the opening 218 and the opening 212 are formed by a photomask through the same photomask, but the invention is not limited thereto.
Referring to fig. 2G, a pad layer 220 electrically connected to the conductive layer 206 is formed in the opening 218. The material of the pad layer 220 is, for example, a metal such as aluminum, tungsten, or copper. The bonding pad layer 220 is formed, for example, by first forming a bonding pad material layer (not shown) on the dielectric layer 216 by a deposition process using a photomask, and then patterning the bonding pad material layer by a photolithography and etching process using the photomask.
Based on the above embodiments, in the method for manufacturing the semiconductor device, since the pad layer 220 is formed after the light blocking structure 214 is formed, the damage to the pad layer 220 caused by the fabrication process (e.g., etching process) for forming the light blocking structure 214 can be prevented. In addition, the number of photomasks used in the manufacturing process of the semiconductor device can be reduced by the method for manufacturing the semiconductor device according to the above embodiment, and thus the cost can be reduced.
In addition, the semiconductor device in the above embodiments is exemplified by a back side illumination (back side illumination) image sensor, but the invention is not limited thereto. The above-mentioned method for manufacturing semiconductor device can also be applied to the manufacture of front side illumination image sensor. The difference between the front-side illuminated image sensor and the back-side illuminated image sensor is as follows. In the front-side illuminated image sensor, the conductive layer connected to the pad layer may be the uppermost conductive layer on the front side of the substrate.
For example, in the embodiment where the semiconductor device is a front-side illuminated image sensor device, the method for manufacturing the semiconductor device includes the following steps. A substrate is provided. There is a dielectric layer structure on the substrate, and there is a conductive layer (e.g., the uppermost conductive layer) in the dielectric layer structure. A first opening is formed in the dielectric layer structure to expose the conductive layer. And forming a light blocking structure on the dielectric layer structure. A dielectric layer is formed to cover the light blocking structure and fill the first opening. A second opening is formed in the dielectric layer to expose the conductive layer. And forming a pad layer electrically connected to the conductor layer in the second opening.
In summary, in the manufacturing method of the semiconductor device in the above embodiments, the pad layer is formed after the light blocking structure is formed, so that the pad layer can be prevented from being damaged by the manufacturing process for forming the light blocking structure. In addition, the number of photomasks used in the manufacturing process of the semiconductor device can be reduced by the method for manufacturing the semiconductor device according to the embodiment, and the production cost can be reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (9)
1. A semiconductor assembly, comprising:
a substrate having a first face, a second face opposite to the first face, and a first opening;
a first dielectric layer structure disposed on the first surface and having a conductive layer and a second opening, wherein the second opening exposes the conductive layer and is connected to the first opening;
a second dielectric layer structure disposed on the second surface and having a third opening, wherein the third opening exposes a portion of the substrate and is connected to the first opening;
the first light blocking structure is arranged on the second dielectric layer structure;
the second light blocking structure is arranged on the side wall of the third opening;
a dielectric layer disposed on the light blocking structure and in the third opening, and having a fourth opening connected to the first opening; and
and a pad layer disposed on the dielectric layer and in the fourth opening and electrically connected to the conductive layer.
2. The semiconductor assembly of claim 1, wherein the first light blocking structure is not connected to the second light blocking structure.
3. The semiconductor device according to claim 1, wherein the first light blocking structure and the second light blocking structure are metal grids.
4. The semiconductor device of claim 1, wherein the second light blocking structure and the pad layer are separated from each other.
5. The semiconductor device of claim 1, wherein the second light blocking structure and the dielectric layer are disposed on the portion of the substrate.
6. The semiconductor device of claim 1, wherein the dielectric layer in the third opening covers the second light blocking structure.
7. The semiconductor device of claim 1, wherein the pad layer is further disposed in the first opening and in the second opening.
8. The semiconductor device of claim 1, wherein the second dielectric layer structure further has a fifth opening exposing a portion of the substrate, and further comprising:
and the third light blocking structure is arranged in the fifth opening.
9. The semiconductor assembly of claim 8, wherein the first light blocking structure is connected to the third light blocking structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211303585.5A CN115548042A (en) | 2018-05-11 | 2018-05-11 | Method for manufacturing semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211303585.5A CN115548042A (en) | 2018-05-11 | 2018-05-11 | Method for manufacturing semiconductor element |
| CN201810449833.4A CN110473886A (en) | 2018-05-11 | 2018-05-11 | The manufacturing method of semiconductor element |
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| CN201810449833.4A Division CN110473886A (en) | 2018-05-11 | 2018-05-11 | The manufacturing method of semiconductor element |
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| CN201810449833.4A Pending CN110473886A (en) | 2018-05-11 | 2018-05-11 | The manufacturing method of semiconductor element |
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| KR100672714B1 (en) * | 2004-07-20 | 2007-01-22 | 동부일렉트로닉스 주식회사 | Method for fabricating of CMOS Image sensor |
| CN100394545C (en) * | 2004-10-21 | 2008-06-11 | 力晶半导体股份有限公司 | Method for manufacturing semiconductor device |
| CN101079967B (en) * | 2006-02-24 | 2013-07-10 | 索尼株式会社 | Solid-state imaging device, method for producing same, and camera |
| CN100553004C (en) * | 2006-09-20 | 2009-10-21 | 财团法人工业技术研究院 | Ovonics unified memory and manufacture method thereof |
| CN100527356C (en) * | 2007-01-12 | 2009-08-12 | 联华电子股份有限公司 | Method for finishing hard mask layer, method for forming transistor grids, and stack structure |
| US20080237761A1 (en) * | 2007-04-02 | 2008-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for enhancing light sensitivity for backside illumination image sensor |
| CN101281871B (en) * | 2007-04-05 | 2011-11-09 | 联华电子股份有限公司 | Composite hard mask layer, metal-oxide-semiconductor transistor and manufacturing method thereof |
| CN101359619B (en) * | 2007-08-01 | 2011-01-19 | 联华电子股份有限公司 | Interconnecting process |
| KR101446330B1 (en) * | 2008-01-29 | 2014-10-02 | 삼성전자주식회사 | Image sensor having through via |
| US8431946B2 (en) * | 2010-05-26 | 2013-04-30 | Hsin-Chih CHIU | Chip package and method for forming the same |
| CN202796959U (en) * | 2012-09-27 | 2013-03-13 | 豪威科技(上海)有限公司 | Backside illuminated image sensor |
| CN104637961B (en) * | 2013-11-13 | 2018-09-11 | 联华电子股份有限公司 | Semiconductor structure and its manufacturing method |
| US9349767B2 (en) * | 2014-04-16 | 2016-05-24 | Semiconductor Components Industries, Llc | Image sensors with through-oxide via structures |
| TWI572024B (en) * | 2015-07-06 | 2017-02-21 | 力晶科技股份有限公司 | Semiconductor device and method of manufacturing the same |
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