CN115527924A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115527924A CN115527924A CN202110706315.8A CN202110706315A CN115527924A CN 115527924 A CN115527924 A CN 115527924A CN 202110706315 A CN202110706315 A CN 202110706315A CN 115527924 A CN115527924 A CN 115527924A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer and comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer; a top dielectric layer located on the bottom dielectric layer; the first metal wire penetrates through the top dielectric layer and is in contact with the conductive plug, and the first metal wire is used as a signal wire; the second metal wire penetrates through the second dielectric layer and the top dielectric layer and is in contact with the second interconnection layer, and the second metal wire is used as a power supply line, so that the power supply line is not required to be electrically connected with the second interconnection layer through a conductive plug, the influence of the resistance of the conductive plug on the electric connection performance between the power supply line and the second interconnection layer is favorably prevented, the electric connection performance between the power supply line and the second interconnection layer is optimized, the IR voltage drop is reduced, and the power supply efficiency of the device is improved.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are continuously reduced, and the circuit density inside the integrated circuits is increased, so that the wafer surface cannot provide enough area for manufacturing the required interconnection lines.
In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. As technology nodes advance, the size of interconnect structures also becomes smaller; accordingly, the difficulty of the process for forming the interconnect structure is increasing, and the quality of the formed interconnect structure has a great influence on the electrical performance of the back end of line (BEOL) and the reliability of the device, and may seriously affect the normal operation of the semiconductor device.
The metal lines typically include signal lines for transmitting signals and power supply lines for supplying power to the components in the chip.
However, the current devices are less efficient in powering.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve power supply efficiency of a device.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a bottom dielectric layer, the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, the interconnection layers comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer; a top dielectric layer located on the bottom dielectric layer; the first metal wire penetrates through the top dielectric layer at the top of the conductive plug and is in contact with the conductive plug, and the first metal wire is used as a signal wire; and the second metal wire penetrates through the second dielectric layer and the top dielectric layer at the top of the second interconnection layer and is in contact with the second interconnection layer, and the second metal wire is used as a power supply wire.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a bottom dielectric layer, the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, the interconnection layers comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer; forming a top dielectric layer on the bottom dielectric layer; forming a first interconnection groove penetrating through the top dielectric layer on the top of the conductive plug, and a second interconnection groove penetrating through a second dielectric layer on the top of the second interconnection layer and the top dielectric layer, wherein the first interconnection groove exposes the conductive plug, and the second interconnection groove exposes the second interconnection layer; and filling a conductive material in the first interconnection groove and the second interconnection groove, and correspondingly forming a first metal wire and a second metal wire respectively, wherein the first metal wire is in contact with the conductive plug and is used as a signal wire, and the second metal wire is in contact with the second interconnection layer and is used as a power supply wire.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, the first metal wire is in contact with the conductive plug and is used as a signal wire, and the second metal wire is in contact with the second interconnection layer and is used as a power supply wire, so that the power supply wire is not required to be electrically connected with the second interconnection layer through the conductive plug, the influence of the resistance of the conductive plug on the electrical connection performance between the power supply wire and the second interconnection layer is favorably prevented, the electrical connection performance between the power supply wire and the second interconnection layer is optimized, the IR drop (IR drop) is reduced, and the power supply efficiency of a device is improved.
In the method for forming a semiconductor structure according to the embodiment of the present invention, in the step of forming the first interconnection groove and the second interconnection groove, the first interconnection groove penetrates through the top dielectric layer on the conductive plug, the second interconnection groove penetrates through the second dielectric layer and the top dielectric layer on the top of the second interconnection layer, and the second interconnection groove exposes the second interconnection layer, that is, the second interconnection groove has a larger depth than that of the first interconnection groove, and the first interconnection groove and the second interconnection groove are filled with a conductive material, which correspond to the step of forming the first metal line and the second metal line, respectively, the first metal line is in contact with the conductive plug and is used as a signal line, and the second metal line is in contact with the second interconnection layer and is used as a signal line, so that the power supply line and the second interconnection layer do not need to be electrically connected through the conductive plug, which is beneficial to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnection layer, optimizing the electrical connection performance between the power supply line and the second interconnection layer, reducing the IR drop (IR drop), and improving the power supply efficiency of the device.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 3 to 9 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the power supply efficiency of the current devices is low. The reason why the power supply efficiency of a semiconductor structure analysis device is low is now combined. Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, the semiconductor structure includes: the substrate 10 comprises a substrate (not shown), a gate structure (not shown) located on the substrate, source-drain doped regions 11 located on two sides of the gate structure, and a first dielectric layer 12 located on the substrate and covering the source-drain doped regions 11, wherein a plurality of source-drain interconnection layers which are in contact with the source-drain doped regions 11 are formed in the first dielectric layer 12, and the plurality of source-drain interconnection layers comprise a first source-drain interconnection layer 13 and a second source-drain interconnection layer 14; the second dielectric layer 15 is positioned on the first dielectric layer 12 and covers the source-drain interconnection layer; the conductive plugs are positioned in the second dielectric layer 15 and are in contact with the source-drain interconnection layers, and the conductive plugs comprise first conductive plugs 16 in contact with the first source-drain interconnection layers 13 and second conductive plugs 17 in contact with the second source-drain interconnection layers 14; a third dielectric layer 18 located on the second dielectric layer 15 and covering the conductive plug; and the metal wires are positioned in the third dielectric layer 18 and comprise signal wires 19 (1) contacted with the first conductive plugs 16 and power supply wires 19 (2) contacted with the second conductive plugs 17, and the line width of the power supply wires 19 (2) is greater than that of the signal wires 19 (1).
In the semiconductor structure, the line width of the power supply line 19 (2) is larger than that of the signal line 19 (1) to reduce the resistance of the power supply line 19 (2), thereby reducing the IR drop (IR drop). Moreover, the power supply line 19 (2) and the signal line 19 (1) are formed in the same process step, and both the power supply line 19 (2) and the signal line 19 (1) need to be electrically connected to the corresponding source-drain interconnection layer through a conductive plug.
However, the power supply line 19 (2) is used to supply power to the source/drain doped region 11 through the source/drain interconnection layer, and the power supply line 19 (2) and the source/drain interconnection layer are electrically connected through a conductive plug, which may reduce the power supply efficiency of the device due to the resistance of the conductive plug.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a bottom dielectric layer, the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, the interconnection layers comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer; a top dielectric layer located on the bottom dielectric layer; the first metal wire penetrates through the top dielectric layer at the top of the conductive plug and is in contact with the conductive plug, and the first metal wire is used as a signal wire; and the second metal wire penetrates through the second dielectric layer and the top dielectric layer at the top of the second interconnection layer and is in contact with the second interconnection layer, and the second metal wire is used as a power supply wire.
In the semiconductor structure provided by the embodiment of the invention, the first metal wire is in contact with the conductive plug and is used as a signal wire, and the second metal wire is in contact with the second interconnection layer and is used as a power supply wire, so that the power supply wire is not required to be electrically connected with the second interconnection layer through the conductive plug, the influence of the resistance of the conductive plug on the electrical connection performance between the power supply wire and the second interconnection layer is favorably prevented, the electrical connection performance between the power supply wire and the second interconnection layer is optimized, the IR drop (IR drop) is reduced, and the power supply efficiency of a device is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Referring to fig. 2, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
As shown in fig. 2, in the present embodiment, the semiconductor structure includes: the substrate 100, the substrate 100 includes a bottom dielectric layer 101, the bottom dielectric layer 101 includes a first dielectric layer 130 and a second dielectric layer 150 located on the first dielectric layer 130, a plurality of interconnection layers are formed in the first dielectric layer 130, the interconnection layers include a first interconnection layer 170 and a second interconnection layer 180 which are spaced apart from each other, and a conductive plug 160 which is in contact with the first interconnection layer 170 is formed in the second dielectric layer 150 on the top of the first interconnection layer 170; a top dielectric layer 102 located on the bottom dielectric layer 101; a first metal line 210 penetrating through the top dielectric layer 102 on top of the conductive plug 160 and contacting the conductive plug 160, the first metal line 210 being used as a signal line; a second metal line 220 penetrating through the second dielectric layer 150 and the top dielectric layer 102 on top of the second interconnect layer 180 and contacting the second interconnect layer 180, the second metal line 220 being used as a Power rail (Power rail).
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
According to the actual process conditions, the base 100 includes a substrate and a functional structure formed on the substrate, for example: the functional structure may include a semiconductor device such as a MOS field effect transistor, a resistive structure, a conductive structure, and the like.
Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) located on the substrate, and source-drain doped regions 140 located at two sides of the gate structure. The gate structure and the source-drain doped regions 140 located at both sides of the gate structure are used to form a MOS transistor.
The substrate provides a process platform for the formation of the transistor. The material of the substrate comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
The gate structure is used to enable the conduction channel of the transistor to be turned on and off. The gate structure comprises the following materials: any one or more of TiAl, tiALC, taAlN, tiAlN, moN, taCN, alN, ta, tiN, taN, taSiN, tiSiN, W, co, al, cu, ag, au, pt and Ni.
In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) between the gate structure and the channel structure 110. The gate dielectric layer is used for realizing electric isolation between the gate structure and the channel structure.
In this embodiment, the gate dielectric layer includes: hfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 、Al 2 O 3 Silicon oxide and nitrogen-doped silicon oxide.
The source and drain doped regions 140 are used as the source or drain of the transistor. As an example, when forming a PMOS transistor, the source/drain doped region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source/drain doped region 140 includes a stress layer doped with N-type ions, and the stress layer is made of Si or SiC.
As an embodiment, the substrate 100 further includes a protrusion 105 separated from the substrate, a channel structure 110 located on the protrusion 105, and an isolation layer 115 located on the substrate and surrounding the protrusion 105; the gate structure is located on the isolation layer 115 and crosses the channel structure 110; the source-drain doped region 140 is located in the channel structure 110 at two sides of the gate structure.
The channel structure 110 is used to provide a conduction channel of a field effect transistor. The materials of the raised portion 105 and the channel structure 110 include: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
In the present embodiment, the channel structure 110 is a fin, and the gate structure correspondingly crosses over the fin and covers a portion of the top and a portion of the sidewall of the fin. Specifically, the fin is connected to the protrusion 105. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the channel structure layer includes one or more channel layers disposed at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layers.
The isolation layer 115 serves to isolate adjacent raised portions 105 and also serves to isolate the substrate from the gate structure. The isolation layer 115 exposes the channel structure 110. The material of the isolation layer 115 is an insulating material, for example: one or more of silicon oxide, silicon oxynitride, and silicon nitride.
In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source-drain doped region 140. Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115.
The bottom dielectric layer 101 is a laminated structure or a single-layer structure. In this embodiment, the bottom dielectric layer 101 is taken as an example of a stacked structure.
In the bottom dielectric layer 101, the first dielectric layer 130 is used for realizing electrical isolation between interconnection layers, and the second dielectric layer 150 is used for realizing electrical isolation between the conductive plugs 160.
The materials of the first dielectric layer 130 and the second dielectric layer 150 are dielectric materials, such as: siOCH, siOC, siO 2 One or more of FSG, BSG, PSG and BPSG. As an example, the material of the first dielectric layer 130 is silicon oxide. As an example, the material of the second dielectric layer 180 is silicon oxide.
The interconnect layer is used to make electrical connections between functional structures within the substrate 100 and external circuitry or other interconnect structures. The number of the interconnection layers is plural, so that it is possible to electrically connect a plurality of functional structures within the substrate 100 with an external circuit or other interconnection structures.
The material of the interconnection layer is a conductive material, and the material of the interconnection layer comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN. As an example, the material of the interconnect layer is Cu. The resistivity of Cu is low, which is beneficial to reducing RC delay in the back-end process, and Cu has excellent electromigration resistance.
As an embodiment, the interconnection layer is located in the first dielectric layer 130 on the top of the source-drain doped region 140, and is in contact with the source-drain doped region 140. That is, the interconnection layer serves as a source-drain interconnection layer for realizing electrical connection between the source-drain doped region 140 and an external circuit or an interconnection structure.
In other implementations, the interconnect layer may also be other types of interconnect layers for achieving electrical connection between other components and external circuits or interconnect structures, according to actual process requirements.
In this embodiment, for convenience of illustration and description, only two device regions in the substrate 100 are illustrated, each device region is correspondingly formed with an MOS transistor, and accordingly, the first interconnection layer 170 and the second interconnection layer 180 are respectively used for realizing electrical connection between the source-drain doped regions 140 of the two device regions and an external circuit or other interconnection structures.
The conductive plugs 160 are used to electrically connect the interconnect layer to an external circuit or other interconnect structure. Specifically, in the present embodiment, the conductive plug 160 is used to electrically connect the first interconnect layer 170 with an external circuit or other interconnect structures.
The material of the conductive plug 160 is a conductive material. The conductive plug 160 is made of a conductive material, and the conductive plug 160 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN.
The top dielectric layer 102 is used to achieve electrical isolation between metal lines. The top dielectric layer 102 covers the conductive plug 160.
The material of the top dielectric layer 102 is a dielectric material. The material of the top dielectric layer 102 may include SiOCH, siOC, siO 2 One or more of FSG, BSG, PSG and BPSG. Specifically, the material of the top dielectric layer 102 may be a low-k dielectric material or an ultra-low-k dielectric material, so that the capacitance between the metal lines may be effectively reduced, and the RC delay of the device may be reduced. As an example, the material of the top dielectric layer 102 is silicon hydroxide.
The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnect layer 170, so that the first metal line 210 is used to electrically connect the source-drain doped region 140 with an external circuit or other interconnect structures. In this embodiment, the first metal line 210 is used as a signal line for realizing signal connection between the source-drain doped region 140 and an external circuit or other interconnection structures.
The second metal line 220 is in contact with the second interconnection layer 180, and the second interconnection layer 180 is in contact with the source-drain doped region 140, so that the second metal line 220 is used for realizing electrical connection between the source-drain doped region 140 and an external circuit or other interconnection structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source/drain doped region 140.
The second metal line 220 is in contact with the second interconnect layer 180 and is used as a power supply line, so that the power supply line and the second interconnect layer 180 are not required to be electrically connected through the conductive plug 160, which is beneficial to preventing the resistance of the conductive plug from influencing the electrical connection performance between the power supply line and the second interconnect layer 180, optimizing the electrical connection performance between the power supply line and the second interconnect layer 180, reducing an IR drop (IR drop), and improving the power supply efficiency of the device.
In addition, in this embodiment, the line width of the second metal line 220 is greater than the line width of the first metal line 210, that is, the line width of the power supply line is greater than the line width of the signal line, which is beneficial to reducing the resistance of the power supply line, reducing IR drop, and further improving the power supply efficiency of the device.
The material of the first metal line 210 and the second metal line 220 is conductive material. As an example, the material of the first metal line 210 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN; the material of the second metal line 220 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN.
The first metal line 210 may include a first diffusion preventing barrier layer (not shown) on sidewalls and a bottom of the first interconnection groove 230, and a first metal layer (not shown) on the first diffusion preventing barrier layer and filling the first interconnection groove; the second metal line 220 may include a second diffusion preventing barrier layer (not shown) on sidewalls and a bottom of the second interconnection groove 240, and a second metal layer (not shown) on the second diffusion preventing barrier layer and filling the second interconnection groove.
In this embodiment, the first metal line 210 and the second metal line 220 are formed in the same step, so that the structure of the first metal line 210 is the same as that of the second metal line 220, and the material of the first metal line 210 is the same as that of the second metal line 220.
Specifically, in this embodiment, the material of the first diffusion barrier layer is the same as the material of the second diffusion barrier layer, and the materials of the first metal layer and the second metal layer are the same.
As an example, the material of the first anti-diffusion barrier layer and the material of the second anti-diffusion barrier layer are both TiN; the first metal layer and the second metal layer are made of Cu, the resistivity of the Cu is low, RC delay in a back-end process can be reduced, and the Cu has excellent electromigration resistance.
The number of the first metal lines 210 may be one or more. The number of the second metal lines 220 may be one or more. It should be noted that, in an actual process, when the number of the second metal lines 220 is plural, based on an actual pattern of the interconnect layer and the metal lines, a part of the second metal lines 220 may not contact with the second interconnect layer 180.
Correspondingly, the invention also provides a forming method of the semiconductor structure. Fig. 3 to 9 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
The method for forming the semiconductor structure of the present embodiment is described in detail below with reference to the accompanying drawings.
Referring to fig. 3, a substrate 100 is provided, where the substrate 100 includes a bottom dielectric layer 101, the bottom dielectric layer 101 includes a first dielectric layer 130 and a second dielectric layer 150 located on the first dielectric layer 130, a plurality of interconnection layers are formed in the first dielectric layer 130, and include a first interconnection layer 170 and a second interconnection layer 180 which are spaced apart from each other, and a conductive plug 160 which is in contact with the first interconnection layer 170 is formed in the second dielectric layer 180 on top of the first interconnection layer 170.
The substrate 100 is used to provide a process platform for subsequent process steps.
According to the actual process conditions, the base 100 includes a substrate and a functional structure formed on the substrate, for example: the functional structure may include a semiconductor device such as a MOS field effect transistor, a resistive structure, a conductive structure, and the like.
Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) located on the substrate, and source-drain doped regions 140 located at two sides of the gate structure. The gate structure and the source-drain doped regions 140 located at both sides of the gate structure are used to form a MOS transistor.
The substrate provides a process platform for the formation of the transistor. The material of the substrate comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium
The gate structure is used to enable the conduction channel of the transistor to be turned on and off. The gate structure comprises the following materials: any one or more of TiAl, tiALC, taAlN, tiAlN, moN, taCN, alN, ta, tiN, taN, taSiN, tiSiN, W, co, al, cu, ag, au, pt and Ni.
In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) between the gate structure and the channel structure 110. The gate dielectric layer is used for realizing electric isolation between the gate structure and the channel structure.
The gate dielectric layer comprises the following materials: hfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 、Al 2 O 3 Silicon oxide and nitrogen-doped silicon oxide.
The source and drain doped regions 140 are used to serve as the source or drain of the transistor. As an example, when forming a PMOS transistor, the source/drain doped region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain doped region 140 includes a stress layer doped with N-type ions, and the stress layer is made of Si or SiC.
As an embodiment, the substrate 100 further includes a protrusion 105 separated from the substrate, a channel structure 110 located on the protrusion 105, and an isolation layer 115 located on the substrate and surrounding the protrusion 105; the gate structure is located on the isolation layer 115 and crosses the channel structure 110; the source-drain doped region 140 is located in the channel structure 110 at two sides of the gate structure.
The channel structure 110 is used to provide a conduction channel of a field effect transistor. The materials of the protrusion 105 and the channel structure 110 include: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
In the present embodiment, the channel structure 110 is a fin, and the gate structure correspondingly crosses over the fin and covers a portion of the top and a portion of the sidewall of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the channel structure layer includes one or more channel layers disposed at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layers.
The isolation layer 115 serves to isolate adjacent raised portions 105 and also serves to isolate the substrate from the gate structure. The isolation layer 115 exposes the channel structure 110. The material of the isolation layer 115 is an insulating material, for example: one or more of silicon oxide, silicon oxynitride, and silicon nitride.
In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source-drain doped region 140. Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115.
The bottom dielectric layer 101 is a laminated structure or a single-layer structure. In this embodiment, the bottom dielectric layer 101 is taken as an example of a stacked structure for explanation.
In the bottom dielectric layer 101, the first dielectric layer 130 is used to realize electrical isolation between the interconnection layers, and the second dielectric layer 150 is used to realize electrical isolation between the conductive plugs 160.
The materials of the first dielectric layer 130 and the second dielectric layer 150 are dielectric materials, such as: siOCH, siOC, siO 2 One or more of FSG, BSG, PSG and BPSG. As an example, the material of the first dielectric layer 130 is silicon oxide. As an example, the material of the second dielectric layer 180 is silicon oxide.
The interconnect layer is used to electrically connect functional structures within the substrate 100 to external circuitry or other interconnect structures. The number of the interconnection layers is plural, so that the plurality of functional structures in the substrate 100 can be electrically connected to an external circuit or other interconnection structures.
The material of the interconnection layer is a conductive material, and the material of the interconnection layer comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN. As an example, the material of the interconnect layer is Cu. The resistivity of Cu is lower, which is beneficial to reducing RC delay in the back-end process, and Cu has excellent electromigration resistance.
As an embodiment, the interconnection layer is located in the first dielectric layer 130 on the top of the source-drain doped region 140, and is in contact with the source-drain doped region 140. That is, the interconnection layer serves as a source-drain interconnection layer for realizing electrical connection between the source-drain doped region 140 and an external circuit or an interconnection structure.
In other implementations, the interconnect layer may also be other types of interconnect layers for making electrical connections between other components and external circuits or interconnect structures, depending on the actual process requirements.
In this embodiment, for convenience of illustration and description, only two device regions in the substrate 100 are illustrated, each device region is correspondingly formed with an MOS transistor, and accordingly, the first interconnection layer 170 and the second interconnection layer 180 are respectively used for realizing electrical connection between the source-drain doped regions 140 of the two device regions and an external circuit or other interconnection structures.
The conductive plug 160 is used to electrically connect the interconnect layer to an external circuit or other interconnect structure. Specifically, in this embodiment, the conductive plug 160 is used to electrically connect the first interconnect layer 170 with an external circuit or other interconnect structures.
The material of the conductive plug 160 is a conductive material. The material of the conductive plug 160 is a conductive material, and the material of the conductive plug 160 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN.
With continued reference to fig. 3, a top dielectric layer 102 is formed on the bottom dielectric layer 101. The top dielectric layer 102 covers the conductive plug 160.
A plurality of metal lines are subsequently formed in the top dielectric layer 102, and the top dielectric layer 102 is used for realizing electrical isolation between the metal lines.
The material of the top dielectric layer 102 is a dielectric material. The material of the top dielectric layer 102 may include SiOCH, siOC, siO 2 One or more of FSG, BSG, PSG and BPSG. Specifically, the material of the top dielectric layer 102 may be a low-k dielectric material or an ultra-low-k dielectric material, so that the capacitance between the metal lines may be effectively reduced, and the RC delay of the device may be reduced. As an example, the material of the top dielectric layer 102 is silicon hydroxide.
Referring to fig. 4 to 8, a first interconnection trench 230 is formed through the top dielectric layer 102 on top of the conductive plug 160, the first interconnection trench 230 exposing the conductive plug 160, and a second interconnection trench 240 is formed through the second dielectric layer 150 on top of the second interconnection layer 180 and the top dielectric layer 102 (as shown in fig. 7), the second interconnection trench 240 exposing the second interconnection layer 180.
The first interconnection groove 230 is used to provide a spatial location for forming the first metal line.
The first interconnection groove 230 penetrates through the top dielectric layer 102 on the top of the conductive plug 160 and exposes the conductive plug 160, so that the subsequent first metal line can contact the conductive plug 160.
The second interconnection groove 240 serves to provide a spatial location for forming the second metal line.
A second interconnect trench 240 extends through the second dielectric layer 150 and the top dielectric layer 102 on top of the second interconnect layer 180 and exposes the second interconnect layer 180 so that a subsequent second metal line can contact the second interconnect layer 180.
Moreover, in this embodiment, the first metal line is used as a signal line, the second metal line is used as a power supply line, and the second interconnection groove 240 penetrates through the second dielectric layer 150 and the top dielectric layer 102 on the top of the second interconnection layer 180 and exposes the second interconnection layer 180, so that the subsequent power supply line is in direct contact with the second interconnection layer 180, and the power supply line and the second interconnection layer 180 are electrically connected without a conductive plug, which is beneficial to preventing the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnection layer 180, optimizing the electrical connection performance between the power supply line and the second interconnection layer 180, reducing an IR drop (IR drop), and improving the power supply efficiency of the device.
In this embodiment, the opening line width of the second interconnection groove 240 is greater than the opening line width of the first interconnection groove 230, and accordingly, after a first metal line is formed in the first interconnection groove 230 and a second metal line is formed in the second interconnection groove 240, the line width of the second metal line is greater than the line width of the first metal line, that is, compared with the line width of a signal line, the line width of the power supply line is greater, which is beneficial to reducing the resistance of the power supply line and reducing IR drop, thereby improving the power supply efficiency of the device.
The number of the first interconnection grooves 230 may be one or more. The number of the second interconnection grooves 240 may be one or more. It should be noted that, in an actual process, when the number of the second interconnection grooves 240 is plural, based on an actual pattern of the interconnection layer and the interconnection grooves, a part of the second interconnection grooves 240 may not expose the second interconnection layer 180.
The steps of forming the first interconnection groove 230 and the second interconnection groove 240 according to this embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 4, a plurality of trenches penetrating the top dielectric layer 102 are formed, including a first interconnection trench 230 on top of the conductive plug 160 and exposing the conductive plug 160, and a first preliminary trench 260 over the second interconnection layer 180, the first preliminary trench 260 exposing the second dielectric layer 102.
In this embodiment, the opening line width of the first initial trench 260 is greater than the opening line width of the first interconnection groove 230, so as to form a second initial trench penetrating through the second dielectric layer 102 at the bottom of the first initial trench 260, and the opening line width of the second interconnection groove formed by the second initial trench and the first initial trench 260 is greater, so that the line width of a second metal line subsequently formed in the second interconnection groove is correspondingly greater.
Specifically, in this embodiment, the step of forming a plurality of trenches penetrating through the top dielectric layer 102 includes: forming a hard mask layer 250 on the top dielectric layer 102, wherein a plurality of mask openings (not labeled) are formed in the hard mask layer 250; and etching the top dielectric layer 102 along the mask opening by taking the hard mask layer 250 as a mask to form a plurality of grooves penetrating through the top dielectric layer 102.
The hard mask layer 250 is used as an etch mask for forming the trench. The mask openings are used to define the size, shape and location of the trenches.
The hard mask layer 250 is made of a material having an etching selectivity with the materials of the top dielectric layer 102 and the bottom dielectric layer 101, so that the hard mask layer 250 can play a role of etching a mask.
In one embodiment, the hard mask layer 250 is made of titanium nitride.
In this embodiment, the hard mask layer 250 is used as a mask, and an anisotropic etching process is used to etch the top dielectric layer 102 along the mask opening, so as to form a plurality of trenches. The anisotropic etching process is beneficial to providing the precision of pattern transfer, and further improves the section controllability of the groove and the dimensional precision of the groove. Specifically, the anisotropic etching process may be an anisotropic dry etching process.
Referring to fig. 5 to 8, a second preliminary trench 270 penetrating the second dielectric layer 102 at the bottom of the first preliminary trench 260 is formed, the second preliminary trench 270 exposing the second interconnect layer 180, and the second preliminary trench 270 and the first preliminary trench 260 are used to form the second interconnect trench 240.
The second preliminary trench 270 is formed such that the depth of the second interconnection groove is increased to enable the second interconnection groove to expose the second interconnection layer 180.
As an embodiment, the step of forming the second preliminary trench 270 includes:
as shown in fig. 5, a sacrificial layer 245 is formed on the bottom and the sidewall of the trench, and the sacrificial layer 245 on the sidewall of the first interconnection groove 230 contacts and fills the first interconnection groove 230, and the sidewall of the sacrificial layer 245 on the sidewall of the first initial trench 260 is separated.
The sacrificial layer 245 is used for forming a shielding layer located in the first interconnection groove 230 through a subsequent etching process, so that the shielding layer can shield and protect the second dielectric layer 150 at the bottom of the first interconnection groove 230 in a subsequent etching process of the second dielectric layer 150 at the bottom of the first initial groove 260.
In this embodiment, the sacrificial layer 245 fills the first interconnect trench 230, and the sidewalls of the sacrificial layer 245 at the sidewalls of the first initial trench 260 are discrete, that is, the sacrificial layer 245 at the sidewalls of the first initial trench 260 is thinner in a direction perpendicular to the sidewalls or the bottom of the first initial trench 260, and the sacrificial layer 245 in the first interconnect trench 230 is thicker in the direction perpendicular to the bottom of the first interconnect trench 230 due to the contact, so that during the subsequent etching process of the sacrificial layer 245, the sacrificial layer 245 in the first interconnect trench 230 can be removed while the sacrificial layer 245 in the first initial trench 260 is removed, and the sacrificial layer 245 in the first interconnect trench 230 can also remain a partial thickness to serve as the shielding layer.
In this embodiment, since the opening line width of the first preliminary trench 260 is greater than the opening line width of the first interconnection trench 230, in the process of forming the sacrificial layer 245, as the thickness of the sacrificial layer 245 material on the bottom and the sidewall of the trench gradually increases, the sacrificial layer 245 material on the opposite sidewall of the first interconnection trench 230 gradually contacts, and the sidewalls of the sacrificial layer 245 on the opposite sidewall of the first preliminary trench 260 are still separated from each other by controlling the thickness of the sacrificial layer 245 to be less than 0.5 times the opening line width of the first preliminary trench 260.
In this embodiment, the sacrificial layer 245 is also formed on the top and sidewalls of the hard mask layer 250.
The sacrificial layer 245 is made of a material having an etching selectivity with the top dielectric layer 102 and the bottom dielectric layer 101, so that after the sacrificial layer 245 is subsequently etched to form the shielding layer, the shielding layer can protect and shield the second dielectric layer 150 at the bottom of the first interconnection groove 230.
In addition, after the second initial trench is formed subsequently, the sacrificial layer 245 needs to be removed, and the sacrificial layer 245 is made of a material which is easy to remove, so that the difficulty of removing the sacrificial layer 245 subsequently is reduced, the process compatibility is improved, and the probability of damage to other film structures (such as a top dielectric layer and a bottom dielectric layer) caused by the process for removing the sacrificial layer 245 is reduced.
In this embodiment, the material of the sacrificial layer 245 includes amorphous carbon or amorphous germanium.
As an example, the material of the sacrificial layer 245 is amorphous carbon. Amorphous carbon is the material of easy acquisition, is favorable to reducing the formation the process cost of sacrificial layer 245, moreover, amorphous carbon is follow-up can get rid of through oxidation process, is favorable to reducing follow-up getting rid of the process operation degree of difficulty of sacrificial layer 245 has simplified process flow, has improved technology manufacturing efficiency, but also is favorable to reducing the influence of sacrificial layer 245 to follow-up process procedure and semiconductor structure.
In this embodiment, forming the sacrificial layer 245 includes a Chemical Vapor Deposition (CVD) process. The chemical vapor deposition process has the advantages of good covering capability, strong process compatibility and low process cost.
In other embodiments, the sacrificial layer 245 may be formed by other processes based on the material of the sacrificial layer and the actual process requirements.
As shown in fig. 6, the sacrificial layer 245 is etched to remove the sacrificial layer 245 on the sidewall and the bottom of the first initial trench 260, and the sacrificial layer 245 filled in the first interconnection trench 230 is used as a shielding layer 265.
In the subsequent etching process of the second dielectric layer 150 at the bottom of the first initial trench 260, the shielding layer 265 is used for shielding and protecting the second dielectric layer 150 at the bottom of the first interconnection trench 230.
In this embodiment, an isotropic etching process is used to etch the sacrificial layer 245.
The isotropic etching process has a characteristic of isotropic etching, and can etch the sacrificial layer 245 at the sidewall and bottom of the first preliminary trench 260. Moreover, in this embodiment, since the sacrificial layers 245 on the sidewalls of the first initial trenches 260 are separated from each other, and the sacrificial layer 245 in the first interconnection groove 230 fills the first interconnection groove 230, the isotropic etching process can remove the sacrificial layer 245 in the first initial trenches 260 while the sacrificial layer 245 in the first interconnection groove 230 can remain a partial thickness for use as the shielding layer 265.
In addition, in the embodiment, a photomask or a mask is not required to be used in the process of forming the blocking layer 265, which is beneficial to saving the process cost and simplifying the process flow.
Specifically, the isotropic etching process may be one or both of an isotropic dry etching process and an isotropic wet etching process.
As shown in fig. 7, the second dielectric layer 150 at the bottom of the first initial trench 260 is etched by using the blocking layer 265 as a mask, a second initial trench 270 exposing the second interconnect layer 180 is formed below the first initial trench 260, and the second initial trench 270 and the first initial trench 260 form the second interconnect trench 240. The second preliminary grooves 270 communicate with the first preliminary grooves 260.
In this embodiment, the process of etching the second dielectric layer 150 at the bottom of the first initial trench 260 includes an anisotropic etching process. The anisotropic etching process is beneficial to improving the precision of pattern transfer, and further improves the profile morphology quality and the dimensional precision of the second initial trench 270.
As shown in fig. 8, after forming the second preliminary trench 270 and before filling the first and second interconnection trenches 230 and 240 with a conductive material, the method for forming a semiconductor structure further includes: the blocking layer 265 is removed.
The shielding layer 265 is removed to expose the space of the first interconnection groove 230, so that the first interconnection groove 230 can be filled with a conductive material later.
In this embodiment, the material of the blocking layer 265 is amorphous carbon, and the sacrificial layer 124 is removed by an oxidation process. The oxygen-containing gas in the oxidation process can react with the amorphous carbon material to generate carbon dioxide gas so as to be discharged out of the reaction cavity, the removal process is simple, the process compatibility is high, the side effect is small, and the reduction of the process cost and the improvement of the production capacity are facilitated.
In other embodiments, when the material of the sacrificial layer is amorphous germanium, a wet etching process is used to remove the sacrificial layer. Specifically, the wet etching process is performed using HCl vapor. In other implementations, when the material of the sacrificial layer is other materials, the sacrificial layer is removed by a suitable process.
In this embodiment, after forming the second preliminary trench 270, the forming of the semiconductor structure further includes: the hard mask layer 250 is removed. The hard mask layer 250 is removed to reduce the thickness of the subsequent conductive material to be filled, thereby reducing the filling difficulty of the subsequent conductive material.
It should be noted that the above step of forming the second preliminary trench 270 is only an example. The step of forming the second preliminary trench 270 is not limited thereto. For example: in other embodiments, the step of forming the second preliminary trench includes: forming a patterning layer on the top dielectric layer, wherein the patterning layer fills the first interconnection layer and exposes the first initial groove; and etching the second dielectric layer at the bottom of the first initial groove by taking the patterning layer as a mask.
It should be noted that, in this embodiment, the second interconnection groove is formed by forming the first interconnection groove and the first initial groove, and then forming the second initial groove communicated with the first initial groove. That is, in the present embodiment, the first and second interconnection grooves are formed in different steps, respectively. The process steps of forming the first interconnection groove and the second interconnection groove are not limited thereto.
In other embodiments, the first and second interconnection grooves may also be formed in the same step, based on the actual process.
Referring to fig. 9, a conductive material is filled in the first interconnection groove 230 and the second interconnection groove 240, and a first metal line 210 and a second metal line 220 are respectively formed, where the first metal line 210 contacts the conductive plug 160 and serves as a signal line, and the second metal line 220 contacts the second interconnection layer 180 and serves as a Power rail (Power rail).
The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnect layer 170, so that the first metal line 210 is used for realizing electrical connection between the source-drain doped region 140 and an external circuit or other interconnect structures. In this embodiment, the first metal line 210 is used as a signal line for realizing signal connection between the source-drain doped region 140 and an external circuit or other interconnection structures.
The second metal wire 220 is in contact with the second interconnection layer 180, and the second interconnection layer 180 is in contact with the source-drain doped region 140, so that the second metal wire 220 is used for realizing electrical connection between the source-drain doped region 140 and an external circuit or other interconnection structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source/drain doped region 140.
The second metal line 220 is in contact with the second interconnect layer 180 and is used as a power supply line, so that the power supply line and the second interconnect layer 180 are not required to be electrically connected through the conductive plug 160, which is beneficial to preventing the resistance of the conductive plug from influencing the electrical connection performance between the power supply line and the second interconnect layer 180, optimizing the electrical connection performance between the power supply line and the second interconnect layer 180, reducing an IR drop (IR drop), and improving the power supply efficiency of the device.
In this embodiment, the opening line width of the second interconnection groove 240 is greater than the opening line width of the first interconnection groove 230, and accordingly, the line width of the second metal line 220 is greater than the line width of the first metal line 210, that is, the line width of the power supply line is greater than the line width of the signal line, which is advantageous for reducing the resistance of the power supply line, reducing IR drop, and further improving the power supply efficiency of the device.
The first metal line 210 and the second metal line 220 are both made of conductive materials. As an example, the material of the first metal line 210 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN; the material of the second metal line 220 includes one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN.
The first metal line 210 may include a first diffusion preventing barrier layer (not shown) on sidewalls and a bottom of the first interconnection trench 230, and a first metal layer (not shown) on the first diffusion preventing barrier layer and filling the first interconnection trench; the second metal line 220 may include a second diffusion preventing barrier layer (not shown) on sidewalls and a bottom of the second interconnection groove 240, and a second metal layer (not shown) on the second diffusion preventing barrier layer and filling the second interconnection groove.
In this embodiment, the first metal line 210 and the second metal line 220 are formed in the same step, so the structure of the first metal line 210 is the same as that of the second metal line 220, and the material of the first metal line 210 is the same as that of the second metal line 220.
Specifically, in this embodiment, the material of the first diffusion barrier layer is the same as the material of the second diffusion barrier layer, and the materials of the first metal layer and the second metal layer are the same.
As an example, the material of the first anti-diffusion barrier layer and the material of the second anti-diffusion barrier layer are both TiN; the first metal layer and the second metal layer are made of Cu, the resistivity of the Cu is low, RC delay in a back-end process can be reduced, and the Cu has excellent electromigration resistance.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A semiconductor structure, comprising:
the substrate comprises a bottom dielectric layer, the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, the interconnection layers comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer;
a top dielectric layer located on the bottom dielectric layer;
the first metal wire penetrates through the top dielectric layer at the top of the conductive plug and is in contact with the conductive plug, and the first metal wire is used as a signal wire;
and the second metal wire penetrates through the second dielectric layer and the top dielectric layer at the top of the second interconnection layer and is in contact with the second interconnection layer, and the second metal wire is used as a power supply wire.
2. The semiconductor structure of claim 1, wherein a linewidth of the second metal line is greater than a linewidth of the first metal line.
3. The semiconductor structure of claim 1, wherein the interconnect layer material comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN; the material of the conductive plug comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN.
4. The semiconductor structure of claim 1, wherein a material of the first metal line comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN; the material of the second metal wire comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN.
5. The semiconductor structure of claim 1, wherein the material of the bottom dielectric layer comprises SiOCH, siOC, siO 2 One or more of FSG, BSG, PSG and BPSG; the material of the top dielectric layer comprises SiOCH, siOC and SiO 2 One or more of FSG, BSG, PSG and BPSG.
6. The semiconductor structure of claim 1, wherein the substrate further comprises: the device comprises a substrate, a grid structure positioned on the substrate and source-drain doped regions positioned on two sides of the grid structure;
the bottom dielectric layer is positioned above the substrate and covers the source-drain doped region;
the interconnection layer is located in the first dielectric layer on the top of the source-drain doped region and is in contact with the source-drain doped region.
7. The semiconductor structure of claim 6, wherein the material of the substrate comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;
the gate structure comprises the following materials: any one or more of TiAl, tiALC, taAlN, tiAlN, moN, taCN, alN, ta, tiN, taN, taSiN, tiSiN, W, co, al, cu, ag, au, pt and Ni.
8. The semiconductor structure of claim 6, wherein the substrate further comprises a gate dielectric layer between the gate structure and the channel structure; the gate dielectric layer comprises the following materials: hfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 、Al 2 O 3 Silicon oxide and nitrogen-doped silicon oxide.
9. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a bottom dielectric layer, the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, the interconnection layers comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer;
forming a top dielectric layer on the bottom dielectric layer;
forming a first interconnection groove penetrating through the top dielectric layer on the top of the conductive plug, and a second interconnection groove penetrating through a second dielectric layer on the top of the second interconnection layer and the top dielectric layer, wherein the conductive plug is exposed out of the first interconnection groove, and the second interconnection layer is exposed out of the second interconnection groove;
and filling a conductive material in the first interconnection groove and the second interconnection groove, and correspondingly forming a first metal wire and a second metal wire respectively, wherein the first metal wire is in contact with the conductive plug and is used as a signal wire, and the second metal wire is in contact with the second interconnection layer and is used as a power supply wire.
10. The method for forming a semiconductor structure according to claim 9, wherein an opening line width of the second interconnect trench is larger than an opening line width of the first interconnect trench.
11. The method of forming a semiconductor structure of claim 9, wherein the step of forming the first and second interconnect trenches comprises: forming a plurality of trenches penetrating through the top dielectric layer, wherein the trenches comprise a first interconnection groove which is positioned on the top of the conductive plug and exposes the conductive plug, and a first initial trench which is positioned above the second interconnection layer and exposes the second dielectric layer;
and forming a second initial groove penetrating through a second dielectric layer at the bottom of the first initial groove, wherein the second initial groove exposes the second interconnection layer, and the second initial groove and the first initial groove are used for forming the second interconnection groove.
12. The method of forming a semiconductor structure according to claim 11, wherein an opening line width of the first preliminary trench is larger than an opening line width of the first interconnection groove;
the step of forming the second preliminary trench includes: forming sacrificial layers on the bottom and the side wall of the groove, wherein the sacrificial layers on the side wall of the first interconnection groove are in contact with each other, the first interconnection groove is filled with the sacrificial layers, and the sacrificial layers on the side wall of the first initial groove are separated;
etching the sacrificial layer, removing the sacrificial layer on the side wall and the bottom of the first initial groove, and using the residual sacrificial layer filled in the first interconnection groove as a shielding layer;
and etching the second dielectric layer at the bottom of the first initial groove by taking the shielding layer as a mask, and forming a second initial groove below the first initial groove.
13. The method of forming a semiconductor structure of claim 11, wherein the step of forming the second initial trench comprises: forming a patterning layer on the top dielectric layer, wherein the patterning layer fills the first interconnection layer and exposes the first initial groove; and etching the second dielectric layer at the bottom of the first initial groove by taking the patterning layer as a mask.
14. The method of forming a semiconductor structure of claim 12, wherein after forming the second preliminary trench, before filling the first and second interconnect trenches with a conductive material, the method of forming a semiconductor structure further comprises: and removing the shielding layer.
15. The method of forming a semiconductor structure of claim 12, wherein forming the sacrificial layer comprises a chemical vapor deposition process.
16. The method of forming a semiconductor structure of claim 12, wherein the sacrificial layer is etched using an isotropic etch process.
17. The method of claim 12, wherein the process of etching the second dielectric layer at the bottom of the first initial trench comprises an anisotropic etching process.
18. The method of claim 12, wherein a material of the sacrificial layer comprises amorphous carbon or amorphous germanium.
19. The method of forming a semiconductor structure of claim 12, wherein forming a plurality of trenches through the top dielectric layer comprises: forming a hard mask layer on the top dielectric layer, wherein a plurality of mask openings are formed in the hard mask layer;
etching the top dielectric layer along the mask opening by taking the hard mask layer as a mask to form a plurality of grooves penetrating through the top dielectric layer;
in the step of forming the sacrificial layer, the sacrificial layer is further formed on the top and sidewalls of the hard mask layer.
20. The method for forming a semiconductor structure according to any one of claims 9 to 19, wherein the base further comprises a substrate, a gate structure located on the substrate, and source-drain doped regions located on both sides of the gate structure;
the bottom dielectric layer is positioned above the substrate and covers the source-drain doped region; the interconnection layer is positioned in the first dielectric layer on the top of the source-drain doped region and is in contact with the source-drain doped region.
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