CN115491650A - 镀膜方法、芯片基板及芯片 - Google Patents
镀膜方法、芯片基板及芯片 Download PDFInfo
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Abstract
本申请公开了一种镀膜方法、芯片基板及芯片,涉及微纳加工技术领域。所述方法包括:将待镀膜的基板固定在基座上,基板上开设有孔;调整基座,以使得基板所在平面与镀膜材料的沉积方向之间的夹角大于0度且小于90度;控制基板绕法线转动;在基板转动的过程中,控制镀膜材料沿沉积方向进入孔内并沉积在孔的侧壁上。本申请利用一种基于可变倾斜角度镀膜工艺对孔的侧壁进行镀膜,特别是对于具有高深宽比、高垂直性的孔来说,能够提升镀膜材料在孔侧壁上沉积的连续性和厚度,以满足对侧壁薄膜厚度和覆盖率的要求。对于超导量子芯片来说,能够提升超导材料在芯片基板的孔侧壁上沉积的连续性和厚度,从而满足微波传输的要求。
Description
技术领域
本申请实施例涉及微纳加工技术领域,特别涉及一种镀膜方法、芯片基板及芯片。
背景技术
为了使得量子芯片能够容纳更多的量子比特,诸如倒装焊技术、多层堆叠技术等方案被提出,硅通孔(Through Silicon Via,简称TSV)技术是实现芯片堆叠的关键技术。
量子芯片中常用的超导材料(诸如铝、铌、氮化钛等)多采用物理气相沉积(Physical Vapor Deposition,简称PVD)方法在垂直于芯片基板的方向上镀膜,对于高深宽比和高垂直性的硅通孔,存在通孔的侧壁无法沉积上连续的薄膜以及侧壁上的薄膜厚度不足的问题。
发明内容
本申请实施例提供了一种镀膜方法、芯片基板及芯片,能够提升镀膜材料在孔侧壁上沉积的连续性和厚度。所述技术方案如下:
根据本申请实施例的一个方面,提供了一种镀膜方法,所述方法包括:
将待镀膜的基板固定在基座上,所述基板上开设有孔;
调整所述基座,以使得所述基板所在平面与镀膜材料的沉积方向之间的夹角大于0度且小于90度;
控制所述基板绕法线转动;
在所述基板转动的过程中,控制所述镀膜材料沿所述沉积方向进入所述孔内并沉积在所述孔的侧壁上。
根据本申请实施例的一个方面,提供了一种芯片基板,所述芯片基板采用上述镀膜方法进行镀膜。
根据本申请实施例的一个方面,提供了一种芯片,所述芯片的基板采用上述镀膜方法进行镀膜。
本申请实施例提供的技术方案可以带来如下有益效果:
本申请利用一种基于可变倾斜角度镀膜工艺对孔的侧壁进行镀膜,特别是对于具有高深宽比、高垂直性的孔来说,能够提升镀膜材料在孔侧壁上沉积的连续性和厚度,以满足对侧壁薄膜厚度和覆盖率的要求。对于超导量子芯片来说,能够提升超导材料在芯片基板的孔侧壁上沉积的连续性和厚度,从而满足微波传输的要求。
附图说明
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是相关技术提供的镀膜方法的示意图;
图2是本申请一个实施例提供的镀膜方法的流程图;
图3是本申请一个实施例提供的镀膜设备的结构示意图;
图4是本申请一个实施例提供的采用可变倾斜角度对盲孔侧壁进行镀膜的示意图;
图5是本申请一个实施例提供的采用可变倾斜角度对通孔侧壁进行镀膜的示意图;
图6是本申请另一个实施例提供的镀膜方法的流程图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请实施方式作进一步地详细描述。
量子计算机(quantum computer)是一类遵循量子力学规律进行高速数学和逻辑运算、存储及处理量子信息的物理装置。当某个装置处理和计算的是量子信息,运行的是量子算法时,它就是量子计算机。量子计算机的特点主要有运行速度较快、处置信息能力较强、应用范围较广等。与经典计算机比较起来,信息处理量愈多,对于量子计算机实施运算也就愈加有利,也就更能确保运算具备精准性。
量子芯片是量子计算机的核心部件。量子芯片是将量子线路集成在基片上,进而承载量子信息处理的功能。借鉴于传统计算机的发展历程,量子计算机的研究在克服瓶颈技术之后,要想实现商品化和产业升级,需要走集成化的道路。超导系统、半导体量子点系统、微纳光子学系统、甚至是原子和离子系统,都想走芯片化的道路。从发展看,超导量子芯片系统从技术上走在了其它物理系统的前面;传统的半导体量子点系统也是人们努力探索的目标,因为毕竟传统的半导体工业发展已经很成熟,如半导体量子芯片在退相干时间和操控精度上一旦突破容错量子计算的阈值,有望集成传统半导体工业的现有成果,节省开发成本。
目前采用PVD方法的镀膜工艺,镀膜材料是以垂直于芯片基板所在平面的方向(也即沿着芯片基板的法线方向)打在芯片基板上的,如图1所示,镀膜材料的沉积方向(图1中箭头所指方向)与芯片基板11所在平面(图1中虚线所示)垂直。对于具有台阶形状的基板11,尤其是具有深孔结构的基板11,大部分的镀膜材料12沉积在了基板11的表面以及孔的底部,仅有极少量的镀膜材料12基于在孔内的散射沉积在了孔的侧壁上,如图1中斜线填充区域所示。在半导体产业中,经常采用这种方法来制备电镀的种子层,之后再进行电镀铜工艺对硅孔进行填充。对于电镀的种子层,需要很小的厚度即可满足后续电镀铜工艺的要求。然而对于超导量子芯片,由于要求沉积形成的薄膜材料为超导态,因此电镀铜的工艺无法使用。如果只使用镀膜技术而不采用后续的电镀工艺进行硅深孔的填充时,就需要侧壁上的薄膜足够厚才能有效传播微波信号,因此垂直入射的方式无法满足要求。
本申请提供了一种镀膜方法、芯片基板及芯片,其基本构思是利用一种基于可变倾斜角度镀膜工艺对孔的侧壁进行镀膜,能够提升镀膜材料在孔侧壁上沉积的连续性和厚度,以满足对侧壁薄膜厚度和覆盖率的要求。对于超导量子芯片来说,能够提升超导材料在芯片基板的孔侧壁上沉积的连续性和厚度,从而满足微波传输的要求。当然,本申请提供的镀膜方法并不仅限于对超导量子芯片的基板进行镀膜,还可对其他一些芯片(如普通的IC(Integrated Circuit,集成电路)芯片)进行镀膜,本申请对此不作限定。
下面,将通过几个实施例对本申请技术方案进行介绍说明。
请参考图2,其示出了本申请一个实施例提供的镀膜方法的流程图,该方法可以包括如下几个步骤(210~240):
步骤210,将待镀膜的基板固定在基座上,基板上开设有孔。
在本申请实施例中,对基板的材质、尺寸、形状等不作限定,这可以结合基板的用途来选择。以超导量子芯片的基板为例,其可以由硅材料制成,因此也可以称为硅片或者硅基板。
基板上开设有孔。可选地,在基板上采用Bosch工艺加工出孔结构,如采用刻蚀-沉积-刻蚀循环进行的工艺得到具有高深宽比、高垂直性的孔。可选地,基板上的孔具有高深宽比、高垂直性的特性。所谓高深宽比,是指孔的深度与宽度的比值较大,如大于某一阈值。在一个示例中,孔的深度为200μm(微米)、孔的宽度为20μm,则深宽比为10。所谓高垂直性,是指孔的侧壁与基板所在平面垂直或基本接近垂直,例如孔的侧壁与基板表面的夹角为90±1度。
可选地,基板上开设的孔可以是通孔,也可以是盲孔。通孔是指将基板刻蚀穿,与基板上下表面相连的结构。盲孔是指将基板部分刻蚀,但不穿透基板,只与基板其中一个表面相连的结构。
另外,在本申请实施例中,对孔的形状不作限定。例如,孔为圆形孔,或多边形孔,或倒角多边形孔,或不规则图形孔。其中,圆形孔是指孔的截面为圆形,多边形孔是指孔的截面为多边形(如三角形、矩形、五边形、六边形等),倒角多边形孔是指孔的截面为倒角多边形,即多边形的角为倒角,如倒角矩形也可称为圆角矩形,不规则图形孔是指孔的截面为不规则图形。
对于不同形状的孔,其深宽比的计算方式会有所不同。例如,在孔为圆形孔的情况下,孔的深宽比为孔的深度与孔的直径的比值。又例如,在孔为多边形孔或倒角多边形孔或不规则图形孔的情况下,孔的深宽比为孔的深度与孔的截面的最大对角线长度的比值。其中,最大对角线长度是指经过孔的截面的中心点的所有对角线线段的长度中的最大值。
步骤220,调整基座,以使得基板所在平面与镀膜材料的沉积方向之间的夹角大于0度且小于90度。
在镀膜之前(即沉积镀膜材料之前),通过对基座进行调整,以改变基板的朝向。上述调整的目标是使得基板所在平面与镀膜材料的沉积方向之间的夹角大于0度且小于90度。在一个示例中,镀膜材料的沉积方向预先规定好,且上述夹角也预先计算确定,那么通过调整基座以改变基板的倾斜角度,就能够达成上述目标,使得基板所在平面与镀膜材料的沉积方向之间的夹角为上述预先计算确定出的角度,该角度是一个大于0度且小于90度的数值。
在对基座进行调整完成之后,可以执行下述步骤230。
步骤230,控制基板绕法线转动。
图3示例性示出了用于实现本申请镀膜方法的镀膜设备的结构示意图。该镀膜设备可以包括:用于产生电子束或离子束的发射器31、靶材或者盛放有靶材的坩埚32、放置待镀膜的基板的基座34、控制基座34倾斜和转动的系统36,以及给基座34施加偏压的系统37。将待镀膜的基板放置在基座34上之后,可以通过系统36控制基座34倾斜和转动。发射器31发射出电子束或离子束,经过加速后轰击靶材32,箭头33表示电子束或离子束的入射方向。从靶材32中溅射或蒸发出的镀膜材料以一定的速率和方向沉积到放置有基板的基座34,箭头35代表镀膜材料的沉积方向。在镀膜材料沉积的过程中,由系统36控制基座34倾斜角度θ+δθ,并且控制基座34以角速度ω旋转,从而带动基板绕着自身法线以角速度ω旋转。另外,在镀膜材料沉积的过程中,由系统37给基座34施加负偏压增加镀膜材料的沉积概率。
需要说明的是,由于在步骤220调整基座的过程中,需要知道镀膜材料的沉积方向,该沉积方向可以预先通过实验进行测算得到。例如,固定好图3所示发射器31和靶材32的位置,发射器31发射出电子束或离子束,经过加速后轰击靶材32,从靶材32中溅射或蒸发出的镀膜材料以一定的速率和方向运动,通过对镀膜材料的运动方向进行测算,即可得到沉积方向。
当然,在一些其他示例中,除了通过调整基座来改变基板的切斜角度,以实现对基板所在平面与镀膜材料的沉积方向之间的夹角进行调整之外,还可以调整镀膜材料的沉积方向来实现对上述夹角的调整。例如,可以调整发射器31的位置、靶材32的位置、发射器31发射出电子束或离子束的朝向等中的至少之一,来实现对镀膜材料的沉积方向进行调整。
步骤240,在基板转动的过程中,控制镀膜材料沿沉积方向进入孔内并沉积在孔的侧壁上。
在镀膜材料沉积的过程中,镀膜材料沿沉积方向运动,一部分镀膜材料会沉积在基板的表面,还有一部分镀膜材料会进入基板的孔内并沉积在孔的侧壁上。
在本申请实施例中,沉积方向与基板所在平面之间的夹角大于0度且小于90度。例如,通过图3中的系统36控制基座34倾斜一定角度,以使得镀膜材料的沉积方向与基板所在平面之间的夹角大于0度且小于90度,也即使得镀膜材料倾斜地射入孔内,而非垂直射入孔内,这有助于提升镀膜材料在孔的侧壁上沉积的连续性和厚度,以满足对侧壁薄膜厚度和覆盖率的要求。
在示例性实施例中,上述夹角为θ+δθ,其中θ基于孔的深宽比确定,δθ为可调整角度。也即,θ可以通过相关计算公式基于孔的深宽比计算得到,δθ可以基于实际的沉积效果进行调整。
在一个示例中,不论孔为通孔还是盲孔,θ=arctan(D/L),其中D为孔的深度,L为孔的宽度,孔的深宽比为D/L。
在另一个示例中,在孔为盲孔的情况下,θ=arctan(D/L),其中D为孔的深度,L为孔的宽度。图4是采用可变倾斜角度对盲孔侧壁进行镀膜的示意图。其中41是带有盲孔的基板,42是在基板41表面以及孔的侧壁上沉积的薄膜(图4中斜线填充区域所示),箭头所指方向是薄膜沉积方向(也即镀膜材料的沉积方向)。θ是根据孔的深宽比确定的薄膜沉积方向和基板表面之间的夹角,即tanθ=D/L,其中D为孔的深度,L为孔的宽度。δθ为根据实际镀膜情况对薄膜沉积方向和基板表面之间的夹角的调整量。当镀膜材料进入孔内部时,对基座上施加的偏压会导致镀膜材料偏离原来的入射方向。此外当镀膜材料带有电荷时,在孔内的镜像力也会使镀膜材料发生一定的偏转。另一方面,镀膜材料与孔侧壁接触时,只有部分材料被孔侧壁捕获形成薄膜,另一部分材料在孔侧壁上发生反射,最终沉积到别处形成薄膜。被孔侧壁捕获的镀膜材料由于仍然具有一定的能量,会在孔侧壁上产生滑移,最后能量降低到一定程度后停留孔侧壁上形成薄膜。基于以上原因,在实际操作中,需要对薄膜沉积方向和基板表面之间的夹角进行一定的调整。通过填充完成后进行裂片观察侧壁上的实际薄膜填充情况来对δθ进行调节,确定最佳的薄膜沉积方向和基板表面之间的夹角θ+δθ。需要说明的是,可以在工艺的试验阶段,对基板进行裂片观察侧壁上的实际薄膜填充情况,以确定出合适的δθ的值(或者说确定出合适的θ+δθ的值),待该值确定之后,就可以按照该值控制薄膜沉积方向与基板所在平面之间的夹角,然后对基板进行镀膜即可生产出镀有符合要求的薄膜,不必再进行裂片观察。
在另一个示例中,在孔为通孔的情况下,θ=arctan(D/2L),其中D为孔的深度,L为孔的宽度。对于这种情况,基板的一面镀膜完成之后,翻转该基板,以对基板的另一面进行镀膜。图5是采用可变倾斜角度对通孔侧壁进行镀膜的示意图,其中51是带有通孔的基板,52是在基板51表面以及孔的侧壁上沉积的薄膜(图5中斜线填充区域所示),箭头所指方向是薄膜沉积方向(也即镀膜材料的沉积方向)。由于通孔可以从基板51的上下表面进行镀膜,因此为了取得更好的薄膜填充效果,可以采用如下步骤:首先从基板51的其中一面进行薄膜沉积,确定薄膜沉积方向和基板51表面之间的夹角θ+δθ,其中tanθ=D/2L。δθ根据实际的镀膜效果进行调整。之后将基板51进行翻转,可以将基板51从镀膜仪器中取出进行手动翻转,也可以设计专用的基座自动将基板51进行翻转。然后从基板51的另一面进行薄膜沉积,同样设定薄膜沉积方向和基板51表面之间的夹角为θ+δθ,最终完成对通孔的薄膜填充。
另外,可以通过调整基板的倾斜角度,以改变基板所在平面与沉积方向之间的夹角;和/或,调整沉积方向的朝向,以改变基板所在平面与沉积方向之间的夹角。例如,控制薄膜沉积方向和基板之间的夹角时,保持薄膜沉积方向不变,调节基底的放置角度以使得基板的倾斜角度发生改变;或者,保持基底的放置角度不变(也即基板的倾斜角度保持不变),调节薄膜沉积方向,使薄膜沉积方向和基板之间的夹角在0~90度范围内调节。
在示例性实施例中,在基板上开设有多个孔且同时对该多个孔进行镀膜的情况下,θ基于多个孔中的目标孔的深宽比确定,该目标孔是深宽比最大的孔。这样可以在同时对该多个孔进行镀膜时,保证每个孔的侧壁上都可以沉积上连续且厚度合适的薄膜,兼顾镀膜效率和镀膜效果。
在示例性实施例中,镀膜材料的沉积方法为物理气相沉积方法,如电子束蒸发或者磁控溅射。
在示例性实施例中,在沉积镀膜材料的过程中,对基座施加负偏压,从而吸引等离子体,使得更多的金属等离子体进入到孔内,这有助于增加镀膜材料的沉积概率。
在示例性实施例中,基板为超导量子芯片的基板(如硅片),且镀膜材料为超导材料(如铝、铌、氮化钛等材料)。
另外,本申请提供了如下两种方式以在基板表面形成诸如电容、谐振腔等元器件结构。
在一种可能的实现方式中,先镀膜后涂敷光刻胶。例如,在基板的表面涂敷光刻胶,形成第一光刻胶层;对第一光刻胶层进行曝光,形成曝光后的第一光刻胶层;其中,基板上由镀膜材料沉积形成的薄膜,被曝光后的第一光刻胶层覆盖的区域为元器件结构区域;对薄膜上未被所述曝光后的第一光刻胶层覆盖的区域进行刻蚀,保留薄膜上被曝光后的第一光刻胶层覆盖的区域,形成元器件结构;去除曝光后的光刻胶层。
在另一种可能的实现方式中,先涂敷光刻胶后镀膜。在镀膜之前,在基板的表面涂敷光刻胶,形成第二光刻胶层;对第二光刻胶层进行曝光,形成曝光后的第二光刻胶层;其中,基板的表面未被曝光后的第二光刻胶层覆盖的区域,为元器件结构区域;对带有曝光后的第二光刻胶层的基板进行镀膜,在元器件结构区域形成元器件结构;去除曝光后的第二光刻胶层以及附着在曝光后的第二光刻胶层上的镀膜材料。这种加工产生元器件结构的方式即为lift-off方法(即金属剥离工艺)。
本申请提供的技术方案,利用一种基于可变倾斜角度镀膜工艺对孔的侧壁进行镀膜,特别是对于具有高深宽比、高垂直性的孔来说,能够提升镀膜材料在孔侧壁上沉积的连续性和厚度,以满足对侧壁薄膜厚度和覆盖率的要求。对于超导量子芯片来说,能够提升超导材料在芯片基板的孔侧壁上沉积的连续性和厚度,从而满足微波传输的要求。
另外,本申请提供的镀膜方法不仅可以用于超导量子芯片中超导材料的沉积,还可以用于半导体产业中深孔内种子层的沉积,具有更高的工艺兼容性。
另外,本申请采用电子束蒸发或磁控溅射等物理气相沉积方法对孔内进行薄膜填充,可以使用的薄膜种类明显增加。而且,与采用化学气相沉积(Chemical VaporDeposition,简称CVD)方法相比(CVD方法需要高温环境,无法与lift-off工艺相结合),本申请采用物理气相沉积方法则不需要高温条件,可以和lift-off工艺相结合,简化加工流程。
请参考图6,其示出了本申请另一个实施例提供的镀膜方法的流程图。在本实施例中,主要以基板为超导量子芯片的基板(如硅片),镀膜材料为超导材料为例进行介绍说明。该方法可以包括如下几个步骤(610~640):
步骤610,将待镀膜的超导量子芯片的基板固定在基座上,该基板上开设有孔。
步骤620,调整基座,以使得基板所在平面与超导材料的沉积方向之间的夹角大于0度且小于90度。
步骤630,控制基板绕法线转动。
步骤640,在基板转动的过程中,控制超导材料沿沉积方向进入孔内并沉积在孔的侧壁上。
可选地,超导量子芯片的基板为硅片,该硅片上开设有一个或者多个孔。可选地,在硅片上采用Bosch工艺加工出孔结构,如采用刻蚀-沉积-刻蚀循环进行的工艺得到具有高深宽比、高垂直性的孔。可选地,硅片上开设的孔可以是通孔,也可以是盲孔。另外,在本申请实施例中,对孔的形状不作限定。例如,孔为圆形孔,或多边形孔,或倒角多边形孔,或不规则图形孔。
在一些实施例中,使用深硅刻蚀技术(比如Bosch工艺)加工出带有硅深孔的硅片,将硅片清洗并吹干后放置在镀膜设备内,对镀膜设备进行抽真空操作,之后等待设备将硅片传送到镀膜位置处时,设定薄膜沉积方向和硅片表面的夹角θ+δθ,其中θ可根据硅孔的深宽比确定,δθ可以根据实际观察到的镀膜效果进行调整。接下来设定基底的旋转角速度ω,例如ω为1~50rpm(rotation per minute,每分钟转数),可选为ω=20rpm。然后对薄膜沉积速率进行设定,通常是通过改变电子束或离子束轰击靶材的功率来调节薄膜沉积速率。在一个示例中,薄膜沉积速率为确定完薄膜沉积速率后就可以根据所要求的薄膜厚度设定薄膜沉积时间。对于硅盲孔结构,在这一步薄膜沉积完毕后,将硅片进行裂片,用电子显微镜观察硅盲孔侧壁上薄膜的沉积情况。而对于硅通孔结构,可以先填充其中的一部分,然后将硅片翻转,采用相同的镀膜参数(包括夹角、薄膜沉积速率、薄膜沉积时间等参数)从硅片的另一面继续进行薄膜沉积。之后将硅片进行裂片,使用电子显微镜观察硅通孔侧壁上薄膜的沉积情况。需要说明的是,可以在工艺的试验阶段,对硅片进行裂片观察侧壁上的实际薄膜填充情况,以确定出合适的夹角度数,待该值确定之后,就可以按照该值控制沉积方向与硅片表面之间的夹角,然后对硅片进行镀膜即可生产出镀有符合要求的薄膜,不必再进行裂片观察。可选地,孔侧壁上的薄膜厚度为100nm左右。在对通孔进行薄膜沉积的时候,硅片的上下表面也会沉积上薄膜,并且得到的硅片上下表面的薄膜和硅通孔内的薄膜直接相连。之后可以采用旋涂光刻胶,并使用光刻的方法在硅片的表面定义需要加工的元器件结构,比如超导量子芯片中的谐振腔、电容等结构,定义出图形结构后采用湿法刻蚀或干法刻蚀的方法在硅片表面刻蚀元器件结构。并且由于本申请中采用的是物理气相沉积的方法,例如电子束蒸发或磁控溅射,不需要高温的镀膜条件,可以采用lift-off工艺加工硅表面的元器件结构,具体为镀膜前在硅片表面旋涂光刻胶,然后进行光刻定义出元器件结构,镀膜完毕后使用丙酮或专用的去胶液去除光刻胶,得到元器件结构,进而将硅片表面结构和通孔内的薄膜直接相连。
本申请一示例性实施例还提供了一种芯片基板,该芯片基板采用上文介绍的镀膜方法进行镀膜。
本申请一示例性实施例还提供了一种芯片,该芯片的基板采用上文介绍的镀膜方法进行镀膜。可选地,该芯片为量子芯片。量子芯片是集成有量子线路(或称为量子电路)的芯片。当然,在一些其他实施例中,该芯片也可以是普通的IC芯片,本申请实施例对此不作限定。
应当理解的是,在本文中提及的“多个”是指两个或两个以上。另外,本文中描述的步骤编号,仅示例性示出了步骤间的一种可能的执行先后顺序,在一些其它实施例中,上述步骤也可以不按照编号顺序来执行,如两个不同编号的步骤同时执行,或者两个不同编号的步骤按照与图示相反的顺序执行,本申请实施例对此不作限定。
以上所述仅为本申请的示例性实施例,并不用以限制本申请,凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。
Claims (15)
1.一种镀膜方法,其特征在于,所述方法包括:
将待镀膜的基板固定在基座上,所述基板上开设有孔;
调整所述基座,以使得所述基板所在平面与镀膜材料的沉积方向之间的夹角大于0度且小于90度;
控制所述基板绕法线转动;
在所述基板转动的过程中,控制所述镀膜材料沿所述沉积方向进入所述孔内并沉积在所述孔的侧壁上。
2.根据权利要求1所述的方法,其特征在于,所述孔为通孔或盲孔。
3.根据权利要求1所述的方法,其特征在于,所述孔为圆形孔,或多边形孔,或倒角多边形孔,或不规则图形孔。
4.根据权利要求3所述的方法,其特征在于,
在所述孔为所述圆形孔的情况下,所述孔的深宽比为所述孔的深度与所述孔的直径的比值;或者,
在所述孔为所述多边形孔或所述倒角多边形孔或所述不规则图形孔的情况下,所述孔的深宽比为所述孔的深度与所述孔的截面的最大对角线长度的比值。
5.根据权利要求1所述的方法,其特征在于,所述夹角为θ+δθ,其中θ基于所述孔的深宽比确定,δθ为可调整角度。
6.根据权利要求5所述的方法,其特征在于,θ=arctan(D/L),其中D为所述孔的深度,L为所述孔的宽度。
7.根据权利要求5所述的方法,其特征在于,在所述孔为通孔的情况下,θ=arctan(D/2L),其中D为所述孔的深度,L为所述孔的宽度。
8.根据权利要求7所述的方法,其特征在于,所述基板的一面镀膜完成之后,翻转所述基板,以对所述基板的另一面进行镀膜。
9.根据权利要求1所述的方法,其特征在于,在所述基板上开设有多个所述孔的情况下,所述夹角基于多个所述孔中的目标孔的深宽比确定,所述目标孔是深宽比最大的孔。
10.根据权利要求1所述的方法,其特征在于,所述镀膜材料的沉积方法为物理气相沉积方法。
11.根据权利要求1所述的方法,其特征在于,所述控制所述镀膜材料沿所述沉积方向进入所述孔内并沉积在所述孔的侧壁上之后,还包括:
在所述基板的表面涂敷光刻胶,形成第一光刻胶层;
对所述第一光刻胶层进行曝光,形成曝光后的第一光刻胶层;其中,所述基板上由所述镀膜材料沉积形成的薄膜,被所述曝光后的第一光刻胶层覆盖的区域为元器件结构区域;
对所述薄膜上未被所述曝光后的第一光刻胶层覆盖的区域进行刻蚀,保留所述薄膜上被所述曝光后的第一光刻胶层覆盖的区域,形成元器件结构;
去除所述曝光后的光刻胶层。
12.根据权利要求1所述的方法,其特征在于,所述方法还包括:
在镀膜之前,在所述基板的表面涂敷光刻胶,形成第二光刻胶层;
对所述第二光刻胶层进行曝光,形成曝光后的第二光刻胶层;其中,所述基板的表面未被所述曝光后的第二光刻胶层覆盖的区域,为元器件结构区域;
对带有所述曝光后的第二光刻胶层的基板进行镀膜,在所述元器件结构区域形成元器件结构;
去除所述曝光后的第二光刻胶层以及附着在所述曝光后的第二光刻胶层上的镀膜材料。
13.根据权利要求1所述的方法,其特征在于,所述基板为超导量子芯片的基板,且所述镀膜材料为超导材料。
14.一种芯片基板,其特征在于,所述芯片基板采用如权利要求1至13任一项所述的镀膜方法进行镀膜。
15.一种芯片,其特征在于,所述芯片的基板采用如权利要求1至13任一项所述的镀膜方法进行镀膜。
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