CN115472656B - Display panel and preparation method thereof - Google Patents
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- CN115472656B CN115472656B CN202211082686.4A CN202211082686A CN115472656B CN 115472656 B CN115472656 B CN 115472656B CN 202211082686 A CN202211082686 A CN 202211082686A CN 115472656 B CN115472656 B CN 115472656B
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- 238000000034 method Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 230000003068 static effect Effects 0.000 abstract description 37
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
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- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
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Abstract
The application provides a display panel and a preparation method thereof, wherein the display panel comprises a substrate; a shielding metal layer disposed on the substrate; the array driving layer is arranged on the shielding metal layer and comprises a plurality of driving thin film transistors; the shielding metal layer comprises a shielding part and an antistatic part, wherein the shielding part corresponds to the driving thin film transistors, the antistatic part is arranged on the periphery of the shielding part, the antistatic part comprises a first antistatic wiring and at least one first bridging section, the first antistatic wiring is arranged around the shielding part, the first antistatic wiring is electrically connected with the shielding part through the first bridging section, the first antistatic wiring is an annular wiring with an intermittent opening, and static charges existing inside the shielding part can be effectively led out of the display panel through the antistatic part with a specific structure arranged on the periphery of the shielding part, so that the problem that the yield and reliability of the display panel are affected due to static charge is concentrated in the shielding part.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
Unlike the conventional Liquid crystal display panel (Liquid CRYSTAL DISPLAY, LCD), the Organic LIGHT EMITTING Diode (OLED) display panel realizes display by self-luminescence of the Organic light emitting device, and has a series of advantages of an all-solid structure, high brightness, full viewing angle, high corresponding speed, wide working stability range, and capability of realizing flexible display, and the like, and has become the next generation display technology with great competitive and development prospects at present. The OLED display panel generally adopts a flexible polyimide material as a flexible substrate, so that the OLED display panel can be made lighter and thinner, but molecules in the flexible substrate material are polarized under the action of an electric field in the production and manufacturing process and when the thin film transistor works, so that charges are accumulated at a layer interface, the charges react to an active layer of the thin film transistor, the thin film transistor is affected by back channel effect, the problems of brightness reduction and image sticking are caused, and the reliability of the thin film transistor is obviously attenuated.
At present, for the problem of reliability attenuation of a thin film transistor, it is common practice in the industry to arrange a shielding metal layer under a driving thin film transistor, but in the preparation process of the thin film transistor, particularly in the excimer laser annealing process, the shielding metal layer is easy to be damaged by static electricity to cause abnormal film patterns, so that the reliability and yield of a display panel are reduced.
Disclosure of Invention
The invention provides a display panel and a preparation method thereof, which can solve the problem that the yield and the reliability of the display panel are affected due to the occurrence of electrostatic explosion of a metal shielding layer.
To solve the above problems, in a first aspect, the present invention provides a display panel including:
A substrate;
a shielding metal layer disposed on the substrate;
the array driving layer is arranged on the shielding metal layer and comprises a plurality of driving thin film transistors;
The shielding metal layer comprises a shielding part and an antistatic part, wherein the shielding part corresponds to the driving thin film transistors, the antistatic part is arranged on the periphery of the shielding part, the antistatic part comprises a first antistatic wiring and at least one first bridging section, the first antistatic wiring is arranged around the shielding part, the first antistatic wiring is electrically connected with the shielding part through the first bridging section, and the first antistatic wiring is an annular wiring with an intermittent opening.
In an embodiment of the present invention, the antistatic portion further includes two extending wires, and the two extending wires are connected to two ends of the first antistatic wire at the intermittent opening and extend in a direction away from the shielding portion.
In an embodiment of the present invention, the first anti-static wire includes a first anti-static wire sub-section located in a first direction of the shielding portion, two intermittent openings are disposed on the first anti-static wire sub-section, and the two intermittent openings are located at two ends of the first anti-static wire sub-section respectively.
In an embodiment of the invention, the anti-static portion includes a second anti-static wire and at least one second bridge section, the second anti-static wire is a closed ring wire disposed around the shielding portion and located inside the first anti-static wire, the second anti-static wire is electrically connected to the shielding portion through the second bridge section, and the first anti-static wire is electrically connected to the second anti-static wire through the first bridge section.
In the display panel provided by the embodiment of the invention, the width of the first anti-static wiring is larger than that of the second anti-static wiring.
In the display panel provided by the embodiment of the invention, the shielding part comprises a shielding sub-part corresponding to the driving thin film transistors and a first connecting wiring connected with the adjacent shielding sub-part, the first antistatic wiring comprises a plurality of antistatic sub-parts arranged at intervals along the extending direction of the first antistatic wiring and a second connecting wiring connected with the adjacent antistatic sub-parts, wherein the front projection of the shielding sub-part on the substrate is identical to the front projection of the antistatic sub-part on the substrate, and the widths of the first connecting wiring and the second connecting wiring are identical.
In the display panel provided by the embodiment of the invention, the shape of the orthographic projection of the shielding sub-portion on the substrate and the orthographic projection of the anti-static sub-portion on the substrate is a rounded rectangle.
In an embodiment of the invention, the display panel includes a display area and a frame area disposed at a peripheral side of the display area, and the first antistatic trace is disposed in the frame area.
In an embodiment of the present invention, the array driving layer includes a gate driving circuit disposed in the frame region, the gate driving circuit includes a plurality of circuit thin film transistors, one of the circuit thin film transistors includes a channel portion, an orthographic projection of the antistatic portion on the substrate coincides with an orthographic projection of the gate driving circuit on the substrate, and an orthographic projection of the antistatic portion on the substrate does not coincide with orthographic projections of the plurality of channel portions on the substrate.
In a second aspect, the present invention provides a method for manufacturing a display panel, the method comprising the steps of:
s10: providing a substrate, forming a shielding metal layer on the substrate, wherein the shielding metal layer comprises a shielding part and an antistatic part formed on the periphery of the shielding part, the antistatic part comprises a first antistatic wiring surrounding the shielding part and at least one first bridging section, the first antistatic wiring is electrically connected with the shielding part through the first bridging section, and the first antistatic wiring is an annular wiring with an intermittent opening;
s20: and forming an array driving layer on the shielding metal layer, wherein the array driving layer comprises a plurality of driving thin film transistors correspondingly arranged on the shielding part.
The beneficial effects are that: the embodiment of the invention provides a display panel and a preparation method thereof, wherein the display panel comprises a substrate; a shielding metal layer disposed on the substrate; the array driving layer is arranged on the shielding metal layer and comprises a plurality of driving thin film transistors; the shielding metal layer comprises a shielding part corresponding to the driving thin film transistors and an anti-static part arranged on the periphery of the shielding part, the anti-static part comprises a first anti-static wiring and at least one first bridging section, the first anti-static wiring is arranged around the shielding part, the first anti-static wiring is electrically connected with the shielding part through the first bridging section, so that static charges existing in the shielding part can be transmitted to the first anti-static wiring through the first bridging section, further, an intermittent opening is arranged in the first anti-static wiring, when the static charges are transmitted to the end part positioned at the intermittent opening along the first anti-static wiring, the static charges can be transferred onto the substrate from the first anti-static wiring due to the fact that the static charges cannot be continuously transmitted along the first anti-static wiring, and meanwhile, in the preparation or use process of the display panel, other connected structures are necessarily existing on the back of the substrate, such as a supporting part structure exists on the back of the substrate, then static charges can be transmitted along the back of the substrate, namely, the static charges can be effectively prevented from being transmitted to the periphery of the shielding part through the first anti-static wiring, and the static charges can be effectively prevented from being transmitted to the inner side of the display panel, and the static charge can be effectively prevented from being damaged by the shielding part.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a cross-sectional structure of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic plan view of a shielding metal layer in a first display panel according to an embodiment of the present invention;
Fig. 3 is a schematic plan view of a shielding metal layer in a second display panel according to an embodiment of the present invention;
fig. 4 is a schematic plan view of a shielding metal layer in a third display panel according to an embodiment of the present invention;
fig. 5 is a schematic plan view of a shielding metal layer in a third display panel according to an embodiment of the present invention;
Fig. 6 is a schematic plan view of a shielding metal layer in a third display panel according to an embodiment of the present invention;
fig. 7 is a schematic plan view of a first antistatic trace in a display panel according to an embodiment of the present invention;
Fig. 8 is a schematic plan view of another first antistatic trace in the display panel according to the embodiment of the present invention;
fig. 9 is a schematic plan view of a display panel according to an embodiment of the present invention;
FIG. 10 is a schematic view of a cross-sectional structure at the mm' position of FIG. 9;
FIG. 11 is a schematic view of another cross-sectional structure at the mm' position in FIG. 9;
Fig. 12 is a schematic text flow diagram of a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 13a to 13c are schematic structural flow diagrams of a method for manufacturing a display panel according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Referring to fig. 1, the display panel includes a substrate 100, a shielding metal layer 200 and an array driving layer 300 disposed on the substrate 100;
the substrate 100 is generally a flexible substrate formed of a polyimide material, and specifically includes a first flexible substrate 110, a second flexible substrate 130, and a barrier layer 120 disposed between the first flexible substrate 110 and the second flexible substrate 130;
The array driving layer 300 is generally formed by sequentially stacking a buffer layer 310, an active layer 320, a first insulating layer 330, a first metal layer 340, a second insulating layer 350, a second metal layer 360, a third insulating layer 370, and a third metal layer 380, wherein each of the stacked film layers includes a plurality of driving thin film transistors TFT1 for driving display correspondingly disposed in each pixel region;
Further, referring to fig. 2, the shielding metal layer 200 includes a shielding portion 210 corresponding to the driving thin film transistors and an antistatic portion 220 disposed on a peripheral side of the shielding portion 210;
The shielding portion 210 includes a shielding sub-portion 211 corresponding to a plurality of driving thin film transistors and a first connection trace 212 connecting adjacent shielding sub-portions 211, that is, the shielding portion 210 has a grid structure, and the orthographic projection of one shielding sub-portion 211 on the substrate 100 is at least partially overlapped with the orthographic projection of the corresponding active segment of the driving thin film transistor on the substrate 100, so as to protect the driving thin film transistor to improve the reliability of the driving thin film transistor;
The antistatic part 220 includes a first antistatic trace 221 disposed around the shielding part 210 and at least one first bridge section 222, the first antistatic trace 221 is electrically connected to the shielding part 210 through the first bridge section 222, and the number of the first bridge sections 222 may be as large as possible, so as to improve the conductivity between the shielding part 210 and the first antistatic trace 221, which is favorable for transmitting the static charges in the shielding part 210 to the first antistatic trace 221, and illustratively, each shielding sub-part 211 adjacent to the first antistatic trace 221 in the shielding part 210 is connected to the first antistatic trace 221 through one first bridge section 222, and eight first bridge section 222 structures are exemplarily drawn, which are set according to specific process requirements in practical application, and further, the first antistatic trace 221 is an annular trace including an intermittent opening 221a for transmitting the static charges on the display panel of the antistatic part 220 to the substrate through a grounding device.
In the display panel provided by the embodiment of the invention, the shielding part 210 is a conventional structure for improving the reliability of the thin film transistor device in the current display panel, by further adding the antistatic part 220 arranged on the same layer on the peripheral side of the shielding part 210, the risk of static electricity explosion of the shielding part 210 can be greatly reduced, in particular, the antistatic part 220 comprises a first antistatic wiring 221 arranged around the shielding part 210, the first antistatic wiring 221 is electrically connected with the shielding part 210 through at least one first bridging section 222, so that static charges existing in the shielding part 210 can be transmitted to the first antistatic wiring 221 through the first bridging section 222, further, when static charges are transmitted to the end part of the intermittent opening 221a along the first antistatic wiring 221, static charges cannot be continuously transmitted along the first antistatic wiring 221, and thus the static charges can be transferred from the first antistatic wiring 221 to the substrate 100, and the back surface of the display panel is necessarily prepared, and the back surface of the display panel is inevitably connected with the back surface of the display panel due to the fact that the static charges exist in the back surface structure is prepared;
therefore, in the display panel provided by the embodiment of the invention, by providing the antistatic part 220 with a specific structure on the peripheral side of the shielding part 210, the static charges existing in the shielding part 210 can be effectively conducted to the outside of the display panel, so that the problems that the yield and the reliability of the display panel are affected due to the electrostatic explosion caused by the concentration of the static charges in the shielding part 210 are effectively avoided.
Particularly, when the material of the active layer 320 in the array driving layer 300 is low temperature polysilicon, in the fabrication process of the active layer 320, there may be an excimer laser annealing process, that is, a process of irradiating an amorphous silicon film on a substrate to be processed with an excimer laser beam for a short time to recrystallize the amorphous silicon film into a polysilicon film, and the excimer laser beam may be scanned and irradiated from one section of the substrate to the opposite end along a predetermined direction, and the part irradiated with the excimer laser beam may absorb a large amount of heat, and the heat may be conducted to the part not irradiated with the excimer laser beam, and the heat conduction direction is the scanning direction of the excimer laser beam, and at the same time, static charges existing in the shielding metal layer 200 may be conducted along the heat conduction direction, that is, the scanning direction of the excimer laser beam;
therefore, in order to match the conduction direction of the electrostatic charge in the shielding metal layer 200 in the excimer laser annealing process, the arrangement direction of the intermittent opening 221a is set in combination with the scanning direction of the excimer laser beam in the excimer laser annealing process, specifically, please continue to refer to fig. 2, in the excimer laser annealing process, the excimer laser beam scans along the first direction X, the first antistatic trace 221 includes a first antistatic trace subsection 2211 located outside the shielding portion 210 along the first direction X, then the intermittent opening 221a is disposed on the first antistatic trace subsection 2211, so that in the excimer laser annealing process, the electrostatic charge in the first antistatic trace 221 is conducted to the end portion of the first antistatic trace subsection 221a along the first direction X, and is transferred onto the substrate 100, and finally is conducted along the structure connected to the back of the substrate, and by this design, the electrostatic charge in the first antistatic trace 221 is further conducted along the first direction X, thereby avoiding the problem that the electrostatic charge in the shielding portion 210 is further damaged and the electrostatic charge is concentrated in the shielding portion, and the electrostatic charge may be prevented from being further generated.
The intermittent opening 221a may be disposed at any position of the first anti-static electricity wire segment 2211, specifically, as shown in fig. 2, the intermittent opening 221a is disposed in the middle of the first anti-static electricity wire segment 2211, or as shown in fig. 3, the intermittent opening 221a is disposed at an end of the first anti-static electricity wire segment 2211.
It is added that the width of the intermittent opening 221a should not be too narrow, otherwise there is a risk of a tip discharge occurring at the intermittent opening 221 a.
In some embodiments, because the static charge in the first antistatic trace 221 is conducted along the first antistatic trace 221 and is transferred from the first antistatic trace 221 to the substrate at the intermittent opening 221a, the static charge at the intermittent opening 221a is concentrated relatively more than in other areas, so that the risk of electrostatic explosion at the intermittent opening 221a is relatively higher, and referring to fig.4, the antistatic portion 220 further includes two extending traces 223, two extending traces 223 are respectively connected with the first antistatic trace 221 at two ends of the intermittent opening 221a and extend away from the shielding portion 210, and by the arrangement of the extending traces 223, the static charge in the first antistatic trace 221 is continuously conducted along the extending trace 223 in a direction away from the shielding portion 210, namely, the concentrated position at the intermittent opening 221a is moved in a direction away from the shielding portion 210, so that the electrostatic charge rate of the panel can be reduced, and the electrostatic explosion damage can be prevented, even though the electrostatic explosion damage is not caused.
In some embodiments, two intermittent openings may be disposed on the first anti-static wire to further improve the static protection effect of the anti-static portion 220, referring to fig. 5, the first anti-static wire 221 includes a first anti-static wire subsection 2211 located outside the shielding portion 210 along the first direction X, two intermittent openings 221a are disposed on the first anti-static wire subsection 2211, and in order to increase the distance between the two intermittent openings 221a, the two intermittent openings 221a are disposed at two ends of the first anti-static wire subsection 2211, respectively, so that, on one hand, static charges originally concentrated in one intermittent opening 221a are shunted to the areas corresponding to the two intermittent openings 221a, so that the risk of electrostatic damage caused by the static charges concentrated in the first anti-static wire 221 is greatly reduced, and on the other hand, the two intermittent openings 221a are used as ports for transferring static charges onto the substrate in the first anti-static wire 221, that is, so that the static charges transferred onto the substrate 221 in the first anti-static wire 221 are effectively improved.
In some embodiments, referring to fig. 6, in order to further enhance the electrostatic protection effect of the electrostatic prevention portion 220, the electrostatic prevention portion 220 includes a second electrostatic prevention trace 224 and at least one second bridge section 225, the second electrostatic prevention trace 224 is a closed loop trace disposed around the shielding portion 210 and located inside the first electrostatic prevention trace 221, the second electrostatic prevention trace 224 is electrically connected to the shielding portion 210 through the second bridge section 225, and the first electrostatic prevention trace is electrically connected to the second electrostatic prevention trace through the first bridge section, i.e., the second electrostatic prevention trace 224 is used as a bridge structure bridging the shielding portion 210 and the first electrostatic prevention trace 221, so as to assist in conducting the electrostatic charge in the shielding portion 210 to the first electrostatic prevention trace 221, i.e., enhancing the efficiency of conducting the electrostatic charge in the shielding portion 210 to the electrostatic prevention portion 220, thereby enhancing the electrostatic protection effect of the electrostatic prevention portion 220.
The number of the second bridge segments 225 may be as large as possible, so as to improve the conductivity between the shielding portion 210 and the second antistatic trace 224, which is beneficial for transmitting the static charge in the shielding portion 210 to the second antistatic trace 224, and illustratively, each shielding sub-portion 211 adjacent to the second antistatic trace 224 in the shielding portion 210 is connected to the second antistatic trace 224 through one first bridge segment 222, and eight second bridge segment 225 structures are exemplarily drawn in the figure, which is set according to specific process requirements in practical application.
In some embodiments, due to the arrangement of the intermittent opening 221a, the risk of the first anti-static electricity trace 221 being damaged by static electricity is higher than that of the second anti-static electricity trace 224, and when the space for arranging the anti-static electricity portion 220 on the peripheral side of the shielding portion 210 is limited, the width of the first anti-static electricity trace 221 is set to be greater than that of the second anti-static electricity trace 224, so as to increase the resistance of the first anti-static electricity trace 221, thereby reducing the risk of the first anti-static electricity trace 221 being damaged by static electricity.
In some embodiments, referring to fig. 2 and fig. 7 or fig. 8, the shielding portion 210 includes a shielding sub-portion 211 corresponding to the driving thin film transistors and a first connection trace 212 connected to the adjacent shielding sub-portion 211, and referring to fig. 7 or fig. 8, the first anti-static trace 221 includes a plurality of anti-static sub-portions 2212 spaced along the extending direction of the first anti-static trace 221 and a second connection trace 2213 connected to the adjacent anti-static sub-portion 2212, wherein the front projection of the shielding sub-portion 211 on the substrate 100 is the same as the front projection of the anti-static sub-portion 2212 on the substrate 100, and the widths of the first connection trace 212 and the second connection trace 2213 are equal, i.e. the pattern of the first anti-static trace 221 is the same as the pattern of the shielding portion 210, so as to reduce the etching difficulty in the manufacturing process of the shielding metal layer 200 in order to improve the accuracy of the pattern formed by patterning the shielding metal layer 200.
It can be appreciated that the number of the antistatic sub-portions 2212 arranged along the width direction is adjusted according to the actual width of the first antistatic trace 221, and one antistatic sub-portion 2212 is exemplarily arranged along the width direction of the first antistatic trace 221, i.e. see fig. 8, or two antistatic sub-portions 2212 are arranged along the width direction of the first antistatic trace 221, i.e. see fig. 9.
It is added that, when the second antistatic trace 224 in the foregoing embodiment is disposed, the pattern of the second antistatic trace 224 is disposed with reference to the first antistatic trace 221, and in addition, the widths of the first bridge stage 222 and the second bridge stage 225 are disposed with reference to the first connection trace 212.
Further, in some embodiments, the shape of the front projection of the shielding sub-portion 211 on the substrate 100 and the front projection of the anti-static sub-portion 2212 on the substrate 100 is rounded rectangle or other rounded shape, such as circle or ellipse, so as to reduce the risk of the occurrence of the tip discharge in the plane of the shielding metal layer 200.
In some embodiments, referring to fig. 9, the display panel includes a display area a and a frame area B disposed at a peripheral side of the display area a, and the first anti-static wire 221 is disposed in the frame area B, i.e. the first anti-static wire 221 is far away from the shielding portion 210 disposed in the display area a as far as possible, so as to reduce the risk of the shielding portion 210 being affected by static explosion of the first anti-static wire 221.
In some embodiments, the array driving layer 300 includes a gate driving circuit disposed in the frame area B, where the frame area B includes a first frame area B1, a second frame area B2, a third frame area B3, and a fourth frame area B4 disposed around the display area a, and the gate driving circuit is typically disposed in the second frame area B2 and the fourth frame area B4 that are opposite to each other;
Specifically, referring to the cross-sectional structure at the mm' position in fig. 9 shown in fig. 10, the gate driving circuit includes a plurality of circuit thin film transistors TFT2, one of the circuit thin film transistors TFT2 includes a channel portion 321, the front projection of the first anti-static wire 221 on the substrate 100 coincides with the front projection of the gate driving circuit on the substrate 100, and the front projection of the first anti-static wire 221 on the substrate 100 does not coincide with the front projections of the plurality of channel portions 321 on the substrate 100, i.e. on the premise that the first anti-static wire 221 does not affect the gate driving circuit, the problem that the width of the frame region B increases due to the arrangement of the first anti-static wire 221 is avoided.
Further, in some embodiments, referring to another cross-sectional structure at the mm' position in fig. 9 shown in fig. 11, the orthographic projection of the antistatic portion 220 on the substrate 100 is located on the outer side of the orthographic projection of the corresponding circuit thin film transistor TFT2 on the substrate 100, which is far away from the display area a direction, that is, the first antistatic trace 221 is disposed on the periphery of the gate driving circuit, so as to effectively perform antistatic protection on the gate driving circuit.
In some embodiments, the buffer layer 310 includes a first buffer layer and a second buffer layer that are stacked, and the shielding metal layer is disposed between the first buffer layer and the second buffer layer, so that the shielding metal layer is prevented from being directly formed on the second flexible substrate 130, and the shielding metal layer is ensured to have a better film forming atmosphere, so that the shielding metal layer has a better film quality.
It should be noted that, in the above display panel embodiment, only the above structure is described, and it is to be understood that, in addition to the above structure, any other necessary structure may be included in the display panel provided in the embodiment of the present invention as needed, and the present invention is not limited thereto.
Still another embodiment of the present invention provides a method for manufacturing a display panel, referring to fig. 12, the method includes the following steps:
s10: providing a substrate, forming a shielding metal layer on the substrate, wherein the shielding metal layer comprises a shielding part and an antistatic part formed on the periphery of the shielding part, the antistatic part comprises a first antistatic wiring surrounding the shielding part and at least one first bridging section, the first antistatic wiring is electrically connected with the shielding part through the first bridging section, and the first antistatic wiring is an annular wiring with an intermittent opening;
s20: and forming an array driving layer on the shielding metal layer, wherein the array driving layer comprises a plurality of driving thin film transistors correspondingly arranged on the shielding part.
The following is detailed in connection with fig. 13 a-13 c:
Referring to fig. 13a, a substrate 100 is provided, the substrate 100 includes a first flexible substrate 110, a second flexible substrate 130, and a barrier layer 120 disposed between the first flexible substrate 110 and the second flexible substrate 130;
Referring to fig. 13b, the shielding metal layer 200 is formed on the second flexible substrate 130 in the substrate 100, where the shielding metal layer 200 includes a shielding portion 210 and an antistatic portion 220 formed on a peripheral side of the shielding portion 210, the antistatic portion 220 includes a first antistatic trace 221 surrounding the shielding portion 210 and at least one first bridge segment 222, the first antistatic trace 221 is electrically connected with the shielding portion 210 through the first bridge segment 222, and the first antistatic trace 221 is an annular trace including an intermittent opening 221 a;
referring to fig. 13c, an array driving layer 300 is formed on the shielding metal layer 200, where the array driving layer 300 is generally formed by sequentially stacking a buffer layer 310, an active layer 320, a first insulating layer 330, a first metal layer 340, a second insulating layer 350, a second metal layer 360, a third insulating layer 370 and a third metal layer 380, each of the stacked layers includes a plurality of driving thin film transistors TFT1 correspondingly disposed in each pixel region for driving display, and a plurality of the driving thin film transistors TFT1 are correspondingly formed in the shielding portion 210.
Forming the active layer 320 specifically includes forming an amorphous silicon thin film on the buffer layer 310, performing an excimer laser annealing process by scanning and irradiating the amorphous silicon thin film along a first direction X with an excimer laser beam, so that the amorphous silicon thin film is recrystallized and converted into a low-temperature polysilicon thin film, and patterning the low-temperature polysilicon thin film to form the active layer;
Meanwhile, the first anti-static wire 221 includes a first anti-static wire segment 2211 located at the outer side of the shielding part 210 along the first direction X, and then the intermittent opening 221a is disposed on the first anti-static wire segment 2211, so that in the excimer laser annealing process, static charges in the first anti-static wire 221 are conducted to the end portion of the first anti-static wire segment 2211 located at the intermittent opening 221a along the first direction X, and then transferred to the substrate 100, and finally moved along the structure connected to the back of the substrate, and by this design, the problems that static charges are damaged due to static concentration in the shielding part 210 in the excimer laser annealing process, and thus the yield and reliability of the display panel are affected can be further avoided.
Another embodiment of the present invention further provides a display device, where the display device includes the display panel provided in the foregoing embodiment, and the display device includes, but is not limited to, a mobile phone, a smart watch, a tablet computer, a notebook computer, a television, and the like.
The foregoing has described in detail a display panel and a method for manufacturing the same, which are provided by the embodiments of the present invention, wherein specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (8)
1. A display panel, the display panel comprising:
A substrate;
a shielding metal layer disposed on the substrate;
the array driving layer is arranged on the shielding metal layer and comprises a plurality of driving thin film transistors;
The shielding metal layer comprises a shielding part and an anti-static part, wherein the shielding part corresponds to the driving thin film transistor, the anti-static part is arranged on the periphery of the shielding part, the anti-static part comprises a first anti-static wire and at least one first bridging section, the first anti-static wire is electrically connected with the shielding part through the first bridging section, the first anti-static wire comprises an intermittent open annular wire, the anti-static part comprises a second anti-static wire and at least one second bridging section, the second anti-static wire is a closed annular wire which is arranged around the shielding part and is positioned in the first anti-static wire, the second anti-static wire is electrically connected with the shielding part through the second bridging section, the first anti-static wire is electrically connected with the second anti-static wire through the first bridging section, the first anti-static wire is wider than the second anti-static wire, the shielding part comprises a plurality of corresponding transistors, the second anti-static wire is arranged on the adjacent to the shielding part, the second anti-static wire is connected with the electronic projection part along the same shape, and the electronic projection part is connected with the adjacent anti-static part, and the electronic projection part is arranged on the same in the shape.
2. The display panel according to claim 1, wherein the antistatic part further comprises two extending wires, and the two extending wires are respectively connected to two ends of the first antistatic wire at the break opening and extend away from the shielding part.
3. The display panel according to claim 1, wherein the first anti-static wiring comprises a first anti-static wiring sub-section located in a first direction of the shielding part, two intermittent openings are formed in the first anti-static wiring sub-section, and the two intermittent openings are located at two ends of the first anti-static wiring sub-section respectively.
4. The display panel of claim 1, wherein the first connection trace and the second connection trace have equal widths.
5. The display panel of claim 4, wherein the shape of the orthographic projection of the shielding sub-portion on the substrate and the orthographic projection of the anti-static sub-portion on the substrate is rounded rectangle.
6. The display panel of claim 1, wherein the display panel comprises a display area and a frame area disposed on a peripheral side of the display area, and the first antistatic trace is disposed in the frame area.
7. The display panel of claim 6, wherein the array driving layer includes a gate driving circuit disposed in the frame region, the gate driving circuit includes a plurality of circuit thin film transistors, one of the circuit thin film transistors includes a channel portion, an orthographic projection of the antistatic portion on the substrate coincides with an orthographic projection of the gate driving circuit on the substrate, and an orthographic projection of the antistatic portion on the substrate does not coincide with orthographic projections of a plurality of the channel portions on the substrate.
8. A method for manufacturing a display panel according to any one of claims 1 to 7, characterized in that the method comprises the steps of:
s10: providing a substrate, forming a shielding metal layer on the substrate, wherein the shielding metal layer comprises a shielding part and an antistatic part formed on the periphery of the shielding part, the antistatic part comprises a first antistatic wiring surrounding the shielding part and at least one first bridging section, the first antistatic wiring is electrically connected with the shielding part through the first bridging section, and the first antistatic wiring is an annular wiring with an intermittent opening;
s20: and forming an array driving layer on the shielding metal layer, wherein the array driving layer comprises a plurality of driving thin film transistors correspondingly arranged on the shielding part.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108170317A (en) * | 2018-01-05 | 2018-06-15 | 京东方科技集团股份有限公司 | Array substrate |
| CN114551438A (en) * | 2022-02-24 | 2022-05-27 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| CN106783842B (en) * | 2017-01-04 | 2019-05-17 | 京东方科技集团股份有限公司 | A kind of electrostatic discharge protective circuit, array substrate, display panel and display device |
| CN110600505A (en) * | 2019-08-20 | 2019-12-20 | 武汉华星光电半导体显示技术有限公司 | OLED display device |
| US11782562B2 (en) * | 2020-09-17 | 2023-10-10 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Touch panel, touch display panel, and electronic device |
| CN112670270B (en) * | 2020-12-22 | 2024-01-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113097261B (en) * | 2021-03-24 | 2022-10-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN114613786A (en) * | 2022-02-25 | 2022-06-10 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108170317A (en) * | 2018-01-05 | 2018-06-15 | 京东方科技集团股份有限公司 | Array substrate |
| CN114551438A (en) * | 2022-02-24 | 2022-05-27 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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