CN113138504B

CN113138504B - Display panel, manufacturing method thereof and display device

Info

Publication number: CN113138504B
Application number: CN202110460440.5A
Authority: CN
Inventors: 王海亮; 李雅缨; 曾晓岚; 杨雁; 周婷; 李俊谊
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-04-27
Filing date: 2021-04-27
Publication date: 2022-09-16
Anticipated expiration: 2041-04-27
Also published as: CN113138504A; CN115421338A

Abstract

The embodiment of the invention provides a display panel, a manufacturing method thereof and a display device, relates to the technical field of display, and aims to enable an optical component setting area to have excellent imaging quality and display effect. The display panel includes: the display panel comprises a first display area, a second display area and a third display area, wherein the first display area comprises a first scanning line and a first data line, the first scanning line and the first data line define a first sub-pixel area, and the first sub-pixel area comprises a first common electrode and a first pixel electrode; a substrate base plate; a planarization layer; the first light-transmitting conducting layer is positioned on one side, back to the substrate, of the planarization layer, and the first common electrode is positioned on the first light-transmitting conducting layer; the second light-transmitting conducting layer is positioned on one side, back to the substrate base plate, of the first light-transmitting conducting layer, and the first pixel electrode is positioned on the second light-transmitting conducting layer; the first data lines are formed of a light-transmitting conductive material on a side of the planarization layer facing the substrate, and/or the first scan lines are formed of a light-transmitting conductive material on a side of the planarization layer facing the substrate.

Description

Display panel, manufacturing method thereof and display device

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a display device.

[ background of the invention ]

In order to increase the screen ratio of a display panel having an image pickup function, an optical component installation area is generally provided in a display area of the panel, and an image pickup module is provided in the optical component installation area.

In the prior art, to solve the problem of insufficient light transmittance during image pickup in the optical component setting area, the signal line in the optical component setting area is usually formed by using a light-transmitting conductive material, and the black matrix above the signal line is removed at the same time. However, although the above design increases the transmittance of the optical component installation area, it adversely affects the display of the optical component installation area, and thus it is difficult for the optical component installation area to have both excellent image quality and display effect.

[ summary of the invention ]

In view of this, embodiments of the present invention provide a display panel and a display apparatus, so that the optical component installation region has both excellent imaging quality and display effect.

In one aspect, an embodiment of the present invention provides a display panel, including:

the display device comprises a first display area, a second display area and a third display area, wherein the first display area comprises a first scanning line and a first data line, the first scanning line and the first data line define a plurality of first sub-pixel areas, and the first sub-pixel areas comprise a first common electrode and a first pixel electrode;

a substrate base plate;

a planarization layer on the substrate base plate;

the first light-transmitting conducting layer is positioned on one side, back to the substrate base plate, of the planarization layer, and the first common electrode is positioned on the first light-transmitting conducting layer;

the second light-transmitting conducting layer is positioned on one side, back to the substrate, of the first light-transmitting conducting layer, and the first pixel electrode is positioned on the second light-transmitting conducting layer;

wherein the first data line is formed by a light-transmitting conductive material and is positioned on one side of the planarization layer facing the substrate base plate, and/or the first scanning line is formed by a light-transmitting conductive material and is positioned on one side of the planarization layer facing the substrate base plate.

In another aspect, an embodiment of the present invention provides a method for manufacturing a display panel, including:

forming a first data line and/or a first scanning line in a first display area of a substrate, wherein the first data line and/or the first scanning line are/is formed by a light-transmitting conductive material;

forming a planarization layer on one side of the first data line and/or the first scanning line, which faces away from the substrate base plate;

forming a first light-transmitting conductive layer on one side, opposite to the substrate, of the planarization layer, wherein the first light-transmitting conductive layer comprises a first common electrode;

and forming a second light-transmitting conductive layer on one side of the first light-transmitting conductive layer, which faces away from the substrate base plate, wherein the second light-transmitting conductive layer comprises a first pixel electrode.

In another aspect, an embodiment of the present invention provides a display device, including the display panel described above.

The technical scheme has the following beneficial effects:

in the embodiment of the invention, the first data line and/or the first scan line are/is arranged on one side of the planarization layer facing the substrate, and the planarization layer can be used for increasing the distance between the first data line and/or the first scan line and the liquid crystal molecules, so that the first data line and the first scan line are far away from the liquid crystal molecules. On the other hand, the first common electrode receives a fixed common voltage signal, and can shield the influence of an interference electric field generated by voltage jump on the first data line and the first scanning line below the first common electrode on liquid crystal molecules, so that the risk of abnormal display in the first display area is reduced to a greater extent.

In addition, in the embodiment of the invention, the first data line and/or the first scan line are/is located on the side of the planarization layer facing the substrate, and based on the structure, in the process flow of the panel, the first data line and/or the first scan line are/is firstly formed, and then the planarization layer is formed, and the first data line and the first scan line do not need to be deposited on the planarization layer, so that the problem that the first data line and the first scan line are easy to peel off due to poor adhesion between a resin material forming the planarization layer and an Indium Tin Oxide (ITO) material forming the first data line and the first scan line is also avoided, the stability of the first data line and the first scan line in the panel is improved, and the transmission reliability of the data signal and the scan signal is improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a top view of a prior art optical component placement area of a display panel;

FIG. 2 is a cross-sectional view taken along the line A1 '-A2' of FIG. 1;

FIG. 3 is a top view of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating the arrangement positions of a first data line and a first scan line according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a dark line at the position of a data line in an optical component placement area according to the prior art;

FIG. 6 is a schematic diagram of a dark line at a position of a first data line in a first display area according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a connection between a first data line and a first scan line according to an embodiment of the present invention;

FIG. 8 is a cross-sectional view taken along line A1-A2 of FIG. 7;

FIG. 9 is a schematic diagram illustrating another connection between a first data line and a first scan line according to an embodiment of the present invention;

FIG. 10 is a cross-sectional view taken along line B1-B2 of FIG. 9;

FIG. 11 is a schematic diagram illustrating dimensions of vias in a first passivation layer and a second interlayer insulating layer provided in accordance with an embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating another arrangement position of the first data line and the first scan line according to the embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating another arrangement position of the first data line and the first scan line according to the embodiment of the present invention;

FIG. 14 is a schematic diagram illustrating the connection between the first data line and the first scan line in FIG. 12;

FIG. 15 is a schematic diagram illustrating the connection between the first data line and the first scan line in FIG. 13;

FIG. 16 is another connection diagram of the first data line and the first scan line corresponding to FIG. 12;

FIG. 17 is another connection diagram of the first data line and the first scan line corresponding to FIG. 13;

FIG. 18 is a schematic diagram illustrating another arrangement position of the first data line and the first scan line according to the embodiment of the present invention;

FIG. 19 is a schematic diagram illustrating another arrangement position of the first data line and the first scan line according to the embodiment of the present invention;

FIG. 20 is a schematic diagram illustrating the connection between the first data line and the first scan line in FIG. 18;

FIG. 21 is a schematic diagram illustrating the connection between the first data line and the first scan line in FIG. 19;

FIG. 22 is a schematic view of another connection of the first data line and the first scan line corresponding to FIG. 18;

FIG. 23 is another connection diagram of the first data line and the first scan line corresponding to FIG. 19;

FIG. 24 is a schematic view of another connection of the first data line and the first scan line of FIG. 18;

FIG. 25 is a schematic view of another connection of the first data line and the first scan line corresponding to FIG. 19;

fig. 26 is a schematic structural diagram of a fourth passivation layer according to an embodiment of the present invention;

fig. 27 is a schematic structural diagram of a fifth passivation layer according to an embodiment of the present invention;

FIG. 28 is a schematic diagram showing another arrangement position of the first data lines and the first scan lines according to an embodiment of the present invention;

FIG. 29 is a schematic diagram illustrating the connection between the first data line and the first scan line in FIG. 28;

FIG. 30 is another schematic connection diagram of the first data line and the first scan line corresponding to FIG. 28;

FIG. 31 is a schematic view of still another connection of the first data line and the first scan line of FIG. 28;

FIG. 32 is a schematic diagram illustrating dimensions of a first scan line and a first data line according to an embodiment of the present invention;

FIG. 33 is a schematic diagram illustrating the dimensions of a driving transistor according to an embodiment of the present invention;

FIG. 34 is a schematic diagram of another dimension of a driving transistor according to an embodiment of the invention;

fig. 35 is a schematic structural diagram of a display panel according to an embodiment of the invention;

FIG. 36 is a schematic structural diagram of a light shielding portion according to an embodiment of the present invention;

FIG. 37 is a schematic diagram illustrating dimensions of a light shielding portion according to an embodiment of the present invention;

fig. 38 is a schematic view illustrating a position of a touch layer according to an embodiment of the present invention;

FIG. 39 is a schematic view of another arrangement position of a touch layer according to an embodiment of the disclosure;

fig. 40 is a schematic view of another arrangement position of the touch layer according to the embodiment of the invention;

FIG. 41 is a cross-sectional view taken along the line C1-C2 of FIG. 40;

FIG. 42 is a schematic structural diagram of a second display area according to an embodiment of the present invention;

fig. 43 is a flowchart of a method for manufacturing a display panel according to an embodiment of the invention;

FIG. 44 is a flowchart illustrating a method for fabricating a display panel according to an embodiment of the present invention;

fig. 45 is a schematic structural diagram of a first passivation layer and a second passivation layer provided in an embodiment of the present invention;

fig. 46 is another schematic structural diagram of a first passivation layer and a second passivation layer provided in an embodiment of the present invention;

fig. 47 is a schematic view of another structure of the first passivation layer and the second passivation layer according to the embodiment of the invention;

fig. 48 is a schematic structural diagram of a display device according to an embodiment of the present invention.

[ detailed description ] embodiments

In order to better understand the technical scheme of the invention, the following detailed description of the embodiments of the invention is made with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used to describe the light-transmitting conductive layers in the embodiments of the present invention, the light-transmitting conductive layers should not be limited to these terms. These terms are only used to distinguish the light-transmitting conductive layers from each other. For example, the first light-transmitting conductive layer may also be referred to as a second light-transmitting conductive layer, and similarly, the second light-transmitting conductive layer may also be referred to as a first light-transmitting conductive layer without departing from the scope of the embodiments of the present invention.

Before describing the technical solutions provided by the embodiments of the present invention, the present invention first describes the problems existing in the prior art.

The display panel includes scan lines and data lines, where the scan lines and the data lines intersect to define a plurality of sub-pixel regions, each of which includes a common electrode and a pixel electrode, and the common electrode and the pixel electrode are usually formed by using a light-transmitting conductive material such as Indium Tin Oxide (ITO).

In connection with the analysis in the background art, in order to solve the problem of insufficient light transmittance when the optical member setting region is imaged, as shown in fig. 1 and 2, fig. 1 is a top view of the optical member setting region of the display panel in the related art, fig. 2 is a sectional view of fig. 1 along a direction a1 ' -a2 ', the scanning line Gate ' and the Data line Data ' in the optical member setting region are disposed in the same layer and material as the common electrode 1 ', and the scanning line Gate ' and the Data line Data ' are not covered with the black matrix.

However, in order to drive the display panel to work normally, the voltages on the scan lines and the data lines in the panel need to be continuously changed. Taking the data line as an example, with the progressive scanning of the scanning lines, when the ith scanning line outputs a scanning signal to the ith row of sub-pixels, the jth data line transmits a data voltage required to be received by the ith row and jth column of sub-pixels, and when the (i + 1) th scanning line outputs a scanning signal to the (i + 1) th row of sub-pixels, the voltage on the jth data line jumps to the data voltage required by the (i + 1) th row and jth column of sub-pixels.

The voltage jumps on the scan lines and the data lines cause the liquid crystal molecules 2' on the upper sides of the scan lines and the data lines to rotate. Because there is no black matrix above the scanning line Gate ' and the Data line Data ' in the optical component setting region, the continuous rotation of the liquid crystal molecules 2 ' can make the picture displayed at the position of the scanning line Gate ' and the Data line Data ' continuously flicker, and the continuous flicker of the picture can lead to the obvious dark brightness of the part of the region in vision, thereby leading to the obvious dark line phenomenon at the position of the scanning line Gate ' and the Data line Data '.

In addition, referring to fig. 2 again, when the scan line Gate 'and the Data line Data' are disposed on the same layer as the common electrode 1 ', the scan line Gate' and the Data line Data 'are formed over the planarization layer 3'. The planarization layer 3 ' is usually made of an organic material such as resin, and the resin material has poor adhesion to an Indium Tin Oxide (ITO) material forming the scan line Gate ' and the Data line Data ', which causes the Indium Tin oxide material to be easily peeled off. In particular, the scanning line Gate 'and the Data line Data' have a thin line structure, and the risk of peeling is greater, and the risk of display abnormality in the optical member disposition region is also greater.

Therefore, the embodiment of the invention provides a display panel, which can solve the problem of insufficient light transmittance of the optical component setting area, and simultaneously avoid adverse effects on the display of the optical component setting area, so that the optical component setting area has better imaging quality and display effect.

As shown in fig. 3 and 4, fig. 3 is a top view of a display panel according to an embodiment of the present invention, and fig. 4 is a schematic diagram of arrangement positions of a first data line and a first scan line according to an embodiment of the present invention, the display panel according to an embodiment of the present invention includes a first display area 1, the first display area 1 may be the optical component arrangement area, and the first display area 1 is provided with an image pickup assembly for implementing an image pickup function. The first display region 1 includes a first scan line Gate1 and a first Data line Data1, the first scan line Gate1 and the first Data line Data1 define a plurality of first sub-pixel regions 3, and the first sub-pixel regions 3 include a first common electrode 4 and a first pixel electrode 5.

In addition, the display panel further includes: a base substrate 6, a planarization layer 7, a first light-transmissive electrically conductive layer 8 and a second light-transmissive electrically conductive layer 9. Wherein, the planarization layer 7 is positioned on the substrate base plate 6; the first light-transmitting conductive layer 8 is positioned on one side of the planarization layer 7, which is opposite to the substrate base plate 6, and the first common electrode 4 is positioned on the first light-transmitting conductive layer 8; the second light-transmitting conductive layer 9 is located on the side of the first light-transmitting conductive layer 8 opposite to the substrate base plate 6, and the first pixel electrode 5 is located on the second light-transmitting conductive layer 9. The first light-transmitting conductive layer 8 and the second light-transmitting conductive layer 9 may be formed of a light-transmitting conductive material such as indium tin oxide.

The first Data line Data1 is made of transparent conductive material such as indium tin oxide, the first Data line Data1 is located on the side of the planarization layer 7 facing the substrate 6, and/or the first scan line Gate1 is made of transparent conductive material such as indium tin oxide, and the first scan line Gate1 is located on the side of the planarization layer 7 facing the substrate 6.

It should be noted that, in order to achieve film planarization, the film thickness of the planarization layer 7 in the direction perpendicular to the plane of the substrate 6 is usually much larger than the film thickness of other films in the panel in the direction perpendicular to the plane of the substrate 6. In the embodiment of the present invention, by disposing the first Data line Data1 and/or the first scan line Gate1 on the side of the planarization layer 7 facing the substrate 6, the planarization layer 7 can be used to increase the distance between the first Data line Data1 and/or the first scan line Gate1 and the liquid crystal molecules, so that the first Data line Data1 and the first scan line Gate1 are far away from the liquid crystal molecules, and thus, even if the voltage jumps on the first Data line Data1 and the first scan line Gate1 occur, the liquid crystal molecules are hardly affected, the abnormal display problem of the first display area 1 caused by the jumps of the Data signals and the scan signals is effectively reduced, and the dark line phenomenon is weakened or even eliminated. On the other hand, the first common electrode 4 receives a fixed common voltage signal, and can also shield the influence of an interference electric field generated by voltage jumps on the first Data line Data1 and the first scan line Gate1 below the first common electrode on the liquid crystal molecules, thereby reducing the risk of abnormal display in the first display area 1 to a greater extent.

Further, the inventors have also verified this, and as shown in fig. 5 and fig. 6, fig. 5 is a schematic diagram of a dark line at the position of the Data line Data' in the optical member disposition region in the related art, and fig. 6 is a schematic diagram of a dark line at the position of the first Data line Data1 in the first display region 1 provided by the embodiment of the present invention, in which the abscissa and ordinate respectively represent position points in the X direction and the Y direction. As can be seen from comparing fig. 5 and fig. 6, the dark line in the first display area is significantly weakened and is difficult to be recognized by human eyes based on the structure provided by the embodiment of the present invention.

In addition, in the embodiment of the invention, the first Data line Data1 and/or the first scan line Gate1 are/is located on the side of the planarization layer 7 facing the substrate 6, based on the structure, in the process flow of the panel, the first Data line Data1 and/or the first scan line Gate1 are/is formed first, and then the planarization layer 7 is formed, the first Data line Data1 and the first scan line Gate1 do not need to be deposited on the planarization layer 7, so that the problem that the first Data line Data1 and the first scan line Gate1 are easy to peel off due to poor adhesion of a resin material and an indium tin oxide material is avoided, the stability of the first Data line Data1 and the first scan line Gate1 in the panel is improved, and the transmission reliability of the Data signal and the scan signal is improved.

In one embodiment, referring to fig. 3 and fig. 4 again, the first sub-pixel region 3 further includes a driving transistor 10, a Gate11 of the driving transistor 10 is electrically connected to the first scan line Gate1, a first electrode 12 of the driving transistor 10 is electrically connected to the first Data line Data1, and a second electrode 13 of the driving transistor 10 is electrically connected to the first pixel electrode 5 of the first sub-pixel region 3.

Based on this, the display panel further includes: a semiconductor layer 14, the semiconductor layer 14 being located on a side of the planarization layer 7 facing the base substrate 6, an active layer 15 of the driving transistor 10 being located on the semiconductor layer 14; a first interlayer insulating layer 16, wherein the first interlayer insulating layer 16 is positioned on the side of the semiconductor layer 14, which faces away from the substrate base plate 6; a first metal layer 17, wherein the first metal layer 17 is positioned on one side of the first interlayer insulating layer 16, which faces away from the substrate base plate 6, and the gate11 of the driving transistor 10 is positioned on the first metal layer 17; a second interlayer insulating layer 18, wherein the second interlayer insulating layer 18 is positioned on one side of the first metal layer 17, which faces away from the substrate base plate 6; and a second metal layer 19, the second metal layer 19 being located between the second interlayer insulating layer 18 and the planarization layer 7, and the first and

second poles

12 and 13 of the driving transistor 10 being located on the second metal layer 19.

When the display panel displays images, the first scan line Gate1 provides a scan signal to the Gate11 of the driving transistor 10 to control the driving transistor 10 to be turned on, the display Data voltage provided by the first Data line Data1 is transmitted to the first pixel electrode 5 electrically connected with the driving transistor 10 through the turned-on driving transistor 10, and the liquid crystal molecules rotate under the action of the electric field formed by the first pixel electrode 5 and the first common electrode 4 to realize normal image display. When the display panel takes an image, the first scan line Gate1 provides a scan signal to the Gate11 of the driving transistor 10 to control the driving transistor 10 to be turned on, the image Data voltage provided by the first Data line Data1, such as a white voltage corresponding to 255 gray scale, is transmitted to the first pixel electrode 5 electrically connected to the driving transistor 10 through the turned-on driving transistor 10, the liquid crystal molecules rotate under the action of the electric field formed by the first pixel electrode 5 and the first common electrode 4, and the external ambient light penetrates through the liquid crystal molecules and enters the image pickup device to realize image formation.

In an embodiment, referring to fig. 4 again, the display panel further includes a third transparent conductive layer 20, the first Data line Data1 and the first scan line Gate1 are both located on the third transparent conductive layer 20, at this time, the first Data line Data1 and the first scan line Gate1 are disposed in the same layer, and the two routing lines only occupy one film thickness, which is more beneficial to the light and thin design of the panel.

Specifically, when the first Data line Data1 and the first scan line Gate1 are both located on the third light-transmitting conductive layer 20, the structure of the panel will be described by taking the following three arrangements as examples in the embodiment of the present invention.

The first setting mode is as follows:

referring to fig. 4 again, the display panel further includes a first passivation layer 21, the first passivation layer 21 is located between the second metal layer 19 and the planarization layer 7, and the third light-transmissive conductive layer 20 is located between the first passivation layer 21 and the planarization layer 7.

In this arrangement, the third transparent conductive layer 20 does not change the original process flow of the driving transistor 10, and only the process flow of the third transparent conductive layer 20 needs to be added after the driving transistor 10 is formed, so that the manufacturing process of the panel is simpler and more convenient. In addition, wet etching is mostly adopted for etching transparent conductive materials such as indium tin oxide, and a first passivation layer 21 is additionally arranged between the third transparent conductive layer 20 and the second metal layer 19, so that the second metal layer 19 can be protected by the first passivation layer 21, the metal in the second metal layer 19 is prevented from being etched by the wet etching process of the third transparent conductive layer 20, and the reliability of signal transmission in the second metal layer 19 is improved.

Further, as shown in fig. 7 and fig. 8, fig. 7 is a schematic connection diagram of the first Data line Data1 and the first scan line Gate1 according to the embodiment of the present invention, fig. 8 is a cross-sectional view of fig. 7 along the direction a1-a2, the first scan line Gate1 includes a first scan line Gate11 and a second scan line Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, the first end 22 is electrically connected to the first scan line Gate11, and the second end 23 is electrically connected to the second scan line Gate 12.

The first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first pole 12 of the driving transistor 10 includes a third terminal 24 and a fourth terminal 25, the first passivation layer 21 includes a first via 26 and a second via 27, the first Data line segment Data11 is electrically connected to the third terminal 24 through the first via 26, the second Data line segment Data12 is electrically connected to the fourth terminal 25 through the second via 27, and the third terminal 24 is also electrically connected to the active layer 15 of the driving transistor 10.

In the above structure, the first Data line Data1 and the first scan line Gate1 both adopt a broken line design at the overlapping position, the first pole 12 of the driving transistor 10 is used as a metal bridge between the first Data line segment Data11 and the second Data line segment Data12, and the Gate11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, so that the effective electrical connection between the first Data line segment Data11 and the second Data line segment Data12, and between the first scan line segment Gate11 and the second scan line segment Gate12 are ensured, no additional bridge structure is required, and the process is simplified. In addition, compared with the light-transmitting conductive material such as indium tin oxide, the load of the metal material is smaller, so the design can reduce the overall load of the first Data line Data1 and the first scan line Gate1 by using the metal bridge, and further reduce the attenuation of the Data signal and the scan signal in the transmission process.

In addition, referring to fig. 7 again, the length of the first electrode 12 of the driving transistor 10 in the extending direction thereof is K, and in order to ensure that the first electrode 12 of the driving transistor 10 has a sufficient length so that the first electrode 12 has a large overlapping area with the first Data line segment Data11 and the second Data line segment Data12, and improve the reliability of the connection, K may satisfy: k is more than or equal to 15 mu m and less than or equal to 25 mu m.

Alternatively, in another implementation, as shown in fig. 9 and 10, fig. 9 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 provided by the embodiment of the present invention, fig. 10 is a cross-sectional view of fig. 9 along the direction B1-B2, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, the first end 22 is electrically connected to the first scan line segment Gate11, and the second end 23 is electrically connected to the second scan line segment Gate 12. In a direction perpendicular to the plane of the substrate base plate 6, a projection of the first Data line Data1 overlaps a projection of the gate electrode 11 of the driving transistor 10, the first passivation layer 21 includes a third via 28, the first Data line Data1 is electrically connected to the first pole 12 of the driving transistor 10 through the third via 28, and the first pole 12 of the driving transistor 10 is also electrically connected to the active layer 15 of the driving transistor 10.

In the above structure, the Gate11 of the driving transistor 10 is used as a metal bridge between the first scanning line segment Gate11 and the second scanning line segment Gate12, and since the Gate11 of the driving transistor 10 and the first Data line Data1 are arranged in different layers, even if the first Data line Data1 is designed such that the continuous routing lines overlap with the Gate11 of the driving transistor 10, signal interference is not caused. Moreover, when the first Data line Data1 is routed continuously, the first pole 12 of the driving transistor 10 does not need to serve as a metal bridge, so that the shielding of metal to the external ambient light can be reduced by reducing the size of the first pole 12 of the driving transistor 10, a greater amount of external ambient light is transmitted through the first display area 1 to enter the camera module, and the imaging quality is effectively improved.

Based on the structure shown in fig. 7 and 9, in an embodiment, referring to fig. 7 and 9 again, the second metal layer 19 further includes a first auxiliary connection 29 and a second auxiliary connection 30, the first auxiliary connection 29 is electrically connected between the first scan line segment Gate11 and the first end 22, and the second auxiliary connection 30 is electrically connected between the second scan line segment Gate12 and the second end 23.

When the third light-transmitting conductive layer 20 is located on a side of the second metal layer 19 facing away from the substrate base plate 6, the first scan line Gate1 is far away from the Gate11 of the driving transistor 10, and the first scan line Gate1 needs at least a connection via penetrating through the first passivation layer 21 and the second interlayer insulating layer 18 to be electrically connected to the Gate11 of the driving transistor 10, and due to the fact that the depth of the via is large, a metal material deposited in the via may be discontinuous, which causes the first scan line Gate1 to be disconnected from the Gate11 of the driving transistor 10. In the embodiment of the present invention, the auxiliary connection portion is disposed in the second metal layer 19, and the auxiliary connection portion can be used as an auxiliary connection layer between the first scan line Gate1 and the Gate electrode 11 of the driving transistor 10, and the first scan line Gate1 only needs to be electrically connected to the auxiliary connection portion through the connection via penetrating through the first passivation layer 21, and then the auxiliary connection portion is electrically connected to the Gate electrode 11 of the driving transistor 10 through the connection via penetrating through the second interlayer insulating layer 18, so that the connection reliability between the first scan line Gate1 and the Gate electrode 11 of the driving transistor 10 is effectively improved.

Further, as shown in fig. 11, fig. 11 is a schematic size diagram of the via holes in the first passivation layer and the second interlayer insulating layer 18 according to the embodiment of the present invention, where the second interlayer insulating layer 18 includes a fifteenth via hole 31 and a sixteenth via hole 32, and the first passivation layer 21 includes a seventeenth via hole 33 and an eighteenth via hole 34. The first scan line Gate11 is electrically connected to the first auxiliary connecting portion 29 through the seventeenth via hole 33, the first auxiliary connecting portion 29 is further electrically connected to the first end 22 through the fifteenth via hole 31, the second scan line Gate12 is electrically connected to the second auxiliary connecting portion 30 through the eighteenth via hole 34, and the second auxiliary connecting portion 30 is further electrically connected to the second end 23 through the sixteenth via hole 32.

In the direction perpendicular to the plane of the substrate base plate 6, the first auxiliary connecting part 29 covers the fifteenth via hole 31, the distance between the projected edge of the first auxiliary connecting part 29 and the projected edge of the fifteenth via hole 31 is H1, and H1 is more than or equal to 0.5 μm and less than or equal to 2.0 μm; in the direction perpendicular to the plane of the substrate base plate 6, the second auxiliary connecting part 30 covers the sixteenth via hole 32, the distance between the edge of the projection of the second auxiliary connecting part 30 and the edge of the projection of the sixteenth via hole 32 is H2, and H2 is greater than or equal to 0.5 mu m and less than or equal to 2.0 mu m; in the direction perpendicular to the plane of the substrate base plate 6, the seventeenth via hole 33 is covered by the first auxiliary connecting part 29, and the distance between the projected edge of the first auxiliary connecting part 29 and the projected edge of the seventeenth via hole 33 is P1, wherein P1 is more than or equal to 0.5 μm and less than or equal to 1.5 μm; in the direction perpendicular to the plane of the substrate base plate 6, the second auxiliary connecting part 30 covers the eighteenth via hole 34, and the distance between the projected edge of the second auxiliary connecting part 30 and the projected edge of the eighteenth via hole 34 is P2, and P2 is greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

At this time, the first auxiliary connection portion 29 extends out of the fifteenth via hole 31 in the second interlayer insulating layer 18, and the second auxiliary connection portion 30 extends out of the sixteenth via hole 32 in the second interlayer insulating layer 18, so that even if the position of the auxiliary connection portion is shifted due to a misalignment error, the auxiliary connection portion can be ensured to overlap with the first scan line Gate1, thereby improving the connection reliability between the first scan line Gate1 and the auxiliary connection portion, and at the same time, the first auxiliary connection portion 29 extends out of the seventeenth via hole 33 in the first passivation layer 21, the second auxiliary connection portion 30 extends out of the eighteenth via hole 34 in the first passivation layer 21, and the connection reliability between the auxiliary connection portion and the Gate11 of the driving transistor 10 is higher.

In one embodiment, referring again to fig. 11, the first passivation layer 21 has a film thickness D in a plane perpendicular to the substrate base plate 6,

setting the minimum value of D to

The first passivation layer 21 can be prevented from being too thin, and when the third light-transmitting conductive layer 20 is subjected to the wet etching process, the first passivation layer 21 can effectively protect the metal in the second metal layer 19 from being etched away, and further the maximum value of D is set to be

It is possible to prevent the first passivation layer 21 from being excessively thick, thereby preventing an influence on the overall thickness of the panel.

The second setting mode is as follows:

as shown in fig. 12 and 13, fig. 12 is a schematic diagram of another arrangement position of the first Data line Data1 and the first scan line Gate1 according to the embodiment of the present invention, fig. 13 is a schematic diagram of another arrangement position of the first Data line Data1 and the first scan line Gate1 according to the embodiment of the present invention, in a direction perpendicular to the plane of the substrate base plate 6, the third transparent conductive layer 20 is disposed adjacent to the first metal layer 17, a projection of the first scan line Gate1 overlaps a projection of the Gate11 of the driving transistor 10, and the first Data line Data1 is electrically insulated from the Gate11 of the driving transistor 10.

That is to say, in this arrangement, no insulating layer is disposed between the third light-transmitting conductive layer 20 and the first metal layer 17, and the first scan line Gate1 and the Gate11 of the driving transistor 10 are electrically connected in a direct contact manner, so that compared with the connection through a via hole, on one hand, the contact area between the two can be increased, the connection is more stable, and on the other hand, the risk of disconnection caused by discontinuity of the metal material deposited in the via hole can be avoided. In addition, the structure only needs to add the third light-transmitting conductive layer 20 in the panel, and does not need to add an additional insulating layer, thereby being more beneficial to the light and thin design of the panel.

Further, referring to fig. 13 again, the first scan line Gate1 is adjacent to the lower surface of the Gate electrode 11 of the driving transistor 10 facing the substrate base plate 6.

Compared with the first scan line Gate1 located at the upper side of the Gate11 of the driving transistor 10 and the first scan line Gate1 located at the lower side of the Gate11 of the driving transistor 10, on one hand, the gap between the first Data line Data1 and the first scan line Gate1 and the liquid crystal molecules can be increased to a greater extent, so as to reduce the influence of the voltage jump on the first Data line Data1 and the first scan line Gate1 on the picture displayed by the first display area 1 to a greater extent; on the other hand, when the first scan line Gate1 is located under the Gate11 of the driving transistor 10, the third transparent conductive layer 20 is formed first and then the first metal layer 17 is formed in the process of the display panel, so as to avoid the etching of the metal in the first metal layer 17 by the wet etching process of the third transparent conductive layer 20.

It should be noted that, the etching of the metal usually adopts a dry etching process, and the dry etching process has little influence on the light-transmitting conductive material such as indium tin oxide, so that the dry etching process of the first metal layer 17 does not etch the underlying third light-transmitting conductive layer 20.

Based on the above-mentioned structures shown in fig. 12 and fig. 13, in an embodiment, as shown in fig. 14 and fig. 15, fig. 14 is a schematic diagram of a connection between the first Data line Data1 and the first scan line Gate1 corresponding to fig. 12, fig. 15 is a schematic diagram of a connection between the first Data line Data1 and the first scan line Gate1 corresponding to fig. 13, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, a projection of the first scan line segment Gate11 overlaps a projection of the first end 22 in a direction perpendicular to the plane of the substrate 6, and a projection of the second scan line segment Gate12 overlaps a projection of the second end 23; the first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third terminal 24 and a fourth terminal 25, the second interlayer insulating layer 18 includes a fourth via 35 and a fifth via 36, the third terminal 24 is electrically connected to the first Data line segment Data11 through the fourth via 35, the fourth terminal 25 is electrically connected to the second Data line segment Data12 through the fifth via 36, the first interlayer insulating layer 16 further includes a sixth via 37, and the first Data line segment Data11 is electrically connected to the active layer 15 of the driving transistor 10 through the sixth via 37.

Alternatively, in another embodiment, as shown in fig. 16 and 17, fig. 16 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 12, fig. 17 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 13, the first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first pole 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, the second interlayer insulating layer 18 includes a seventh via 38 and an eighth via 39, the third end 24 is electrically connected to the first Data line segment Data11 through the seventh via 38, the fourth end 25 is connected to the second Data line segment Data12 through the eighth via 39, the first interlayer insulating layer 16 further includes a ninth via 40, and the first Data line segment Data11 is electrically connected to the active layer 15 of the driving transistor 10 through the ninth via 40.

In the above structure, the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first Data line segment Data11 and the second Data line segment Data12, and since the first electrode 12 of the driving transistor 10 is disposed in a different layer from the first scan line Gate1, even if the first scan line Gate1 is designed such that the continuous trace overlaps the first electrode 12 of the driving transistor 10, no signal interference is caused. Moreover, when the first scan line Gate1 runs continuously, the first scan line Gate1 has a large overlapping area with the Gate electrode 11 of the driving transistor 10, so that even if the arrangement position of the first scan line Gate1 or the Gate electrode 11 of the driving transistor 10 deviates due to process error factors, the first scan line Gate1 can still be ensured to be in contact with the Gate electrode 11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the Gate electrode 11 of the driving transistor 10 is high.

The third setting mode is as follows:

as shown in fig. 18 and 19, fig. 18 is a schematic diagram of another arrangement position of the first Data line Data1 and the first scan line Gate1 according to the embodiment of the present invention, fig. 19 is a schematic diagram of another arrangement position of the first Data line Data1 and the first scan line Gate1 according to the embodiment of the present invention, in a direction perpendicular to the plane of the substrate 6, the third transparent conductive layer 20 is disposed adjacent to the second metal layer 19, and in a direction perpendicular to the plane of the substrate 6, a projection of the first Data line Data1 overlaps a projection of the first pole 12 of the driving transistor 10, the first Data line 1 is electrically insulated from the second pole 13 of the driving transistor 10, and the first scan line Gate1 is electrically insulated from the first pole 12 and the second pole 13 of the driving transistor 10, respectively.

That is to say, in this arrangement, no insulating layer is disposed between the third light-transmitting conductive layer 20 and the second metal layer 19, and the first Data line Data1 and the first electrode 12 of the driving transistor 10 are electrically connected in a direct contact manner, so that compared with the connection through a via hole, on one hand, the contact area between the first Data line Data1 and the first electrode 12 of the driving transistor 10 can be increased, the connection is more stable, and on the other hand, the risk of disconnection caused by discontinuity of the metal material deposited in the via hole can be avoided. In addition, the structure only needs to add the third light-transmitting conductive layer 20 in the panel, and does not need to add an additional insulating layer, thereby being more beneficial to the light and thin design of the panel.

Further, referring to fig. 19 again, the first Data line Data1 is adjacent to the lower surface of the first electrode 12 of the driving transistor 10 facing the substrate base plate 6 side.

On one hand, compared with the first Data line Data1 located on the upper side of the driving transistor 10 and the first Data line Data1 located on the lower side of the first electrode 12 of the driving transistor 10, the distance between the first Data line Data1 and the first scanning line Gate1 and the liquid crystal molecules can be increased to a greater extent, so that the influence of voltage jump on the first Data line Data1 and the first scanning line Gate1 on the picture displayed in the first display area 1 is reduced to a greater extent; on the other hand, when the first Data line Data1 is located under the first electrode 12 of the driving transistor 10, in the process of manufacturing the display panel, the third light-transmitting conductive layer 20 is formed first, and then the second metal layer 19 is formed, so that the metal in the second metal layer 19 can be prevented from being etched away by the wet etching process of the third light-transmitting conductive layer 20. In addition, although the third light-transmitting conductive layer 20 is located on a side of the first metal layer 17 away from the substrate base plate 6, since the second interlayer insulating layer 18 is further disposed between the third light-transmitting conductive layer 20 and the first metal layer 17, the metal in the first metal layer 17 is not etched by the wet etching process of the third light-transmitting conductive layer 20.

In addition, it should be noted that, the etching of the metal usually adopts a dry etching process, and the dry etching process has little influence on the light-transmitting conductive material such as indium tin oxide, so that the dry etching process of the second metal layer 19 does not etch away the underlying third light-transmitting conductive layer 20.

Based on the above-mentioned structures shown in fig. 18 and 19, in one embodiment, as shown in fig. 20 and 21, fig. 20 is a schematic connection diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 18, fig. 21 is a schematic connection diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 19, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, the second interlayer insulating layer 18 includes a tenth via 41 and an eleventh via 42, the first scan line segment Gate11 is electrically connected to the first end 22 through the tenth via 41, and the second scan line segment Gate12 is electrically connected to the second end 23 through the eleventh via 42; the first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, a projection of the third end 24 overlaps a projection of the first Data line segment Data11, a projection of the fourth end 25 overlaps a projection of the second Data line segment Data12, and the third end 24 is electrically connected to the active layer 15 of the driving transistor 10.

In the above structure, the first Data line Data1 and the first scan line Gate1 both adopt a broken line design at the overlapping position, the first pole 12 of the driving transistor 10 is used as a metal bridge between the first Data line segment Data11 and the second Data line segment Data12, and the Gate11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, so that the effective electrical connection between the first Data line segment Data11 and the second Data line segment Data12, and between the first scan line segment Gate11 and the second scan line segment Gate12 are ensured, and an additional bridge structure is not required to be provided, thereby simplifying the process. In addition, compared with the light-transmitting conductive material such as indium tin oxide, the load of the metal material is smaller, so the design can reduce the overall load of the first Data line Data1 and the first scan line Gate1 by using the metal bridge, and further reduce the attenuation of the Data signal and the scan signal in the transmission process.

Alternatively, in another embodiment, as shown in fig. 22 and 23, fig. 22 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 18, fig. 23 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 19, a projection of the first scan line Gate1 overlaps a projection of the Gate11 of the driving transistor 10 in a direction perpendicular to the plane of the substrate 6, the second interlayer insulating layer 18 includes a twelfth via 43, and the first scan line Gate1 is electrically connected to the Gate11 of the driving transistor 10 through the twelfth via 43; the first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, a projection of the third end 24 overlaps a projection of the first Data line segment Data11, a projection of the fourth end 25 overlaps a projection of the second Data line segment Data12, and the third end 24 is electrically connected to the active layer 15 of the driving transistor 10.

In the above structure, the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first Data line segment Data11 and the second Data line segment Data12, and since the first electrode 12 of the driving transistor 10 is disposed at a different layer from the first scan line Gate1, even if the first scan line Gate1 is designed such that the continuous trace overlaps the first electrode 12 of the driving transistor 10, no signal interference is caused. Moreover, when the first scan line Gate1 runs continuously, the first scan line Gate1 has a large overlapping area with the Gate electrode 11 of the driving transistor 10, so that even if the arrangement position of the first scan line Gate1 or the Gate electrode 11 of the driving transistor 10 deviates due to process error factors, the first scan line Gate1 can still be ensured to be in contact with the Gate electrode 11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the Gate electrode 11 of the driving transistor 10 is high.

Still alternatively, as shown in fig. 24 and 25, fig. 24 is a further connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 18, fig. 25 is a further connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 19, the first scan line Gate1 includes a first scan line Gate11 and a second scan line Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, the second interlayer insulating layer 18 includes a thirteenth via hole 44 and a fourteenth via hole 45, the first scan line Gate11 is electrically connected to the first end 22 through the thirteenth via hole 44, and the second scan line Gate12 is electrically connected to the second end 23 through the fourteenth via hole 45. In a direction perpendicular to the plane of the base substrate 6, a projection of the first Data line Data1 overlaps a projection of the first pole 12 of the driving transistor 10, and the first pole 12 of the driving transistor 10 is also electrically connected to the active layer 15 of the driving transistor 10.

In the above structure, the Gate11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, and since the Gate11 of the driving transistor 10 is disposed in a different layer from the first Data line Data1, even if the first Data line Data1 is designed such that the continuous trace overlaps the Gate11 of the driving transistor 10, signal interference is not caused. Moreover, when the first Data line Data1 is routed continuously, the first Data line Data1 has a large overlapping area with the first pole 12 of the driving transistor 10, even if the arrangement position of the first Data line Data1 or the first pole 12 of the driving transistor 10 is deviated due to process error factors, the first Data line Data1 can still be ensured to be in contact with the first pole 12 of the driving transistor 10, and the connection reliability of the first Data line Data1 and the first pole 12 of the driving transistor 10 is high.

It should be noted that in other alternative embodiments of the present invention, a passivation layer may also be disposed between the third light-transmitting conductive layer 20 and the first metal layer 17 or the second metal layer 19. For example, as shown in fig. 26, fig. 26 is a schematic structural diagram of a fourth passivation layer 81 provided in the embodiment of the present invention, and when the third light-transmissive conductive layer 20 is located between the planarization layer 7 and the second interlayer insulating layer 18, a fourth passivation layer 81 may further be spaced between the third light-transmissive conductive layer 20 and the second metal layer 19. With this configuration, when the third light-transmitting conductive layer 20 is located on a side of the second metal layer 19 opposite to the substrate base plate 6, the fourth passivation layer 81 can be used to protect the second metal layer 19 from the wet etching process of the third light-transmitting conductive layer 20. Alternatively, as shown in fig. 27, fig. 27 is a schematic structural diagram of a fifth passivation layer 82 according to an embodiment of the present invention, when the third light-transmitting conductive layer 20 is located between the first interlayer insulating layer 16 and the second interlayer insulating layer 18, a fifth passivation layer 82 may further be spaced between the third light-transmitting conductive layer 20 and the first metal layer 17, so that when the third light-transmitting conductive layer 20 is located on a side of the first metal layer 17 opposite to the substrate 6, the fifth passivation layer 82 may be used to protect the first metal layer 17 from being affected by the wet etching process of the third light-transmitting conductive layer 20.

In one implementation, as shown in fig. 28, fig. 28 is a schematic view of another arrangement position of the first Data line Data1 and the first scan line Gate1 according to an embodiment of the present invention, the display panel further includes a fourth transparent conductive layer 46 and a fifth transparent conductive layer 47 arranged in different layers, the first Data line Data1 is located on the fourth transparent conductive layer 46, and the first scan line Gate1 is located on the fifth transparent conductive layer 47.

When the first scan line Gate1 and the first Data line Data1 are arranged in different layers, the arrangement positions of the first scan line Gate1 and the first Data line Data1 are more flexible. For example, referring to fig. 28 again, the fifth light-transmitting conductive layer 47 may be disposed adjacent to the first metal layer 17, so as to facilitate electrical connection between the first scan line Gate1 and the Gate electrode 11 of the driving transistor 10, and the fourth light-transmitting conductive layer 46 may be disposed adjacent to the second metal layer 19, so as to facilitate electrical connection between the first Data line Data1 and the first electrode 12 of the driving transistor 10.

In one embodiment, referring again to fig. 28, in the direction perpendicular to the plane of the substrate 6, the fourth light-transmitting conductive layer 46 is disposed adjacent to the second metal layer 19, and the projection of the first Data line Data1 overlaps the projection of the first electrode 12 of the driving transistor 10; the fifth light-transmitting conductive layer 47 is disposed adjacent to the first metal layer 17 in a direction perpendicular to the plane of the base substrate 6, and a projection of the first scan line Gate1 overlaps a projection of the Gate electrode 11 of the drive transistor 10.

For example, the fourth transparent conductive layer 46 is disposed adjacent to the second metal layer 19, no insulating layer is disposed between the fourth transparent conductive layer 46 and the second metal layer 19, and the first Data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 in a direct contact manner. Moreover, the structure can also reduce the number of the insulating layers arranged in the panel, and is more beneficial to the light and thin design of the panel.

Further, as shown in fig. 29, fig. 29 is a schematic connection diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 28, and in a direction perpendicular to the plane of the substrate 6, a projection of the first Data line Data1 overlaps a projection of the first scan line Gate1, at this time, the first Data line Data1 and the first scan line Gate1 are in a continuous routing structure, and a metal bridge does not need to be provided, so that the process is simpler.

Alternatively, as shown in fig. 30, fig. 30 is another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 28, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the Gate11 of the driving transistor 10 includes a first end 22 and a second end 23, a projection of the first scan line segment Gate11 overlaps a projection of the first end 22, and a projection of the second scan line segment Gate12 overlaps a projection of the second end 23 in a direction perpendicular to the plane of the substrate 6; in the direction perpendicular to the plane of the base substrate 6, the projection of the first Data line Data1 overlaps the projection of the gate electrode 11 of the drive transistor 10.

At this time, the first Data line Data1 is continuously routed, and there is a large overlapping area between the first Data line Data1 and the first pole 12 of the driving transistor 10, so even if the arrangement position of the first Data line Data1 or the first pole 12 of the driving transistor 10 is deviated due to process error factors, the first Data line Data1 can still be ensured to be in contact with the first pole 12 of the driving transistor 10, and the connection reliability between the first Data line Data1 and the first pole 12 of the driving transistor 10 is high.

Still alternatively, as shown in fig. 31, fig. 31 is still another connection schematic diagram of the first Data line Data1 and the first scan line Gate1 corresponding to fig. 28, and in a direction perpendicular to the plane of the substrate 6, the projection of the first scan line Gate1 overlaps the projection of the first pole 12 of the driving transistor 10; the first Data line Data1 includes a first Data line segment Data11 and a second Data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, and in the direction perpendicular to the plane of the substrate base plate 6, the projection of the third end 24 overlaps the projection of the first Data line segment Data11, and the projection of the fourth end 25 overlaps the projection of the second Data line segment Data 12.

At this time, the first scan line Gate1 is continuously routed, and there is a large overlapping area between the first scan line Gate1 and the Gate11 of the driving transistor 10, so that even if the arrangement position of the first scan line Gate1 or the Gate11 of the driving transistor 10 is deviated due to process error factors, the first scan line Gate1 can still be ensured to be in contact with the Gate11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the Gate11 of the driving transistor 10 is high.

In one embodiment, to avoid the excessive load of the first scan line Gate1 and the large loss of the scan signal, as shown in fig. 32, fig. 32 is a schematic size diagram of the first scan line Gate1 and the first Data line Data1 provided in the embodiment of the present invention, a film thickness of the first scan line Gate1 in a plane perpendicular to the substrate 6 is X1, a line width of the first scan line Gate1 in a direction perpendicular to an extending direction thereof is Z1, and X1 and Z1 may satisfy:

z1 is more than or equal to 2.5 mu m and less than or equal to 9 mu m. In order to avoid the excessive load of the first Data line Data1 and the large loss of the Data signal, the film thickness of the first Data line Data1 in the plane perpendicular to the substrate 6 is X2, the line width of the first Data line Data1 in the direction perpendicular to the extending direction is Z2, and X2 and Z2 can satisfy the following conditions:

2.5μm≤Z2≤9μm。

in one embodiment, as shown in fig. 33, fig. 33 is a schematic size diagram of the driving transistor 10 according to an embodiment of the present invention, the active layer 15 of the driving transistor 10 has a U-shaped structure, and the active layer 15 of the driving transistor 10 includes a first semiconductor portion 48, a second semiconductor portion 49, and a third semiconductor portion 50, which are sequentially connected.

In a direction perpendicular to the plane of the base substrate 6, a projection of the gate11 of the drive transistor 10 overlaps with a projection of the first semiconductor portion 48 and the third semiconductor portion 50, respectively, the gate11 of the drive transistor 10 includes a first side 51 and a second side 52 opposite in an extending direction thereof, and a minimum distance between the first side 51 and the first semiconductor portion 48 is larger than a minimum distance between the first side 51 and the third semiconductor portion 50. The distance between the projected edge of the first side 51 and the projected edge of the first semiconductor portion 48 is Q1, the distance between the projected edge of the second side 52 and the projected edge of the third semiconductor portion 50 is Q2, 5 μm is equal to or less than Q1 is equal to or less than 15 μm, and 5 μm is equal to or less than Q2 is equal to or less than 15 μm, so that the Gate11 of the driving transistor 10 has a sufficient length, the Gate11 of the driving transistor 10 is ensured to penetrate through the entire active layer 15 of the driving transistor 10, and is electrically connected to the first scan line segment Gate11 and the second scan line segment Gate 12.

In one implementation, as shown in fig. 34, fig. 34 is another schematic size diagram of the driving transistor 10 according to an embodiment of the present invention, the active layer 15 of the driving transistor 10 includes a connection island 53, the connection island 53 is electrically connected to the first electrode 12 of the driving transistor 10, the first electrode 12 of the driving transistor 10 covers the connection island 53 in a direction perpendicular to the plane of the substrate 6, and a distance between an edge of the projection of the first electrode 12 of the driving transistor 10 and an edge of the projection of the connection island 53 is Y, and Y is greater than or equal to 0 and less than or equal to 1 μm. At this time, the first electrode 12 of the driving transistor 10 is extended beyond the connection island 53 of the active layer 15, and reliable electrical connection between the first electrode 12 of the driving transistor 10 and the active layer 15 of the driving transistor 10 is facilitated through the via.

In an implementation manner, as shown in fig. 35 and fig. 36, fig. 35 is another schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 36 is a schematic structural diagram of a light-shielding portion according to an embodiment of the present invention, the display panel further includes a color filter substrate 54 disposed opposite to the array substrate, the color filter substrate 54 includes a light-shielding layer 55, the light-shielding layer 55 includes a plurality of light-shielding portions 56 located in the first display region 1, in a direction perpendicular to a plane of the substrate 6, a projection of the light-shielding portion 56 overlaps a projection of the driving transistor 10 in the first sub-pixel region 3, and at least a part of an edge of the light-shielding portion 56 is a non-linear edge.

When the display panel performs the image pickup mode, the external environment light is incident through the opening area of the light shielding layer 55, and if the light shielding layer 55 extends in a regular straight line, the external environment light is incident through the gap of the light shielding layer 55, and then periodic interference is likely to occur, and further diffraction fringes are generated. By setting at least part of the edge of the light shielding part 56 to be a nonlinear edge, the irregular edge of the light shielding part 56 can be used for breaking the periodic interference of light, weakening the diffraction phenomenon and further reducing the influence of diffraction fringes on the imaging quality.

Further, referring again to fig. 36, the light shielding portion 56 includes at least one sub-light shielding portion 57, and the shape of the sub-light shielding portion 57 is circular or elliptical. For example, the light shielding portion 56 may include two circular sub-light shielding portions 57, thereby achieving effective coverage of the driving transistors 10 of different layout shapes.

In addition, as shown in fig. 37, fig. 37 is a schematic size diagram of the light shielding portion provided by the embodiment of the present invention, in the direction perpendicular to the plane of the substrate 6, the light shielding portion 56 covers the gate11 of the driving transistor 10, and the distance between the projected edge of the light shielding portion 56 and the projected edge of the gate11 of the driving transistor 10 is E1, 0 ≦ E1 ≦ 2.0 μm; in the direction vertical to the plane of the substrate base plate 6, the light shielding part 56 covers the first pole 12 of the driving transistor 10, the distance between the projection edge of the light shielding part 56 and the projection edge of the first pole 12 of the driving transistor 10 is E2, and E2 is more than or equal to 0 and less than or equal to 2.0 microns; in the direction vertical to the plane of the substrate base plate 6, the light shielding part 56 covers the second pole 13 of the driving transistor 10, the distance between the projection edge of the light shielding part 56 and the projection edge of the second pole 13 of the driving transistor 10 is E3, and E3 is more than or equal to 0 and less than or equal to 2.0 mu m; in the direction perpendicular to the plane of the substrate base plate 6, the light shielding portion 56 covers the active layer 15 of the driving transistor 10, and the distance between the projected edge of the light shielding portion 56 and the projected edge of the active layer 15 of the driving transistor 10 is E4, and E4 is more than or equal to 0 and less than or equal to 2.0 microns.

At this time, the light shielding portion 56 completely covers the metal in the driving transistor 10, and the external ambient light is absorbed by the light shielding portion 56 covering the driving transistor 10 after entering the first display region 1, so that the external ambient light cannot be reflected to the human eye by the metal in the driving transistor 10, and a better contrast ratio can be ensured. In addition, the light shielding portion 56 also covers the active layer 15 of the driving transistor 10, so that the external ambient light or stray light cannot be irradiated to the active layer 15, thereby preventing the driving transistor 10 from generating leakage current and improving the working stability of the driving transistor 10.

In one embodiment, as shown in fig. 38, fig. 38 is a schematic view illustrating a location of a touch layer provided in the embodiment of the present invention, the display panel further includes a touch layer 58 and a third passivation layer 60, wherein the touch layer 58 includes a touch signal line 59, the touch layer 58 is located between the first light-transmissive conductive layer 8 and the planarization layer 7, and the touch layer 58 is made of a light-transmissive conductive material; the third passivation layer 60 is located between the touch layer 58 and the first light-transmissive conductive layer 8.

Since the touch layer 58 and the third passivation layer 60 are disposed on the side of the planarization layer 7 opposite to the substrate 6, the distances between the first Data line Data1 and the first scan line Gate1 and the liquid crystal molecules can be further increased by using the touch layer 58 and the third passivation layer 60, so that the influence of voltage jumps on the first Data line Data1 and the first scan line Gate1 on the liquid crystal molecules can be further reduced. In addition, the touch layer 58 is also made of a transparent conductive material, so that the shielding of the touch layer 58 on the first Data line Data1 and the first scan line Gate1 can be reduced, and the light transmittance of the first display area 1 can be improved.

Or, in another embodiment, when the first Data line Data1 and the first scan line Gate1 are located on the third transparent metal layer, as shown in fig. 39, fig. 39 is another schematic diagram of a location where the touch layer is disposed according to an embodiment of the present invention, the display panel further includes a touch layer 58, the touch layer 58 includes a touch signal line 59, the touch signal line 59 extends in the same direction as the first Data line Data1, the touch signal line 59 includes a first touch line segment 61, a second touch line segment 62 and a bridge 63, the bridge 63 is electrically connected between the first touch line segment 61 and the second touch line segment 62, and a projection of the bridge 63 overlaps a projection of the first scan line Gate1 in a direction perpendicular to the plane of the substrate 6; the first touch segment 61 and the second touch segment 62 are located on the third transparent conductive layer 20, and the bridge 63 is disposed on a different layer from the third transparent conductive layer 20, for example, the bridge 63 may be located on the first metal layer 17, the second metal layer 19, or an additional metal layer.

In the above structure, the first touch segment 61 and the second touch segment 62 only need to be formed by the same composition process as the first Data line Data1 and the first scanning line Gate1, and no extra film thickness is occupied, and the first touch segment 61 and the second touch segment 62 are electrically connected by the bridge 63, so that the first touch segment 61 and the second touch segment 62 can be prevented from contacting the first scanning line Gate1, and further mutual crosstalk between the touch signal and the scanning signal can be avoided.

Or, in another embodiment, when the first Data line Data1 is located on the fourth transparent metal layer and the first scan line Gate1 is located on the fifth transparent metal layer, as shown in fig. 40 and 41, fig. 40 is a schematic view of another setting position of the touch layer provided in the embodiment of the present invention, fig. 41 is a cross-sectional view of fig. 40 along a direction from C1 to C2, the display panel further includes a touch layer 58, the touch layer 58 includes a touch signal line 59, the touch signal line 59 extends in the same direction as the first Data line Data1, and the touch signal line 59 is located on the fourth transparent conductive layer 46.

In the above structure, the first Data line Data1 and the first scan line Gate1 are disposed in different layers, and when the touch signal line 59 is located on the fourth transparent conductive layer 46, the touch signal line 59 does not contact the first scan line Gate1, so that the touch signal line 59 can be disposed in a continuous routing structure, a bridge does not need to be disposed, and the process of the touch signal line 59 is simplified. Moreover, the touch signal line 59 does not occupy additional film space, and does not affect the overall thickness of the panel.

In addition, a light blocking layer may be further disposed on a side of the semiconductor layer 14 facing the substrate 6, where the light blocking layer is located in the first display region 1 and is used to block the active layer 15 of the driving transistor 10, so as to prevent photo-generated carriers from being generated by light emitted into the active layer 15 by a backlight, and further prevent the driving transistor 10 from generating a leakage current.

In one implementation manner, referring to fig. 3 and fig. 42, fig. 42 is a schematic structural diagram of the second display region according to the embodiment of the present invention, the display panel further includes a second display region 64 disposed adjacent to the first display region 1, the second display region 64 includes a second scan line Gate2 and a second Data line Data2, the second scan line Gate2 and the second Data line Data2 define a plurality of second sub-pixel regions 65, and each of the second sub-pixel regions 65 includes a second common electrode 66 and a second pixel electrode 67; the second scan line Gate2 is located on the first metal layer 17, the second Data line Data2 is located on the second metal layer 19, the second scan line Gate2 is electrically connected to the first scan line Gate1 through a via, and the second Data line Data2 is electrically connected to the first Data line Data1 through a via.

Based on the same inventive concept, an embodiment of the present invention further provides a manufacturing method of a display panel, the manufacturing method is used for manufacturing the display panel, and as shown in fig. 43 in conjunction with fig. 3 and fig. 4, fig. 43 is a flowchart of the manufacturing method of the display panel provided by the embodiment of the present invention, and the manufacturing method includes:

step S1: a first Data line Data1 and/or a first scan line Gate1 are formed in the first display region 1 of the base substrate 6, and the first Data line Data1 and/or the first scan line Gate1 are formed of a light-transmitting conductive material.

Step S2: the planarization layer 7 is formed on a side of the first Data line Data1 and/or the first scan line Gate1 facing away from the base substrate 6.

Step S3: a first light-transmissive electrically conductive layer 8 is formed on the side of the planarization layer 7 facing away from the base substrate 6, the first light-transmissive electrically conductive layer 8 comprising the first common electrode 4.

Step S4: a second light-transmitting conductive layer 9 is formed on a side of the first light-transmitting conductive layer 8 facing away from the substrate base plate 6, the second light-transmitting conductive layer 9 including the first pixel electrode 5.

In the embodiment of the present invention, the first Data line Data1 and/or the first scan line Gate1 are located on the side of the planarization layer 7 facing the substrate 6, the first Data line Data1 and the first scan line Gate1 are far away from the liquid crystal molecules, and even if the voltage jumps on the first Data line Data1 and the first scan line Gate1, the influence on the liquid crystal molecules is difficult to generate, so that the abnormal display problem of the first display area 1 caused by the jumps of the Data signals and the scan signals is effectively reduced, and the dark line phenomenon is weakened or even eliminated. On the other hand, the first common electrode 4 receives a fixed common voltage signal, and can also shield the influence of an interference electric field generated by voltage jumps on the first Data line Data1 and the first scan line Gate1 below the first common electrode on the liquid crystal molecules, thereby reducing the risk of abnormal display in the first display area 1 to a greater extent.

In addition, in the embodiment of the invention, the first Data line Data1 and/or the first scan line Gate1 are formed first, and then the planarization layer 7 is formed, so that the first Data line Data1 and the first scan line Gate1 do not need to be deposited on the planarization layer 7, thereby avoiding the problem that the first Data line Data1 and the first scan line Gate1 are easy to peel off due to poor adhesive force between a resin material and an indium tin oxide material.

In one embodiment, referring to fig. 3 and 4 again, the display panel further includes a driving transistor 10, a Gate11 of the driving transistor 10 is electrically connected to the first scan line Gate1, a first electrode 12 of the driving transistor 10 is electrically connected to the first Data line Data1, and a second electrode 13 of the driving transistor 10 is electrically connected to the first pixel electrode 5.

Based on this, as shown in fig. 44, fig. 44 is another flowchart of the manufacturing method of the display panel according to the embodiment of the present invention, before forming the planarization layer 7, the manufacturing method further includes:

step S01: a semiconductor layer 14 is formed on the base substrate 6, the semiconductor layer 14 being located on a side of the planarization layer 7 facing the base substrate 6, the semiconductor layer 14 including an active layer 15 of the driving transistor 10.

Step S02: a first interlayer insulating layer 16 is formed on the side of the semiconductor layer 14 facing away from the base substrate 6.

Step S03: a first metal layer 17 is formed on the side of the first interlayer insulating layer 16 facing away from the substrate base plate 6, and the first metal layer 17 includes the gate electrode 11 of the driving transistor 10.

Step S04: a second interlayer insulating layer 18 is formed on the side of the first metal layer 17 facing away from the base substrate 6.

Step S05: a second metal layer 19 is formed on the side of the second interlayer insulating layer 18 facing away from the substrate base plate 6, the second metal layer 19 including the first pole 12 and the second pole 13 of the drive transistor 10.

In one embodiment, please refer to fig. 44 again, step S1 may specifically include:

step S11: on the side of the second metal layer 19 facing away from the substrate 6, a first passivation layer 21 is formed with a first mask.

Step S12: a third light-transmitting conductive layer 20 is formed on a side of the first passivation layer 21 opposite to the substrate base plate 6, and the third light-transmitting conductive layer 20 includes a first Data line Data1 and a first scan line Gate 1.

Further, after the first light-transmitting conductive layer 8 is formed and before the second light-transmitting conductive layer 9 is formed, the manufacturing method further includes: and forming a second passivation layer by using the first mask.

When the first passivation layer 21 and the second passivation layer 80 are formed by using the same mask, as shown in fig. 45, fig. 45 is a schematic structural view of the first passivation layer 21 and the second passivation layer 80 provided in the embodiment of the present invention, where the first passivation layer 21 includes a nineteenth via 70, a twentieth via 71, and a twenty-first via 72, the first Data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 through the nineteenth via 70, and the first scan line Gate1 is electrically connected to the Gate electrode 11 of the driving transistor 10 through the twentieth via 71. The second passivation layer 80 includes twenty-second, twenty-third and twenty-

fourth vias

73, 74 and 75, and the first pixel electrode 5 is electrically connected to the second pole 13 of the driving transistor 10 through twenty-fourth and twenty-

first vias

75 and 72. In a direction perpendicular to the plane of the substrate base plate 6, a projection of the nineteenth via 70 coincides with a projection of the twenty-second via 73, a projection of the twentieth via 71 coincides with a projection of the twenty-third via 74, and a projection of the twenty-first via 72 coincides with a projection of the twenty-fourth via 75.

It should be noted that no conductive material is deposited in the twenty-second via 73 and the twenty-third via 74 in the second passivation layer 80, and is not used for electrical connection between the conductive film layers.

By adopting the manufacturing method, the first passivation layer 21 and the second passivation layer 80 are etched by using the same mask plate, so that the number of the mask plates required in the panel process is reduced, and the process cost is reduced.

Alternatively, in another embodiment, after the forming of the first light-transmitting conductive layer 8 and before the forming of the second light-transmitting conductive layer 9, the manufacturing method further includes: a second passivation layer 80 is formed using a second mask.

When the first passivation layer 21 and the second passivation layer 80 are formed by using different masks, as shown in fig. 46, fig. 46 is another schematic structural diagram of the first passivation layer 21 and the second passivation layer 80 according to an embodiment of the present invention, where the first passivation layer 21 includes a nineteenth via 70, a twentieth via 71, and a twenty-first via 72, the first Data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 through the nineteenth via 70, and the first scan line Gate1 is electrically connected to the Gate electrode 11 of the driving transistor 10 through the twentieth via 71. The second passivation layer 80 includes only the twenty-fourth via 75, and the first pixel electrode 5 is electrically connected to the second pole 13 of the driving transistor 10 through the twenty-fourth via 75, the twenty-first via 72, and the via in the planarization layer 7.

By adopting the manufacturing method, the first passivation layer 21 and the second passivation layer 80 are etched by adopting different mask plates, idle twenty-second through holes 73 and idle twenty-third through holes 74 do not need to be formed in the second passivation layer 80, the number of the through holes in the second passivation layer 80 is small, the second passivation layer 80 is easier to form a flat surface, and the film flatness of the second passivation layer 80 and the box thickness uniformity of a panel are effectively improved.

Further, as shown in fig. 47, fig. 47 is a schematic structural diagram of the first passivation layer 21 and the second passivation layer 80 according to an embodiment of the present invention, where the planarization layer 7 has a twenty-fifth via 76, a projection of the twenty-fifth via 76 covers a projection of the twenty-first via 72 in a direction perpendicular to a plane of the substrate base plate 6, an aperture of the twenty-fifth via 76 is larger than an aperture of the twenty-first via 72, and the twenty-fifth via 76 and the twenty-first via 72 form a trepan structure. At this time, for the nineteenth, twentieth, and twenty-

first vias

70, 71, and 72 of the first passivation layer 21, the aperture of the twenty-first via 72 may be set smaller than that of the nineteenth and

twentieth vias

70 and 71. Specifically, the aperture of the nineteenth via 70 is L1, the aperture of 3.0 μm or less L1 or less 5.5 μm, the aperture of the twentieth via 71 is L2, the aperture of 3.0 μm or less L2 or less 5.5 μm, the aperture of the twenty-first via 72 is L3, and the aperture of 2.5 μm or less L3 or less 4.5 μm.

After the planarization layer 7 is formed on the first passivation layer 21, since the aperture of the twenty-first via hole 72 in the first passivation layer 21 is small, in the process of forming the twenty-fifth via hole 76 on the planarization layer 7, the etched region of the planarization layer 7 corresponding to the twenty-fifth via hole 76 covers the twenty-first via hole 72 and a portion of the first passivation layer 21 around the twenty-first via hole 72, so that even if the etching process of the planarization layer 7 affects the first passivation layer 21, only the portion of the first passivation layer 21 exposed in the twenty-fifth via hole 76 is affected, the aperture of the twenty-first via hole 72 is not too large, the situation that the aperture of the twenty-first via hole 72 is larger than that of the twenty-fifth via hole 76 is avoided, and further, when the twenty-fourth via hole 75 of the second passivation layer 80 is formed subsequently, the incomplete etching condition in the twenty-first via hole 72 is avoided, thereby improving the reliability of the connection between the first pixel electrode 5 and the second electrode 13 of the driving transistor 10.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 48, fig. 48 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device includes the display panel 100. The specific structure and manufacturing method of the display panel 100 have been described in detail in the above embodiments, and are not described herein again. Of course, the display device shown in fig. 48 is only a schematic illustration, and the display device may be any electronic device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, comprising:

a first display area including a first scan line and a first data line, the first scan line and the first data line defining a plurality of first sub-pixel areas, the first sub-pixel areas including a first common electrode and a first pixel electrode, the first display area being an optical member disposition area;

a substrate base plate;

a planarization layer on the substrate base plate;

wherein the first data line is formed by a light-transmitting conductive material, the first data line is positioned at one side of the planarization layer facing the substrate base plate, and/or the first scanning line is formed by a light-transmitting conductive material, the first scanning line is positioned at one side of the planarization layer facing the substrate base plate;

the first sub-pixel area further comprises a driving transistor, a grid electrode of the driving transistor is electrically connected with the first scanning line, a first pole of the driving transistor is electrically connected with the first data line, and a second pole of the driving transistor is electrically connected with the first pixel electrode of the first sub-pixel area;

the display panel further includes:

the semiconductor layer is positioned on one side, facing the substrate, of the planarization layer, and the active layer of the driving transistor is positioned on the semiconductor layer;

the first interlayer insulating layer is positioned on one side, back to the substrate, of the semiconductor layer;

the first metal layer is positioned on one side, back to the substrate base plate, of the first interlayer insulating layer, and the grid electrode of the driving transistor is positioned on the first metal layer;

the second interlayer insulating layer is positioned on one side, back to the substrate base plate, of the first metal layer;

a second metal layer between the second interlayer insulating layer and the planarization layer, the first and second poles of the driving transistor being located at the second metal layer;

and the first data line and the first scanning line are positioned on the third light-transmitting conductive layer.

2. The display panel according to claim 1,

the display panel further comprises a first passivation layer between the second metal layer and the planarization layer;

a third light-transmissive conductive layer is located between the first passivation layer and the planarization layer.

3. The display panel according to claim 2,

the first scanning line comprises a first scanning line segment and a second scanning line segment, the grid of the driving transistor comprises a first end and a second end, the first end is electrically connected with the first scanning line segment, and the second end is electrically connected with the second scanning line segment;

the first data line comprises a first data line segment and a second data line segment, the first pole of the driving transistor comprises a third end and a fourth end, the first passivation layer comprises a first through hole and a second through hole, the first data line segment is electrically connected with the third end through the first through hole, the second data line segment is electrically connected with the fourth end through the second through hole, and the third end is further electrically connected with the active layer of the driving transistor.

4. The display panel according to claim 2,

in a direction perpendicular to a plane of the substrate base plate, a projection of the first data line overlaps a projection of the gate electrode of the driving transistor, the first passivation layer includes a third via hole, the first data line is electrically connected to the first pole of the driving transistor through the third via hole, and the first pole of the driving transistor is also electrically connected to the active layer of the driving transistor.

5. The display panel according to claim 3 or 4,

the second metal layer further comprises a first auxiliary connecting portion and a second auxiliary connecting portion, the first auxiliary connecting portion is electrically connected between the first scanning line segment and the first end, and the second auxiliary connecting portion is electrically connected between the second scanning line segment and the second end.

6. The display panel according to claim 1,

in a direction perpendicular to the plane of the substrate base plate, the third light-transmitting conductive layer is arranged adjacent to the first metal layer, the projection of the first scanning line is overlapped with the projection of the grid electrode of the driving transistor, and the first data line is electrically insulated from the grid electrode of the driving transistor.

7. The display panel according to claim 6,

the first scanning line is adjacent to the lower surface of the side, facing the substrate, of the grid electrode of the driving transistor.

8. The display panel according to claim 6,

the first scanning line comprises a first scanning line segment and a second scanning line segment, the grid of the driving transistor comprises a first end and a second end, in the direction perpendicular to the plane of the substrate, the projection of the first scanning line segment is overlapped with the projection of the first end, and the projection of the second scanning line segment is overlapped with the projection of the second end;

the first data line comprises a first data line segment and a second data line segment, the first pole of the driving transistor comprises a third end and a fourth end, the second interlayer insulating layer comprises a fourth through hole and a fifth through hole, the third end is electrically connected with the first data line segment through the fourth through hole, the fourth end is electrically connected with the second data line segment through the fifth through hole, the first interlayer insulating layer further comprises a sixth through hole, and the first data line segment is electrically connected with the active layer of the driving transistor through the sixth through hole.

9. The display panel according to claim 6,

the first data line comprises a first data line segment and a second data line segment, the first pole of the driving transistor comprises a third end and a fourth end, the second interlayer insulating layer comprises a seventh through hole and an eighth through hole, the third end is electrically connected with the first data line segment through the seventh through hole, the fourth end is connected with the second data line segment through the eighth through hole, the first interlayer insulating layer further comprises a ninth through hole, and the first data line segment is electrically connected with the active layer of the driving transistor through the ninth through hole.

10. The display panel according to claim 1,

in a direction perpendicular to the plane of the substrate base plate, the third light-transmitting conductive layer is arranged adjacent to the second metal layer, and in the direction perpendicular to the plane of the substrate base plate, a projection of the first data line overlaps a projection of the first pole of the driving transistor, the first data line is electrically insulated from the second pole of the driving transistor, and the first scanning line is electrically insulated from the first pole and the second pole of the driving transistor respectively.

11. The display panel according to claim 10,

the first data line is adjacent to the lower surface of the first pole of the driving transistor facing to one side of the substrate base plate.

12. The display panel according to claim 10,

the first scanning line comprises a first scanning line segment and a second scanning line segment, the grid of the driving transistor comprises a first end and a second end, the second interlayer insulating layer comprises a tenth through hole and an eleventh through hole, the first scanning line segment is electrically connected with the first end through the tenth through hole, and the second scanning line segment is electrically connected with the second end through the eleventh through hole;

the first data line comprises a first data line segment and a second data line segment, the first pole of the driving transistor comprises a third end and a fourth end, in the direction perpendicular to the plane of the substrate base plate, the projection of the third end is overlapped with the projection of the first data line segment, the projection of the fourth end is overlapped with the projection of the second data line segment, and the third end is further electrically connected with the active layer of the driving transistor.

13. The display panel according to claim 10,

in a direction perpendicular to the plane of the substrate base plate, the projection of the first scanning line overlaps the projection of the gate of the driving transistor, the second interlayer insulating layer comprises a twelfth through hole, and the first scanning line is electrically connected with the gate of the driving transistor through the twelfth through hole;

14. The display panel according to claim 10,

the first scanning line comprises a first scanning line segment and a second scanning line segment, the grid of the driving transistor comprises a first end and a second end, the second interlayer insulating layer comprises a thirteenth through hole and a fourteenth through hole, the first scanning line segment is electrically connected with the first end through the thirteenth through hole, and the second scanning line segment is electrically connected with the second end through the fourteenth through hole;

in a direction perpendicular to the plane of the substrate base plate, the projection of the first data line overlaps the projection of the first pole of the driving transistor, and the first pole of the driving transistor is electrically connected with the active layer of the driving transistor.

15. The display panel according to claim 1, characterized in that the display panel further comprises:

the color film substrate is arranged opposite to the substrate and comprises a light shielding layer, the light shielding layer comprises a plurality of light shielding parts located in the first display area, in the direction perpendicular to the plane of the substrate, the projections of the light shielding parts are overlapped with the projections of the driving transistors in the first sub-pixel area, and at least part of the edges of the light shielding parts are nonlinear edges.

16. The display panel according to claim 15,

the shading part comprises at least one sub-shading part, and the shape of the sub-shading part is circular or elliptical.

17. The display panel according to claim 1, characterized in that the display panel further comprises:

the touch layer comprises a touch signal line, is positioned between the first light-transmitting conductive layer and the planarization layer and is made of a light-transmitting conductive material;

a third passivation layer located between the touch layer and the first light-transmissive conductive layer.

18. The display panel according to claim 1, characterized in that the display panel further comprises:

the touch control layer comprises a touch control signal line, the touch control signal line and the first data line extend in the same direction, the touch control signal line comprises a first touch control line segment, a second touch control line segment and a bridge, the bridge is electrically connected between the first touch control line segment and the second touch control line segment, and in the plane direction perpendicular to the substrate base plate, the projection of the bridge is overlapped with the projection of the first scanning line;

the first touch line segment and the second touch line segment are located on the third light-transmitting conductive layer, and the bridge and the third light-transmitting conductive layer are arranged in a different layer.

19. The display panel according to claim 1,

the display panel further comprises a second display area arranged adjacent to the first display area, the second display area comprises a second scanning line and a second data line, the second scanning line and the second data line define a plurality of second sub-pixel areas, and the second sub-pixel areas comprise a second common electrode and a second pixel electrode;

the second scan line is located in the first metal layer, and the second data line is located in the second metal layer.

20. A method for manufacturing a display panel is characterized by comprising the following steps:

forming a first data line and/or a first scan line in a first display region of a substrate, the first data line and/or the first scan line being formed of a light-transmitting conductive material;

forming a planarization layer on one side of the first data line and/or the first scanning line, which faces away from the substrate;

forming a second light-transmitting conductive layer on one side, back to the substrate, of the first light-transmitting conductive layer, wherein the second light-transmitting conductive layer comprises a first pixel electrode;

the display panel further comprises a driving transistor, wherein a grid electrode of the driving transistor is electrically connected with the first scanning line, a first pole of the driving transistor is electrically connected with the first data line, and a second pole of the driving transistor is electrically connected with the first pixel electrode;

before forming the planarization layer, the method further comprises:

forming a semiconductor layer on the substrate base plate, wherein the semiconductor layer is positioned on one side, facing the substrate base plate, of the planarization layer and comprises an active layer of the driving transistor;

forming a first interlayer insulating layer on one side of the semiconductor layer, which faces away from the substrate;

forming a first metal layer on one side of the first interlayer insulating layer, which faces away from the substrate base plate, wherein the first metal layer comprises a grid electrode of the driving transistor;

forming a second interlayer insulating layer on one side of the first metal layer, which faces away from the substrate base plate;

forming a second metal layer on one side of the second interlayer insulating layer, which faces away from the substrate base plate, wherein the second metal layer comprises a first pole and a second pole of the driving transistor;

the process of forming the first data line and/or the first scan line on the substrate base plate includes:

forming a first passivation layer on one side of the second metal layer, which is back to the substrate base plate, by using a first mask plate;

and forming a third light-transmitting conductive layer on one side of the first passivation layer, which faces away from the substrate, wherein the third light-transmitting conductive layer comprises the first data line and the first scan line.

21. The method of manufacturing according to claim 20,

after the first light-transmitting conductive layer is formed and before the second light-transmitting conductive layer is formed, the manufacturing method further includes: and forming a second passivation layer by using the first mask plate.

22. The method of manufacturing according to claim 20,

after the first light-transmitting conductive layer is formed and before the second light-transmitting conductive layer is formed, the manufacturing method further includes: and forming a second passivation layer by using the second mask.

23. A display device comprising the display panel according to any one of claims 1 to 19.