CN115472556A - 形成互连结构的方法 - Google Patents
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- CN115472556A CN115472556A CN202210200200.6A CN202210200200A CN115472556A CN 115472556 A CN115472556 A CN 115472556A CN 202210200200 A CN202210200200 A CN 202210200200A CN 115472556 A CN115472556 A CN 115472556A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本案提供一种形成互连结构的方法,包括以下操作:在第一导电特征上沉积第一介电层,在第一介电层上沉积第一遮罩层,以及在第一遮罩层上沉积第二遮罩层。在第一遮罩层及第二遮罩层中图案化第一开口,此第一开口具有第一宽度。在第一开口的底表面中图案化第二开口,此第二开口延伸至第一介电层中,此第二开口具有第二宽度。第二宽度小于第一宽度。第一开口延伸至第一介电层中,及第二开口延伸穿过第一介电层以暴露第一导电特征的顶表面。
Description
技术领域
本揭示内容是关于一种形成互连结构的方法。
背景技术
半导体集成电路(integrated circuit;IC)行业已经经历了指数式的生长。IC材料及设计的技术进步已经生产了数代IC,其中每一代都具有比上一代更小及更复杂的电路。在IC演进的过程中,几何尺寸(例如,使用制造制程可制造的最小元件(或线路))减小的同时,功能密度(即,单位晶片面积的互连元件的数目)普遍增加。这种缩小过程普遍通过提高生产效率及降低关联成本而提供益处。
随着元件的缩小,制造商已经开始使用新的及不同的材料及/或材料组合以促进元件的缩小。缩小,单独地及结合新的及不同材料,亦导致前几代在更大几何形状上尚未遇到的挑战。
发明内容
本揭示内容提供了一种形成互连结构的方法,包含以下操作。在第一导电特征上沉积第一介电层。在第一介电层上沉积第一遮罩层,第一遮罩层包含碳化钨。在第一遮罩层上沉积第二遮罩层,第二遮罩层包含氮化钛。在第一遮罩层及第二遮罩层中图案化第一开口,第一开口具有第一宽度。在第一开口的底表面中图案化第二开口,第二开口延伸至第一介电层中,第二开口具有第二宽度,第二宽度小于第一宽度。将第一开口延伸至第一介电层中,及将第二开口延伸穿过第一介电层以暴露第一导电特征的顶表面。
本揭示内容提供了一种形成互连结构的方法,包含以下操作。在低介电常数介电层上沉积第一遮罩层,第一遮罩层为氧化硅。在第一遮罩层上沉积第二遮罩层,第二遮罩层为碳化钨。在第二遮罩层上沉积第三遮罩层,第三遮罩层为氮化钛。在第三遮罩层上沉积第四遮罩层,第四遮罩层为氧化硅。图案化第二遮罩层、第三遮罩层、及第四遮罩层以形成沟槽。通过蚀刻穿过第一遮罩层,将沟槽延伸至低介电常数介电层中。通过用导电材料填充沟槽而形成导电线。移除第一遮罩层、第二遮罩层、第三遮罩层及第四遮罩层。
本揭示内容提供了一种形成互连结构的方法,包含以下操作。在第一介电层上形成第一遮罩层,第一介电层在第一导电特征上,第一遮罩层包含碳化钨。在第一遮罩层上沉积第二遮罩层,第二遮罩层包含氮化钛。图案化第一遮罩层及第二遮罩层。在图案化第一遮罩层及第二遮罩层之后,使用第一遮罩层及第二遮罩层作为蚀刻遮罩通过用氟基蚀刻剂蚀刻第一介电层而形成延伸至第一介电层中的开口,开口曝露第一导电特征的顶表面,在第一温度下执行用氟基蚀刻剂蚀刻第一介电层,其中氟基蚀刻剂与第一遮罩层的第一副产物的沸点小于第一温度。
附图说明
当结合附图阅读时,根据以下详细描述可更好地理解本揭示案的态样。应注意,根据工业标准实务,各种特征未按比例绘制。事实上,为论述清楚,各特征的尺寸可任意地增加或缩小。
图1根据一些实施例图示一种半导体基板及集成电路的多层互连结构的横截面视图;
图2至图10根据一些实施例图示半导体元件在制造的不同中间阶段处的横截面视图;
图11根据一些实施例图示半导体元件在制造的一中间阶段处的横截面视图。
【符号说明】
60:半导体基板
62:元件
64:层间介电(ILD)层
66:触点
70:互连结构
100:半导体元件
100A:互连级
100B:互连级
100N:互连级
100N-1:互连级
101:区域
104A:导电通孔
104B:导电通孔
104N:导电通孔
104N-1:导电通孔
108A:导电线
108B:导电线
108N:导电线
108N-1:导电线
110A:金属间介电(IMD)层
110B:金属间介电(IMD)层
110N:金属间介电(IMD)层
110N-1:金属间介电(IMD)层
112:导电特征
114:介电层
202:蚀刻停止层(ESL)
202A:底部ESL
202B:中间ESL
202C:顶部ESL
204:通孔开口
206:介电层
208:沟槽
210:遮罩层
220:遮罩层
230:遮罩层
240:遮罩层
242:开口
250:光敏遮罩
250A:底层
250B:中间层
250C:顶层
260:光敏遮罩
260A:底层
260B:中间层
260C:顶层
290:导电材料
302:蚀刻停止层(ESL)
306:介电层
T1:第一厚度
T2:第二厚度
W1:第一宽度
W2:第二宽度
W3:第三宽度
W4:第四宽度
具体实施方式
以下揭示内容提供许多不同实施例或实例,以便实现本揭示内容的不同特征。下文描述部件及排列的特定例子以简化本揭示内容。当然,这些仅为例子且不意欲为限制性。举例而言,在随后描述中第一特征在第二特征上方或在第二特征上的形成可包括第一及第二特征形成为直接接触的实施例,以及亦可包括额外特征可形成在第一及第二特征之间,使得第一及第二特征可不直接接触的实施例。另外,本揭示案在各实例中可重复元件符号及/或字母。此重复为出于简单清楚的目的,且本身不指示所论述各实施例及/或配置之间的关系。
另外,空间相对用语,诸如“之下”、“下方”、“下部”、“上方”、“上部”及类似者,在此为便于描述可用于描述诸图中所图示一个元件或特征与另一(些)元件或(多个)特征的关系。除图形中描绘的取向外,空间相对术语意欲包含元件在使用或操作中的不同取向。设备可为不同取向(旋转90度或在其他的取向)及可因此同样地解释在此使用的空间相对描述词。
本揭示案包括,例如,利用双重镶嵌(dual damascene)制程形成用于图案化互连开口(包括沟槽及通孔开口)的遮罩的方法。例如,遮罩可以包括在含钨遮罩层上的含钛遮罩层。含钛遮罩层可以提供对底层介电材料的高蚀刻选择性,用于利用双重镶嵌制程在介电材料中形成互连开口。含钨遮罩层,可能由于本来具有强物理模数,而减少互连开口的扭曲。此外,在多层遮罩中包含含钨遮罩层会帮助在图案化互连开口期间减少非挥发性蚀刻副产物的量,从而减少蚀刻不足。
图1根据一些实施例图示半导体元件100的横截面视图。半导体元件100包括包含电子元件的半导体基板60,及互连电子元件以形成集成电路的在半导体基板60上的互连结构70。图1为半导体元件100的简化视图,并且为了图示清晰,省略了半导体元件100的一些特征(下文论述)。
半导体基板60可包含块半导体基板或绝缘体上硅(silicon-on-insulator;SOI)基板。SOI基板在薄半导体层(SOI基板的主动层)下方包括绝缘体层。主动层的半导体及块半导体大致包含晶体半导体材料硅,但可以包括一或多种其他半导体材料,诸如锗、硅锗合金、化合物半导体(例如,GaAs、AlAs、InAs、GaN、AlN等等)、或他们的合金(例如,GaxAl1-xAs、GaxAl1-xN、InxGa1-xAs等等)、氧化物半导体(例如,ZnO、SnO2、TiO2、Ga2O3等等)或上述组合。半导体材料可为掺杂或未掺杂的。可使用的其他基板包括多层基板、梯形基板(gradientsubstrate)、或混合取向(hybrid orientation)基板。
在半导体基板60的主动表面处形成元件62。元件62可为主动元件、被动元件、或它们的组合。例如,元件62可为晶体管、二极管、电容器、电阻器、或通过任何适当形成方法形成的类似元件。
一或多个层间介电(inter-layer dielectric;ILD)层64形成于半导体基板60上,并且电导电特征,诸如触点66(亦称为触点插塞),实体且电耦接至元件62。ILD层64可由任意适当介电材料,例如,诸如氧化硅(silicon oxide)的氧化物、磷硅酸盐玻璃(phosphosilicate glass;PSG)、硅酸硼玻璃(borosilicate glass;BSG)、硼掺杂磷硅酸盐玻璃(boron-doped phosphosilicate glass;BPSG)等;诸如氮化硅(silicon nitride)的氮化物;或类似者形成。ILD层64可通过任何适当沉积制程,诸如旋涂、物理气相沉积(physical vapor deposition;PVD)、化学气相沉积(chemical vapor deposition;CVD)、类似者、或它们的组合形成。触点66可通过任何适当制程,诸如沉积、镶嵌(例如,单一镶嵌、双重镶嵌等)、类似者或它们的组合形成。
互连结构70包括多个互连级100A-100N,其垂直堆叠于触点66及ILD层64上。互连结构70根据针对集成电路设计所采用之后段制程(back end of line;BEOL)方案而形成。在图1中图示的BEOL方案中,不同互连级100A-100N具有类似特征。其他实施例可利用交替整合方案,其中不同互连级100A-100N使用不同特征。例如,触点66,其被图示为垂直连接件,可被扩展以形成横向传输电流的导电线。如随后将描述的,互连结构70的互连级100A-100N通过双重镶嵌制程而形成。
互连结构70的互连级100A-100N均包含嵌入金属间介电(intermetaldielectric;IMD)层中的导电通孔及/或导电线。大致上,通孔垂直传导电流并用于垂直连接位于垂直相邻级处的两个导电特征,而线横向传导电流并用于将电信号及电力分布在一个互连级内。在底部互连级100A中,导电通孔104A将触点66连接至导电线108A,并且在后续互连级100B-100N处,通孔将通孔下方一级上的线连接至通孔上方的线(例如,一对导电线108A与108B通过导电通孔104B连接在一起)。在一些实施例中,不同互连级的结构(例如,底部互连级100A与后续互连级100B-100N)可为类似的。在图1中图示的实例中,互连级100A-100N均包括导电通孔104A-104N及导电线108A-108N,此些导电通孔及导电线嵌入具有平坦顶表面的IMD层110A-110N中。其他实施例可以采用不同的方案。例如,导电通孔104A可从底部互连级100A忽略,并且触点66可直接连接至导电线108A。
图2至图10根据一些实施例图示半导体元件在制造的不同中间阶段处的横截面视图。具体地,图示了互连结构的互连级的形成。图2至图10为图1的区域101的细节横截面视图,示出形成互连结构70的中间互连级100N-1的制程。然而,可以使用此制程形成互连结构的任意互连级。例如,此类制程亦可用于形成互连结构的底部互连级100A(参见图1)及/或顶部互连级100N(参见图1)。
图2图示蚀刻停止层(etch stop layer;ESL)202及介电层206的形成。ESL 202及介电层206在介电层114及导电特征112上形成。介电层114可为底层互连级的IMD(例如,图1中的IMD层110B)或可为底层ILD(例如,图1中的ILD层64)。导电特征112可为底层互连级的导电线(例如,图1中的导电线108B)或可为底层ILD中的电导电特征(例如,图1中的触点66)。
在一些实施例中,ESL 202用于控制后续蚀刻制程以形成通孔开口(参见下文,图8)。ESL 202可为任意可接受的ESL,诸如单层ESL、双层ESL、三层ESL,或类似者。在一些实施例中,ESL 202为三层ESL,其包含底部ESL 202A、底部ESL 202A上的中间ESL 202B、及中间ESL 202B上的顶部ESL 202C。ESL 202A包含一种绝缘材料,诸如AlOx、AlN、AlYOx、ZrOx、YOx、上述组合,或类似者,此ESL的蚀刻速率不同于底层介电层114及后续形成的上层材料的蚀刻速率。ESL 202A可使用PECVD(plasma enhance chemical vapor deposition)、ALD(atomic layer deposition)、CVD、或类似者形成。ESL 202B包含一种绝缘材料,诸如SiO、SiOC、SiCN、SiON、SiN、或类似者。ESL 202C可由如上文针对ESL 202A所述的类似材料及类似方法形成。ESL 202C的蚀刻速率可不同于底层ESL 202B及后续形成的上层材料的蚀刻速率。
介电层206在ESL 202上形成。介电层206用于围绕互连级100N-1的导电通孔及导电线形成金属间介电(IMD)块(参见下文,图10)。在一些实施例中,介电层206由多孔或致密低介电常数(低k)介电质形成,诸如碳氧化硅(SiOCH)、氟硅酸盐玻璃(FSG)、碳掺杂氧化物(carbon-doped oxide;CDO)、可流动氧化物、多孔氧化物(例如,干凝胶/气凝胶)、磷硅酸盐玻璃(PSG)、硅酸硼玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、无掺杂硅酸盐玻璃(undopedsilicate glass;USG)、类似者、或上述组合。介电层206亦可称为低介电常数介电层。介电层206的介电材料可使用任何适当方法,诸如CVD、PECVD、FCVD、旋涂、类似者、或上述组合沉积。
在图3中,遮罩层210、220、230、及240在介电层206上形成。遮罩层210、220、230、及240用于控制后续蚀刻制程以分别形成用于导电通孔及导电线的开口及沟槽(参见下文,图7至图8)。
在一些实施例中,遮罩层210由诸如氧化硅的介电材料形成,其例如使用正硅酸乙酯(tetraethylorthosilicate;TEOS)作为前驱物形成。遮罩层210的介电材料相对于遮罩层220及230的蚀刻具有高蚀刻选择性(下文描述)。在一些实施例中,遮罩层210的介电材料为不含金属的介电材料。遮罩层210的材料的形成方法可包括化学气相沉积(CVD)、电浆增强化学气相沉积(PECVD)、低大气化学气相沉积(sub atmosphere chemical vapordeposition;SACVD)、或类似者。
接下来,遮罩层220在遮罩层210上形成。遮罩层220由诸如碳化钨(tungstencarbide)的含钨遮罩材料形成,其具有用于后续沟槽图案化的强物理模数(参见下文,图5至图8)。在一些实施例中,含钨遮罩材料的杨氏模数在500MPa至2000MPa的范围中。由于含钨遮罩材料具有强物理模数,因此可降低后续图案化沟槽的线宽粗糙度(line widthroughness;LWR)。另外,沟槽图案化制程期间蚀刻含钨遮罩材料产生的副产物可能易挥发(例如,气相替代固相),使得副产物可从图案化沟槽轻易地去除,从而可减少蚀刻不足(参见下文,图7至图8)。遮罩层220的材料可使用PECVD、原子层沉积(ALD)、CVD、物理气相沉积(PVD)、或类似沉积形成。遮罩层220所形成的第一厚度T1在至的范围中,其可能有利于为线图案化提供强物理模数并降低后续在介电层206中形成的沟槽的LWR。将遮罩层220的厚度形成为小于可能导致后续形成的导电线的增大的LWR。
接下来,遮罩层230在遮罩层220上形成。遮罩层230由诸如氮化钛(titaniumnitride)的含钛遮罩材料形成,其相对于遮罩层210及介电层206的蚀刻具有高蚀刻选择性。在一些实施例中,相较于遮罩层220的含钨遮罩材料,遮罩层230的含钛遮罩材料相对于遮罩层210及介电层206具有更大的蚀刻选择性。因而,可以改进用于后续在介电层206(参见下文,图5至图8)中形成通孔开口及沟槽的覆盖窗口。遮罩层230的材料可使用PECVD、原子层沉积(ALD)、CVD、物理气相沉积(PVD)、或类似沉积形成。遮罩层230可形成的第二厚度T2在至的范围中,其可有利于提高用于后续蚀刻制程的蚀刻选择性。将遮罩层230的厚度形成为小于可能导致用于后续蚀刻制程的更弱蚀刻选择性。
接下来,遮罩层240在遮罩层230上形成。在一些实施例中,遮罩层220由诸如氧化硅的介电材料形成,其相对于遮罩层220及230的蚀刻具有高蚀刻选择性。遮罩层240可由如上文针对遮罩层220所述的类似材料及类似方法形成。
在图4中,光敏遮罩250在遮罩层240上形成。光敏遮罩250可为任意可接受的光阻剂,诸如单层光阻剂、二层光阻剂、三层光阻剂,或类似者。在图示实施例中,光敏遮罩250为三层光阻剂,包括底层250A、中间层250B、及顶层250C。在一些实施例中,底层250A由非晶碳形成,中间层250B由含硅光阻剂或膜形成,以及顶层250C由光敏材料形成。顶层250C经图案化为具有开口,此开口的第一宽度W1在5nm至40nm的范围中,其适用于后续在介电层206中图案化用于导电线(参见下文,图8至图9)的沟槽。
在图5中,光敏遮罩250用作蚀刻遮罩以蚀刻及图案化遮罩层240、230、及220,因而形成具有开口242的遮罩,其将在后续蚀刻制程中使用以在介电层206中形成用于导电线的沟槽。开口242经形成为穿过遮罩层240、230、及220。在一些实施例中,开口242延伸至(但不穿过)遮罩层210。光敏遮罩250的一或多层可在蚀刻制程中消耗,或可在蚀刻制程之后移除。在一些实施例中,通过灰化制程,之后进行湿式清洗制程而移除光敏遮罩250。在蚀刻制程及移除光敏遮罩250之后,图案化遮罩层240的剩余部分可具有减小的厚度。或者,图案化遮罩层240的厚度可通过蚀刻制程而大致上不变。
蚀刻可为任意可接受的蚀刻制程,诸如反应离子蚀刻(reactive ion etch;RIE)、中性束蚀刻(neutral beam etch;NBE)等,或上述组合。在一些实施例中,蚀刻制程为通过电浆制程执行的各向异性干式蚀刻。电浆蚀刻制程在处理腔室中执行,其中制程气体被供应进处理腔室中。在一些实施例中,电浆为直接电浆。在一些实施例中,电浆为在连接至处理腔室的单独电浆生成腔室中生成的远端电浆。制程气体可通过生成电浆的任何适当方法而激化成电浆,诸如变压器耦合电浆(transformer coupled plasma;TCP)系统、电感耦合电浆(inductively coupled plasma;ICP)系统、电容耦合电浆(capacitively coupledplasma;CCP)系统、磁性增强反应离子技术、电子回旋共振技术、或类似者。
电浆蚀刻制程中使用的制程气体包括一或多种蚀刻剂气体。在一些实施例中,蚀刻剂气体为氯基蚀刻剂气体,诸如Cl2、BCl3、类似者、或它们的组合。亦可使用额外制程气体,诸如氧气及/或氢气。载气,诸如N2、Ar、He、或类似者,可用于将制程气体传送进处理腔室中。制程气体可以范围为100sccm至1000sccm的速率流入处理腔室中。
电浆蚀刻制程可使用范围在50伏特至500伏特的偏压执行。电浆蚀刻制程可使用范围在0瓦特至500瓦特的电浆生成功率执行。电浆蚀刻制程可在范围在20℃至60℃的温度下执行。处理腔室中的压力可在20mTorr至80mTorr的范围中。电浆蚀刻制程的执行时间可在50秒至200秒的范围中。利用上述范围外的蚀刻参数(例如,偏压、持续时间等)执行电浆蚀刻制程可导致遮罩层210的不期望的蚀刻不足或过度蚀刻。
在图6中,光敏遮罩260形成于遮罩层240上并填充开口242。光敏遮罩260可为任意可接受的光阻剂,诸如单层光阻剂、二层光阻剂、三层光阻剂,或类似者。在图示实施例中,光敏遮罩260为三层光阻剂,包括底层260A、中间层260B、及顶层260C。在一些实施例中,光敏遮罩260由如上文针对光敏遮罩250所述的类似材料及类似方法而形成(参见上文,图4)。顶层260C经图案化为具有开口,此开口的第二宽度W2在5nm至30nm的范围中,其适用于后续在介电层206中图案化用于导电通孔(参见下文,图8至图9)的开口。第二宽度W2小于光敏遮罩250中开口的第一宽度W1(参见上文,图4)。
在图7中,执行图案化制程以将光敏遮罩260的图案传递至遮罩层210及介电层206。图案化制程形成穿过遮罩层210并延伸至介电层206中的通孔开口204。在一些实施例中,图案化制程可包含一或多种蚀刻制程,其中光敏遮罩260用作蚀刻遮罩。一或多个蚀刻制程可包括适当各向异性的干式蚀刻制程,诸如反应离子蚀刻(RIE)制程等。在一些实施例中,蚀刻制程为通过电浆制程(诸如上文关于图5描述的电浆蚀刻制程)执行的各项异性干式蚀刻。在另一实施例中,用于蚀刻制程的蚀刻剂混合物可包含氟基蚀刻剂(fluorine-based etchant),诸如CxFy(例如,CF4、C4F8、等等)、NF3、类似者、或它们的组合,此蚀刻制程类似于下文关于图8描述的电浆蚀刻制程。在一些实施例中,遮罩层210及介电层206中的通孔开口204可具有与光敏遮罩260中的开口大约相同的宽度W2(参见上文,图6)。定时蚀刻制程可用以蚀刻介电层206,直到通孔开口204部分地延伸至介电层206达一期望距离为止。在遮罩层210及介电层206中形成通孔开口204之后,光敏遮罩260(参见上文,图6)可用适当制程移除,诸如灰化制程,之后进行湿式清洗制程。
在图8中,执行图案化制程以将遮罩层220、230、及240中开口的图案传递至介电层206,从而在遮罩层210及介电层206中形成沟槽208,并将通孔开口204延伸穿过介电层206。在它们延伸穿过介电层206之后,通孔开口204从沟槽208的底部延伸至ESL 202。通孔开口204及沟槽208将随后被填充以分别形成导电通孔及导电线(参见下文,图9至图10)。如后续将更详细描述地,图案化制程可包括一或多个蚀刻制程,其中遮罩层220、230、及240(参见上文,图7)用作蚀刻遮罩,并且遮罩层210未被遮罩层220、230、及240覆盖的部分通过一或多个蚀刻制程移除,以便沟槽208延伸至介电层206中并且通孔开口204延伸穿过介电层206。蚀刻剂可经选择以对遮罩层210及240与介电层206的材料具有选择性,对遮罩层220及230进行很少蚀刻或不蚀刻。在一些实施例中,通过一或多个蚀刻制程移除遮罩层240。例如,当遮罩层210及240由相同材料(例如,氧化硅)形成时,遮罩层240可通过用于在遮罩层210及介电层206中形成沟槽208的蚀刻制程而移除。通孔开口204随后可通过可接受的蚀刻技术而延伸穿过ESL 202,暴露导电特征112的顶表面。在一些实施例中,沟槽208的第三宽度W3在5nm至40nm的范围中,以及通孔开口204的第四宽度W4在5nm至30nm的范围中。
在一些实施例中,用于介电层206的图案化制程可包含一或多种蚀刻制程,其中遮罩层220、230、及240用作蚀刻遮罩。蚀刻可为任意可接受的蚀刻制程,诸如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等,或上述组合。在一些实施例中,蚀刻制程为通过电浆制程执行的各向异性干式蚀刻。电浆蚀刻制程在处理腔室中执行,其中制程气体被供应进处理腔室中。在一些实施例中,电浆为直接电浆。在一些实施例中,电浆为在连接至处理腔室的单独电浆生成腔室中生成的远端电浆。制程气体可通过生成电浆的任何适当方法而激化成电浆,诸如变压器耦合电浆(transformer coupled plasma;TCP)系统、电感耦合电浆(inductively coupled plasma;ICP)系统、电容耦合电浆(capacitively coupledplasma;CCP)系统、磁性增强反应离子技术、电子回旋共振技术、或类似者。
电浆蚀刻制程中使用的制程气体包括一或多种蚀刻剂气体。在一些实施例中,蚀刻剂气体为氟基蚀刻剂气体,诸如CxFy(例如,CF4、C4F8、等等)、NF3、类似者、或它们的组合。亦可使用额外制程气体,诸如氧气、氢气、及/或CxOy气体。载气,诸如N2、Ar、He、或类似者,可用于将制程气体传送进处理腔室中。制程气体可以范围为100sccm至1000sccm的速率流入处理腔室中。
电浆蚀刻制程可使用范围在30伏特至1000伏特的偏压执行。电浆蚀刻制程可使用范围在30瓦特至1000瓦特的电浆生成功率执行。电浆蚀刻制程可在范围在20℃至60℃的温度下执行。处理腔室中的压力可在3mTorr至80mTorr的范围中。电浆蚀刻制程的执行时间可在30秒至200秒的范围中。利用上述范围外的蚀刻参数(例如,偏压、持续时间等)执行电浆蚀刻制程可导致介电层206的不期望的蚀刻不足或过度蚀刻。
如上文所述,遮罩层220由含钨遮罩材料形成,及遮罩层230由含钛遮罩材料形成。在氟基蚀刻剂气体用于将光敏遮罩260的图案传递至遮罩层210及介电层206的一些实施例中,蚀刻剂气体可与含钛遮罩材料反应以形成诸如TiF4的含钛副产物,以及蚀刻剂气体可与含钨遮罩材料反应以形成诸如WF6的含钨副产物。例如,当遮罩层220由碳化钨(WC)形成及蚀刻剂气体包括氧气及三氟化氮(NF3)时,诸如六氟化钨(WF6)、一氧化碳(CO)、及氟化碳(CxFy)的副产物可根据WC+O2+NF3→WF6+CO+CxFy而形成。开口242及204的侧壁及底表面上的剩余副产物可导致后续形成的用于导电线及导电通孔的沟槽及开口的蚀刻不足,从而可导致接触电阻的增大及元件效能的退化。因为TiF4的沸点为约284℃,所以难以从开口242及204的侧壁或底表面移除TiF4。有利地,WF6的沸点为约17℃,所以其可能通过例如在室温(例如,约25℃)下升华或蒸发而轻易地从开口242及204的侧壁或底表面而移除。在一些实施例中,在高于WF6的沸点且低于TiF4的沸点的温度下,诸如在约25℃的约室温下,执行电浆蚀刻制程。
相较于使用没有遮罩层220的较厚遮罩层230,结合遮罩层230使用遮罩层220允许减少含钛副产物。此外,相较于没有遮罩层230使用较厚遮罩层220,结合遮罩层220使用遮罩层230保留含钛遮罩材料的优点,诸如相对于遮罩层210及遮罩层206的蚀刻具有提高的蚀刻选择性。
在图9中,在结构上形成导电材料290以填充(或超填)通孔开口204及沟槽208(参见上文,图8)。在一些实施例中,导电材料290包括内衬通孔开口204及沟槽208的侧壁及底表面的导电扩散阻障衬垫,及在导电扩散阻障衬垫上的导电填充材料。导电扩散阻障衬垫可减少导电材料外扩散进介电层206中。导电扩散阻障线可包括TaN、Ta、TiN、Ti、Co、类似者、或上述组合的一或多层。导电扩散阻障衬垫可通过任何适当方法而沉积,诸如CVD、PECVD、PVD、ALD、PEALD、电镀(electrochemical plating;ECP)、无电镀等等。导电填充材料可包含金属,诸如W、Cu、Co、Ru、CuMn、Mo、Al、或类似者、或它们的组合、或它们的多层。导电填充材料可通过任何适当方法而沉积,例如CVD、PECVD、PVD、ALD、PEALD、电镀(ECP)、无电镀等等。在一些实施例中,薄导电晶种层可沉积在导电扩散阻障衬垫上以帮助引发ECP制程,其中导电填充材料填充开口。在一些实施例中,导电晶种层可为与导电填充材料相同的导电材料,并且可使用适当沉积方法(例如,CVD、PECVD、ALD、PEALD、或PVD等)沉积。
在图10中,执行移除制程以移除导电材料290的过量部分,其过量部分在介电层206的顶表面上。移除制程亦移除遮罩层210、220、及230(参见上文,图9)在介电层206上的剩余部分。在移除制程之后,导电材料290具有部分保持在通孔开口204中(因而形成导电通孔104N-1)并具有部分保持在沟槽208中(因而形成导电线108N-1)。介电层206的剩余部分为设置在导电通孔104N-1及导电线108N-1周围的IMD层110N-1。移除制程可为诸如CMP或类似者的平面化制程。在平面化制程之后,导电线108N-1及IMD层110N-1的顶表面为共面的(在制程变化内)。移除制程完成互连级100N-1的制造,其包括嵌入IMD层110N-1中的导电通孔104N-1及导电线108N-1。
在图2至图10描述的制程之后,可形成额外互连级。图11图示形成于中间互连级100N-1上的互连级100N。互连级100N包括IMD层110N和蚀刻停止层(ESL)302,IMD层110N包括导电通孔104N及导电线108N。IMD层110N由例如介电层306形成。互连级100N可由上文针对互连级100N-1所述的类似材料及类似方法形成(参见上文,图2至图10)。
实施例可实现优势。在含钨遮罩层上形成包括含钛遮罩层的多层遮罩,以利用双重镶嵌制程图案化互连开口(包括沟槽及通孔开口)。含钛遮罩层与用于图案化互连开口的底层介电材料可具有改善的蚀刻选择性。含钨遮罩层可具有强物理模数,其可降低后续形成的导电线的线宽粗糙度(LWR)。此外,在多层遮罩中包含含钨遮罩层帮助在图案化互连开口期间减少非挥发性蚀刻副产物的量,从而减少蚀刻不足。
根据一实施例,一种形成互连结构的方法包括以下操作:在第一导电特征上沉积第一介电层;在第一介电层上沉积第一遮罩层,第一遮罩层包括碳化钨;在第一遮罩层上沉积第二遮罩层,第二遮罩层包括氮化钛;在第一遮罩层及第二遮罩层中图案化第一开口,第一开口具有第一宽度;在第一开口的底表面中图案化第二开口,第二开口延伸至第一介电层中,第二开口具有第二宽度,第二宽度小于第一宽度;以及第一开口延伸至第一介电层中,及第二开口延伸穿过第一介电层以暴露第一导电特征的顶表面。在一实施例中,第一遮罩层的第一厚度在至的范围中。在一实施例中,第二遮罩层的第二厚度在至的范围中。在一实施例中,方法进一步包括以下操作,用导电材料填充第一开口及第二开口。在一实施例中,填充第一开口会在第一开口中形成导电线,导电线的第三宽度在5nm至40nm的范围中。在一实施例中,填充第二开口会在第二开口中形成导电通孔,导电通孔的第四宽度在5nm至30nm的范围中。在一实施例中,方法进一步包括在第二遮罩层上形成第三遮罩层的操作。在一实施例中,第三遮罩层包括氧化硅。
根据另一实施例,一种形成互连结构的方法包括以下操作:在低介电常数介电层上沉积第一遮罩层,第一遮罩层为氧化硅;在第一遮罩层上沉积第二遮罩层,第二遮罩层为碳化钨;在第二遮罩层上沉积第三遮罩层,第三遮罩层为氮化钛;在第三遮罩层上沉积第四遮罩层,第四遮罩层为氧化硅;图案化第二遮罩层、第三遮罩层、及第四遮罩层以形成沟槽;通过蚀刻穿过第一遮罩层,将沟槽延伸至低介电常数介电层中;通过用导电材料填充沟槽而形成导电线;以及移除第一遮罩层、第二遮罩层、第三遮罩层,以及第四遮罩层。在一实施例中,蚀刻穿过第一遮罩层的操作包括用氟基蚀刻剂蚀刻第一遮罩层。在一实施例中,第二遮罩层的杨氏模数在500MPa至2000MPa的范围中。在一实施例中,当蚀刻穿过第一遮罩层时执行第四遮罩层的移除。在一实施例中,形成导电线的操作包括平面化导电材料,并且其中通过平面化导电材料移除第一遮罩层、第二遮罩层、及第三遮罩层。
根据另一实施例,一种形成互连结构的方法包括以下操作:在第一介电层上形成第一遮罩层,第一介电层在第一导电特征上,此第一遮罩层包括碳化钨;在第一遮罩层上沉积第二遮罩层,第二遮罩层包括氮化钛;图案化第一遮罩层及第二遮罩层;在图案化第一遮罩层及第二遮罩层之后,使用第一遮罩层及第二遮罩层作为蚀刻遮罩通过氟基蚀刻剂蚀刻第一介电层而形成延伸至第一介电层中的开口,此开口暴露第一导电特征的顶表面,在第一温度下执行利用氟基蚀刻剂蚀刻第一介电层,其中氟基蚀刻剂与第一遮罩层的第一副产物的沸点小于第一温度。在一实施例中,氟基蚀刻剂与第二遮罩层的第二副产物的沸点大于第一温度。在一实施例中,第二副产物为TiF4。在一实施例中,第一副产物为WF6。在一实施例中,利用电浆蚀刻制程执行第一介电层的蚀刻,并且氟基蚀刻剂为CF4。在一实施例中,在范围在20℃至60℃的温度下执行电浆蚀刻制程。在一实施例中,第一温度为室温。
前面概述了几个实施例的特征,以便熟悉本领域者可以更好地理解本揭示的各个态样。熟悉本领域者应当理解,他们可以容易地使用本揭示作为设计或修改其他制程及结构的基础,以实现本文介绍的实施例的相同目的和/或实现其相同优点。熟悉本领域者还应认识到,此类等效构造不脱离本揭示的精神及范畴,并且它们可以在不脱离本揭示的精神及范畴的情况下对本文进行各种改变、替换及变更。
Claims (10)
1.一种形成互连结构的方法,其特征在于,包括:
在一第一导电特征上沉积一第一介电层;
在该第一介电层上沉积一第一遮罩层,该第一遮罩层包含碳化钨;
在该第一遮罩层上沉积一第二遮罩层,该第二遮罩层包含氮化钛;
在该第一遮罩层及该第二遮罩层中图案化一第一开口,该第一开口具有一第一宽度;
在该第一开口的一底表面中图案化一第二开口,该第二开口延伸至该第一介电层中,该第二开口具有一第二宽度,该第二宽度小于该第一宽度;以及
将该第一开口延伸至该第一介电层中,及将该第二开口延伸穿过该第一介电层以暴露该第一导电特征的一顶表面。
4.根据权利要求1所述的方法,其特征在于,进一步包括用一导电材料填充该第一开口及该第二开口。
5.一种形成互连结构的方法,其特征在于,包括:
在一低介电常数介电层上沉积一第一遮罩层,该第一遮罩层为氧化硅;
在该第一遮罩层上沉积一第二遮罩层,该第二遮罩层为碳化钨;
在该第二遮罩层上沉积一第三遮罩层,该第三遮罩层为氮化钛;
在该第三遮罩层上沉积一第四遮罩层,该第四遮罩层为氧化硅;
图案化该第二遮罩层、该第三遮罩层、及该第四遮罩层以形成一沟槽;
通过蚀刻穿过该第一遮罩层,将该沟槽延伸至该低介电常数介电层中;
通过用一导电材料填充该沟槽而形成一导电线;以及
移除该第一遮罩层、该第二遮罩层、该第三遮罩层及该第四遮罩层。
6.根据权利要求5所述的方法,其特征在于,蚀刻穿过该第一遮罩层包括用一氟基蚀刻剂蚀刻该第一遮罩层。
7.根据权利要求5所述的方法,其特征在于,该第二遮罩层的一杨氏模数在500MPa至2000MPa的一范围中。
8.一种形成互连结构的方法,其特征在于,包括:
在一第一介电层上形成一第一遮罩层,该第一介电层在一第一导电特征上,该第一遮罩层包含碳化钨;
在该第一遮罩层上沉积一第二遮罩层,该第二遮罩层包含氮化钛;
图案化该第一遮罩层及该第二遮罩层;以及
在图案化该第一遮罩层及该第二遮罩层之后,使用该第一遮罩层及该第二遮罩层作为一蚀刻遮罩通过用一氟基蚀刻剂蚀刻该第一介电层而形成延伸至该第一介电层中的一开口,该开口曝露该第一导电特征的一顶表面,在一第一温度下执行用该氟基蚀刻剂蚀刻该第一介电层,其中该氟基蚀刻剂与该第一遮罩层的一第一副产物的一沸点小于该第一温度。
9.根据权利要求8所述的方法,其特征在于,该氟基蚀刻剂与该第二遮罩层的一第二副产物的一沸点大于该第一温度。
10.根据权利要求8所述的方法,其特征在于,该第一温度为室温。
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