TW202308036A - 形成互連結構的方法 - Google Patents
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- TW202308036A TW202308036A TW110145391A TW110145391A TW202308036A TW 202308036 A TW202308036 A TW 202308036A TW 110145391 A TW110145391 A TW 110145391A TW 110145391 A TW110145391 A TW 110145391A TW 202308036 A TW202308036 A TW 202308036A
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本案提供一種方法,包括以下操作:在第一導電特徵上沉積第一介電層,在第一介電層上沉積第一遮罩層,以及在第一遮罩層上沉積第二遮罩層。在第一遮罩層及第二遮罩層中圖案化第一開口,此第一開口具有第一寬度。在第一開口之底表面中圖案化第二開口,此第二開口延伸至第一介電層中,此第二開口具有第二寬度。第二寬度小於第一寬度。第一開口延伸至第一介電層中,及第二開口延伸穿過第一介電層以暴露第一導電特徵之頂表面。
Description
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半導體積體電路(integrated circuit;IC)行業已經經歷了指數式的生長。IC材料及設計的技術進步已經生產了數代IC,其中每一代都具有比上一代更小及更複雜的電路。在IC演進的過程中,幾何尺寸(例如,使用製造製程可製造的最小元件(或線路))減小的同時,功能密度(即,單位晶片面積的互連元件的數目)普遍增加。這種縮小過程普遍藉由提高生產效率及降低關聯成本而提供益處。
隨著元件之縮小,製造商已經開始使用新的及不同的材料及/或材料組合以促進元件的縮小。縮小,單獨地及結合新的及不同材料,亦導致前幾代在更大幾何形狀上尚未遇到的挑戰。
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以下揭示內容提供許多不同實施例或實例,以便實現本揭示內容的不同特徵。下文描述部件及排列的特定例子以簡化本揭示內容。當然,這些僅為例子且不意欲為限制性。舉例而言,在隨後描述中第一特徵在第二特徵上方或在第二特徵上的形成可包括第一及第二特徵形成為直接接觸的實施例,以及亦可包括額外特徵可形成在第一及第二特徵之間,使得第一及第二特徵可不直接接觸的實施例。另外,本揭示案在各實例中可重複元件符號及/或字母。此重複為出於簡單清楚之目的,且本身不指示所論述各實施例及/或配置之間之關係。
另外,空間相對用語,諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者,在此為便於描述可用於描述諸圖中所圖示一個元件或特徵與另一(些)元件或(多個)特徵之關係。除圖形中描繪的取向外,空間相對術語意欲包含元件在使用或操作中的不同取向。設備可為不同取向(旋轉90度或在其他的取向)及可因此同樣地解釋在此使用的空間相對描述詞。
本揭示案包括,例如,利用雙重鑲嵌(dual damascene)製程形成用於圖案化互連開口(包括溝槽及通孔開口)之遮罩的方法。例如,遮罩可以包括在含鎢遮罩層上之含鈦遮罩層。含鈦遮罩層可以提供對底層介電材料之高蝕刻選擇性,用於利用雙重鑲嵌製程在介電材料中形成互連開口。含鎢遮罩層,可能由於本來具有強物理模數,而減少互連開口之扭曲。此外,在多層遮罩中包含含鎢遮罩層會幫助在圖案化互連開口期間減少非揮發性蝕刻副產物的量,從而減少蝕刻不足。
第1圖根據一些實施例圖示半導體元件100的橫截面視圖。半導體元件100包括包含電子元件之半導體基板60,及互連電子元件以形成積體電路的在半導體基板60上之互連結構70。第1圖為半導體元件100之簡化視圖,並且為了圖示清晰,省略了半導體元件100之一些特徵(下文論述)。
半導體基板60可包含塊半導體基板或絕緣體上矽(silicon-on-insulator;SOI)基板。SOI基板在薄半導體層(SOI基板之主動層)下方包括絕緣體層。主動層之半導體及塊半導體大致包含晶體半導體材料矽,但可以包括一或多種其他半導體材料,諸如鍺、矽鍺合金、化合物半導體(例如,GaAs、AlAs、InAs、GaN、AlN等等)、或他們的合金(例如,Ga
xAl
1-xAs、Ga
xAl
1-xN、In
xGa
1-xAs等等)、氧化物半導體(例如,ZnO、SnO
2、TiO
2、Ga
2O
3等等)或上述組合。半導體材料可為摻雜或未摻雜的。可使用的其他基板包括多層基板、梯形基板(gradient substrate)、或混合取向(hybrid orientation)基板。
在半導體基板60之主動表面處形成元件62。元件62可為主動元件、被動元件、或它們的組合。例如,元件62可為電晶體、二極體、電容器、電阻器、或藉由任何適當形成方法形成的類似元件。
一或多個層間介電(inter-layer dielectric; ILD)層64形成於半導體基板60上,並且電導電特徵,諸如觸點66(亦稱為觸點插塞),實體且電耦接至元件62。ILD層64可由任意適當介電材料,例如,諸如氧化矽(silicon oxide)之氧化物、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、矽酸硼玻璃(borosilicate glass;BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG)等;諸如氮化矽(silicon nitride)之氮化物;或類似者形成。ILD層64可藉由任何適當沉積製程,諸如旋塗、物理氣相沉積(physical vapor deposition;PVD)、化學氣相沉積(chemical vapor deposition;CVD)、類似者、或它們的組合形成。觸點66可藉由任何適當製程,諸如沉積、鑲嵌(例如,單一鑲嵌、雙重鑲嵌等)、類似者或它們的組合形成。
互連結構70包括多個互連級100A-100N,其垂直堆疊於觸點66及ILD層64上。互連結構70根據針對積體電路設計所採用之後段製程(back end of line;BEOL)方案而形成。在第1圖中圖示之BEOL方案中,不同互連級100A-100N具有類似特徵。其他實施例可利用交替整合方案,其中不同互連級100A-100N使用不同特徵。例如,觸點66,其被圖示為垂直連接件,可被擴展以形成橫向傳輸電流之導電線。如隨後將描述的,互連結構70之互連級100A-100N藉由雙重鑲嵌製程而形成。
互連結構70之互連級100A-100N均包含嵌入金屬間介電(intermetal dielectric;IMD)層中之導電通孔及/或導電線。大致上,通孔垂直傳導電流並用於垂直連接位於垂直相鄰級處的兩個導電特徵,而線橫向傳導電流並用於將電信號及電力分佈在一個互連級內。在底部互連級100A中,導電通孔104A將觸點66連接至導電線108A,並且在後續互連級100B-100N處,通孔將通孔下方一級上的線連接至通孔上方的線(例如,一對導電線108A與108B藉由導電通孔104B連接在一起)。在一些實施例中,不同互連級之結構(例如,底部互連級100A與後續互連級100B-100N)可為類似的。在第1圖中圖示之實例中,互連級100A-100N均包括導電通孔104A-104N及導電線108A-108N,此些導電通孔及導電線嵌入具有平坦頂表面之IMD層110A-110N中。其他實施例可以採用不同的方案。例如,導電通孔104A可從底部互連級100A忽略,並且觸點66可直接連接至導電線108A。
第2圖至第10圖根據一些實施例圖示半導體元件在製造之不同中間階段處的橫截面視圖。具體地,圖示了互連結構之互連級的形成。第2圖至第10圖為第1圖之區域101的細節橫截面視圖,示出形成互連結構70之中間互連級100N-1的製程。然而,可以使用此製程形成互連結構之任意互連級。例如,此類製程亦可用於形成互連結構之底部互連級100A (參見第1圖)及/或頂部互連級100N (參見第1圖)。
第2圖圖示蝕刻停止層(etch stop layer;ESL)202及介電層206之形成。ESL 202及介電層206在介電層114及導電特徵112上形成。介電層114可為底層互連級之IMD (例如,第1圖中之IMD層110B)或可為底層ILD (例如,第1圖中之ILD層64)。導電特徵112可為底層互連級之導電線(例如,第1圖中之導電線108B)或可為底層ILD中之電導電特徵(例如,第1圖中之觸點66)。
在一些實施例中,ESL 202用於控制後續蝕刻製程以形成通孔開口(參見下文,第8圖)。ESL 202可為任意可接受之ESL,諸如單層ESL、雙層ESL、三層ESL,或類似者。在一些實施例中,ESL 202為三層ESL,其包含底部ESL 202A、底部ESL 202A上之中間ESL 202B、及中間ESL 202B上之頂部ESL 202C。ESL 202A包含一種絕緣材料,諸如AlO
x、AlN、AlYO
x、ZrO
x、YO
x、上述組合,或類似者,此ESL之蝕刻速率不同於底層介電層114及後續形成之上層材料的蝕刻速率。ESL 202A可使用PECVD (plasma enhance chemical vapor deposition)、ALD (atomic layer deposition)、CVD、或類似者形成。ESL 202B包含一種絕緣材料,諸如SiO、SiOC、SiCN、SiON、SiN、或類似者。ESL 202C可由如上文針對ESL 202A所述之類似材料及類似方法形成。ESL 202C之蝕刻速率可不同於底層ESL 202B及後續形成之上層材料的蝕刻速率。
介電層206在ESL 202上形成。介電層206用於圍繞互連級100N-1之導電通孔及導電線形成金屬間介電(IMD)塊(參見下文,第10圖)。在一些實施例中,介電層206由多孔或緻密低介電常數(低k)介電質形成,諸如碳氧化矽(SiOCH)、氟矽酸鹽玻璃(FSG)、碳摻雜氧化物(carbon-doped oxide;CDO)、可流動氧化物、多孔氧化物(例如,幹凝膠/氣凝膠)、磷矽酸鹽玻璃(PSG)、矽酸硼玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、無摻雜矽酸鹽玻璃(undoped silicate glass;USG)、類似者、或上述組合。介電層206亦可稱為低介電常數介電層。介電層206之介電材料可使用任何適當方法,諸如CVD、PECVD、FCVD、旋塗、類似者、或上述組合沉積。
在第3圖中,遮罩層210、220、230、及240在介電層206上形成。遮罩層210、220、230、及240用於控制後續蝕刻製程以分別形成用於導電通孔及導電線之開口及溝槽(參見下文,第7圖至第8圖)。
在一些實施例中,遮罩層210由諸如氧化矽之介電材料形成,其例如使用正矽酸乙酯(tetraethylorthosilicate;TEOS)作為前驅物形成。遮罩層210之介電材料相對於遮罩層220及230之蝕刻具有高蝕刻選擇性(下文描述)。在一些實施例中,遮罩層210之介電材料為不含金屬之介電材料。遮罩層210之材料的形成方法可包括化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、低大氣化學氣相沉積(sub atmosphere chemical vapor deposition;SACVD)、或類似者。
接下來,遮罩層220在遮罩層210上形成。遮罩層220由諸如碳化鎢(tungsten carbide)之含鎢遮罩材料形成,其具有用於後續溝槽圖案化之強物理模數(參見下文,第5圖至第8圖)。在一些實施例中,含鎢遮罩材料之楊氏模數在500 MPa至2000 MPa之範圍中。由於含鎢遮罩材料具有強物理模數,因此可降低後續圖案化溝槽之線寬粗糙度(line width roughness;LWR)。另外,溝槽圖案化製程期間蝕刻含鎢遮罩材料產生的副產物可能易揮發(例如,氣相替代固相),使得副產物可從圖案化溝槽輕易地去除,從而可減少蝕刻不足(參見下文,第7圖至第8圖)。遮罩層220之材料可使用PECVD、原子層沉積(ALD)、CVD、物理氣相沉積(PVD)、或類似沉積形成。遮罩層220所形成之第一厚度T
1在30 Å至200 Å之範圍中,其可能有利於為線圖案化提供強物理模數並降低後續在介電層206中形成之溝槽的LWR。將遮罩層220之厚度形成為小於30 Å可能導致後續形成之導電線的增大的LWR。
接下來,遮罩層230在遮罩層220上形成。遮罩層230由諸如氮化鈦(titanium nitride)之含鈦遮罩材料形成,其相對於遮罩層210及介電層206之蝕刻具有高蝕刻選擇性。在一些實施例中,相較於遮罩層220之含鎢遮罩材料,遮罩層230之含鈦遮罩材料相對於遮罩層210及介電層206具有更大的蝕刻選擇性。因而,可以改進用於後續在介電層206(參見下文,第5圖至第8圖)中形成通孔開口及溝槽的覆蓋窗口。遮罩層230之材料可使用PECVD、原子層沉積(ALD)、CVD、物理氣相沉積(PVD)、或類似沉積形成。遮罩層230可形成之第二厚度T
2在20 Å至100 Å之範圍中,其可有利於提高用於後續蝕刻製程之蝕刻選擇性。將遮罩層230之厚度形成為小於20 Å可能導致用於後續蝕刻製程之更弱蝕刻選擇性。
接下來,遮罩層240在遮罩層230上形成。在一些實施例中,遮罩層220由諸如氧化矽之介電材料形成,其相對於遮罩層220及230之蝕刻具有高蝕刻選擇性。遮罩層240可由如上文針對遮罩層220所述之類似材料及類似方法形成。
在第4圖中,光敏遮罩250在遮罩層240上形成。光敏遮罩250可為任意可接受之光阻劑,諸如單層光阻劑、二層光阻劑、三層光阻劑,或類似者。在圖示實施例中,光敏遮罩250為三層光阻劑,包括底層250A、中間層250B、及頂層250C。在一些實施例中,底層250A由非晶碳形成,中間層250B由含矽光阻劑或膜形成,以及頂層250C由光敏材料形成。頂層250C經圖案化為具有開口,此開口之第一寬度W
1在5 nm至40 nm之範圍中,其適用於後續在介電層206中圖案化用於導電線(參見下文,第8圖至第9圖)之溝槽。
在第5圖中,光敏遮罩250用作蝕刻遮罩以蝕刻及圖案化遮罩層240、230、及220,因而形成具有開口242之遮罩,其將在後續蝕刻製程中使用以在介電層206中形成用於導電線的溝槽。開口242經形成為穿過遮罩層240、230、及220。在一些實施例中,開口242延伸至(但不穿過)遮罩層210。光敏遮罩250之一或多層可在蝕刻製程中消耗,或可在蝕刻製程之後移除。在一些實施例中,藉由灰化製程,之後進行濕式清洗製程而移除光敏遮罩250。在蝕刻製程及移除光敏遮罩250之後,圖案化遮罩層240之剩餘部分可具有減小的厚度。或者,圖案化遮罩層240之厚度可藉由蝕刻製程而大致上不變。
蝕刻可為任意可接受的蝕刻製程,諸如反應離子蝕刻(reactive ion etch;RIE)、中性束蝕刻(neutral beam etch;NBE)等,或上述組合。在一些實施例中,蝕刻製程為藉由電漿製程執行之各向異性乾式蝕刻。電漿蝕刻製程在處理腔室中執行,其中製程氣體被供應進處理腔室中。在一些實施例中,電漿為直接電漿。在一些實施例中,電漿為在連接至處理腔室之單獨電漿生成腔室中生成的遠端電漿。製程氣體可藉由生成電漿之任何適當方法而激化成電漿,諸如變壓器耦合電漿(transformer coupled plasma;TCP)系統、電感耦合電漿(inductively coupled plasma;ICP)系統、電容耦合電漿(capacitively coupled plasma;CCP)系統、磁性增強反應離子技術、電子迴旋共振技術、或類似者。
電漿蝕刻製程中使用的製程氣體包括一或多種蝕刻劑氣體。在一些實施例中,蝕刻劑氣體為氯基蝕刻劑氣體,諸如Cl
2、BCl
3、類似者、或它們的組合。亦可使用額外製程氣體,諸如氧氣及/或氫氣。載氣,諸如N
2、Ar、He、或類似者,可用於將製程氣體傳送進處理腔室中。製程氣體可以範圍為100 sccm至1000 sccm之速率流入處理腔室中。
電漿蝕刻製程可使用範圍在50伏特至500伏特之偏壓執行。電漿蝕刻製程可使用範圍在0瓦特至500瓦特之電漿生成功率執行。電漿蝕刻製程可在範圍在20°C至60°C之溫度下執行。處理腔室中之壓力可在20 mTorr至80 mTorr之範圍中。電漿蝕刻製程的執行時間可在50秒至200秒之範圍中。利用上述範圍外之蝕刻參數(例如,偏壓、持續時間等)執行電漿蝕刻製程可導致遮罩層210之不期望之蝕刻不足或過度蝕刻。
在第6圖中,光敏遮罩260形成於遮罩層240上並填充開口242。光敏遮罩260可為任意可接受之光阻劑,諸如單層光阻劑、二層光阻劑、三層光阻劑,或類似者。在圖示實施例中,光敏遮罩260為三層光阻劑,包括底層260A、中間層260B、及頂層260C。在一些實施例中,光敏遮罩260由如上文針對光敏遮罩250所述之類似材料及類似方法而形成(參見上文,第4圖)。頂層260C經圖案化為具有開口,此開口之第二寬度W
2在5 nm至30 nm之範圍中,其適用於後續在介電層206中圖案化用於導電通孔(參見下文,第8圖至第9圖)之開口。第二寬度W
2小於光敏遮罩250中開口之第一寬度W
1(參見上文,第4圖)。
在第7圖中,執行圖案化製程以將光敏遮罩260之圖案傳遞至遮罩層210及介電層206。圖案化製程形成穿過遮罩層210並延伸至介電層206中的通孔開口204。在一些實施例中,圖案化製程可包含一或多種蝕刻製程,其中光敏遮罩260用作蝕刻遮罩。一或多個蝕刻製程可包括適當各向異性的乾式蝕刻製程,諸如反應離子蝕刻(RIE)製程等。在一些實施例中,蝕刻製程為藉由電漿製程(諸如上文關於第5圖描述之電漿蝕刻製程)執行的各項異性乾式蝕刻。在另一實施例中,用於蝕刻製程之蝕刻劑混合物可包含氟基蝕刻劑(fluorine-based etchant),諸如C
xF
y(例如,CF
4、C
4F
8、等等)、NF
3、類似者、或它們的組合,此蝕刻製程類似於下文關於第8圖描述之電漿蝕刻製程。在一些實施例中,遮罩層210及介電層206中之通孔開口204可具有與光敏遮罩260中之開口大約相同的寬度W
2(參見上文,第6圖)。定時蝕刻製程可用以蝕刻介電層206,直到通孔開口204部分地延伸至介電層206達一期望距離為止。在遮罩層210及介電層206中形成通孔開口204之後,光敏遮罩260(參見上文,第6圖)可用適當製程移除,諸如灰化製程,之後進行濕式清洗製程。
在第8圖中,執行圖案化製程以將遮罩層220、230、及240中開口之圖案傳遞至介電層206,從而在遮罩層210及介電層206中形成溝槽208,並將通孔開口204延伸穿過介電層206。在它們延伸穿過介電層206之後,通孔開口204從溝槽208之底部延伸至ESL 202。通孔開口204及溝槽208將隨後被填充以分別形成導電通孔及導電線(參見下文,第9圖至第10圖)。如後續將更詳細描述地,圖案化製程可包括一或多個蝕刻製程,其中遮罩層220、230、及240(參見上文,第7圖)用作蝕刻遮罩,並且遮罩層210未被遮罩層220、230、及240覆蓋之部分藉由一或多個蝕刻製程移除,以便溝槽208延伸至介電層206中並且通孔開口204延伸穿過介電層206。蝕刻劑可經選擇以對遮罩層210及240與介電層206之材料具有選擇性,對遮罩層220及230進行很少蝕刻或不蝕刻。在一些實施例中,藉由一或多個蝕刻製程移除遮罩層240。例如,當遮罩層210及240由相同材料(例如,氧化矽)形成時,遮罩層240可藉由用於在遮罩層210及介電層206中形成溝槽208之蝕刻製程而移除。通孔開口204隨後可藉由可接受的蝕刻技術而延伸穿過ESL 202,暴露導電特徵112之頂表面。在一些實施例中,溝槽208之第三寬度W
3在5 nm至40 nm之範圍中,以及通孔開口204之第四寬度W
4在5 nm至30 nm之範圍中。
在一些實施例中,用於介電層206之圖案化製程可包含一或多種蝕刻製程,其中遮罩層220、230、及240用作蝕刻遮罩。蝕刻可為任意可接受的蝕刻製程,諸如反應離子蝕刻(RIE)、中性束蝕刻(NBE)等,或上述組合。在一些實施例中,蝕刻製程為藉由電漿製程執行之各向異性乾式蝕刻。電漿蝕刻製程在處理腔室中執行,其中製程氣體被供應進處理腔室中。在一些實施例中,電漿為直接電漿。在一些實施例中,電漿為在連接至處理腔室之單獨電漿生成腔室中生成的遠端電漿。製程氣體可藉由生成電漿之任何適當方法而激化成電漿,諸如變壓器耦合電漿(transformer coupled plasma;TCP)系統、電感耦合電漿(inductively coupled plasma;ICP)系統、電容耦合電漿(capacitively coupled plasma; CCP)系統、磁性增強反應離子技術、電子迴旋共振技術、或類似者。
電漿蝕刻製程中使用的製程氣體包括一或多種蝕刻劑氣體。在一些實施例中,蝕刻劑氣體為氟基蝕刻劑氣體,諸如C
xF
y(例如,CF
4、C
4F
8、等等)、NF
3、類似者、或它們的組合。亦可使用額外製程氣體,諸如氧氣、氫氣、及/或C
xO
y氣體。載氣,諸如N
2、Ar、He、或類似者,可用於將製程氣體傳送進處理腔室中。製程氣體可以範圍為100 sccm至1000 sccm之速率流入處理腔室中。
電漿蝕刻製程可使用範圍在30伏特至1000伏特之偏壓執行。電漿蝕刻製程可使用範圍在30瓦特至1000瓦特之電漿生成功率執行。電漿蝕刻製程可在範圍在20°C至60°C之溫度下執行。處理腔室中之壓力可在3 mTorr至80 mTorr之範圍中。電漿蝕刻製程的執行時間可在30秒至200秒之範圍中。利用上述範圍外之蝕刻參數(例如,偏壓、持續時間等)執行電漿蝕刻製程可導致介電層206之不期望之蝕刻不足或過度蝕刻。
如上文所述,遮罩層220由含鎢遮罩材料形成,及遮罩層230由含鈦遮罩材料形成。在氟基蝕刻劑氣體用於將光敏遮罩260之圖案傳遞至遮罩層210及介電層206的一些實施例中,蝕刻劑氣體可與含鈦遮罩材料反應以形成諸如TiF
4之含鈦副產物,以及蝕刻劑氣體可與含鎢遮罩材料反應以形成諸如WF
6之含鎢副產物。例如,當遮罩層220由碳化鎢(WC)形成及蝕刻劑氣體包括氧氣及三氟化氮(NF
3)時,諸如六氟化鎢(WF
6)、一氧化碳(CO)、及氟化碳(C
xF
y)之副產物可根據
而形成。開口242及204之側壁及底表面上的剩餘副產物可導致後續形成之用於導電線及導電通孔之溝槽及開口的蝕刻不足,從而可導致接觸電阻之增大及元件效能之退化。因為TiF
4之沸點為約284°C,所以難以從開口242及204之側壁或底表面移除TiF
4。有利地,WF
6之沸點為約17°C,所以其可能藉由例如在室溫(例如,約 25°C)下昇華或蒸發而輕易地從開口242及204之側壁或底表面而移除。在一些實施例中,在高於WF
6之沸點且低於TiF
4之沸點的溫度下,諸如在約25°C之約室溫下,執行電漿蝕刻製程。
相較於使用沒有遮罩層220之較厚遮罩層230,結合遮罩層230使用遮罩層220允許減少含鈦副產物。此外,相較於沒有遮罩層230使用較厚遮罩層220,結合遮罩層220使用遮罩層230保留含鈦遮罩材料之優點,諸如相對於遮罩層210及遮罩層206的蝕刻具有提高的蝕刻選擇性。
在第9圖中,在結構上形成導電材料290以填充(或超填)通孔開口204及溝槽208(參見上文,第8圖)。在一些實施例中,導電材料290包括內襯通孔開口204及溝槽208之側壁及底表面的導電擴散阻障襯墊,及在導電擴散阻障襯墊上之導電填充材料。導電擴散阻障襯墊可減少導電材料外擴散進介電層206中。導電擴散阻障線可包括TaN、Ta、TiN、Ti、Co、類似者、或上述組合之一或多層。導電擴散阻障襯墊可藉由任何適當方法而沉積,諸如CVD、PECVD、PVD、ALD、PEALD、電鍍(electrochemical plating;ECP)、無電鍍等等。導電填充材料可包含金屬,諸如W、Cu、Co、Ru、CuMn、Mo、Al、或類似者、或它們的組合、或它們的多層。導電填充材料可藉由任何適當方法而沉積,例如CVD、PECVD、PVD、ALD、PEALD、電鍍(ECP)、無電鍍等等。在一些實施例中,薄導電晶種層可沉積在導電擴散阻障襯墊上以幫助引發ECP製程,其中導電填充材料填充開口。在一些實施例中,導電晶種層可為與導電填充材料相同的導電材料,並且可使用適當沉積方法(例如,CVD、PECVD、ALD、PEALD、或PVD等)沉積。
在第10圖中,執行移除製程以移除導電材料290之過量部分,其過量部分在介電層206之頂表面上。移除製程亦移除遮罩層210、220、及230(參見上文,第9圖)在介電層206上之剩餘部分。在移除製程之後,導電材料290具有部分保持在通孔開口204中(因而形成導電通孔104N-1)並具有部分保持在溝槽208中(因而形成導電線108N-1)。介電層206之剩餘部分為設置在導電通孔104N-1及導電線108N-1周圍之IMD層110N-1。移除製程可為諸如CMP或類似者之平面化製程。在平面化製程之後,導電線108N-1及IMD層110N-1之頂表面為共面的(在製程變化內)。移除製程完成互連級100N-1之製造,其包括嵌入IMD層110N-1中之導電通孔104N-1及導電線108N-1。
在第2圖至第10圖描述之製程之後,可形成額外互連級。第11圖圖示形成於中間互連級100N-1上之互連級100N。互連級100N包括IMD層110N和蝕刻停止層(ESL) 302,IMD層110N包括導電通孔104N及導電線108N。IMD層110N由例如介電層306形成。互連級100N可由上文針對互連級100N-1所述之類似材料及類似方法形成(參見上文,第2圖至第10圖)。
實施例可實現優勢。在含鎢遮罩層上形成包括含鈦遮罩層之多層遮罩,以利用雙重鑲嵌製程圖案化互連開口(包括溝槽及通孔開口)。含鈦遮罩層與用於圖案化互連開口之底層介電材料可具有改善之蝕刻選擇性。含鎢遮罩層可具有強物理模數,其可降低後續形成之導電線之線寬粗糙度(LWR)。此外,在多層遮罩中包含含鎢遮罩層幫助在圖案化互連開口期間減少非揮發性蝕刻副產物的量,從而減少蝕刻不足。
根據一實施例,一種方法包括以下操作:在第一導電特徵上沉積第一介電層;在第一介電層上沉積第一遮罩層,第一遮罩層包括碳化鎢;在第一遮罩層上沉積第二遮罩層,第二遮罩層包括氮化鈦;在第一遮罩層及第二遮罩層中圖案化第一開口,第一開口具有第一寬度;在第一開口之底表面中圖案化第二開口,第二開口延伸至第一介電層中,第二開口具有第二寬度,第二寬度小於第一寬度;以及第一開口延伸至第一介電層中,及第二開口延伸穿過第一介電層以暴露第一導電特徵之頂表面。在一實施例中,第一遮罩層之第一厚度在30 Å至200 Å之範圍中。在一實施例中,第二遮罩層之第二厚度在20 Å至100 Å之範圍中。在一實施例中,方法進一步包括以下操作,用導電材料填充第一開口及第二開口。在一實施例中,填充第一開口會在第一開口中形成導電線,導電線之第三寬度在5 nm至40 nm之範圍中。在一實施例中,填充第二開口會在第二開口中形成導電通孔,導電通孔之第四寬度在5 nm至30 nm之範圍中。在一實施例中,方法進一步包括在第二遮罩層上形成第三遮罩層之操作。在一實施例中,第三遮罩層包括氧化矽。
根據另一實施例,一種方法包括以下操作:在低介電常數介電層上沉積第一遮罩層,第一遮罩層為氧化矽;在第一遮罩層上沉積第二遮罩層,第二遮罩層為碳化鎢;在第二遮罩層上沉積第三遮罩層,第三遮罩層為氮化鈦;在第三遮罩層上沉積第四遮罩層,第四遮罩層為氧化矽;圖案化第二遮罩層、第三遮罩層、及第四遮罩層以形成溝槽;藉由蝕刻穿過第一遮罩層,將溝槽延伸至低介電常數介電層中;藉由用導電材料填充溝槽而形成導電線;以及移除第一遮罩層、第二遮罩層、第三遮罩層,以及第四遮罩層。在一實施例中,蝕刻穿過第一遮罩層之操作包括用氟基蝕刻劑蝕刻第一遮罩層。在一實施例中,第二遮罩層之楊氏模數在500 MPa至2000 MPa之範圍中。在一實施例中,當蝕刻穿過第一遮罩層時執行第四遮罩層之移除。在一實施例中,形成導電線之操作包括平面化導電材料,並且其中藉由平面化導電材料移除第一遮罩層、第二遮罩層、及第三遮罩層。
根據另一實施例,一種方法包括以下操作:在第一介電層上形成第一遮罩層,第一介電層在第一導電特徵上,此第一遮罩層包括碳化鎢;在第一遮罩層上沉積第二遮罩層,第二遮罩層包括氮化鈦;圖案化第一遮罩層及第二遮罩層;在圖案化第一遮罩層及第二遮罩層之後,使用第一遮罩層及第二遮罩層作為蝕刻遮罩藉由氟基蝕刻劑蝕刻第一介電層而形成延伸至第一介電層中的開口,此開口暴露第一導電特徵之頂表面,在第一溫度下執行利用氟基蝕刻劑蝕刻第一介電層,其中氟基蝕刻劑與第一遮罩層之第一副產物的沸點小於第一溫度。在一實施例中,氟基蝕刻劑與第二遮罩層之第二副產物的沸點大於第一溫度。在一實施例中,第二副產物為TiF
4。在一實施例中,第一副產物為WF
6。在一實施例中,利用電漿蝕刻製程執行第一介電層之蝕刻,並且氟基蝕刻劑為CF
4。在一實施例中,在範圍在20°C至60°C之溫度下執行電漿蝕刻製程。在一實施例中,第一溫度為室溫。
前面概述了幾個實施例的特徵,以便熟習本領域者可以更好地理解本揭示之各個態樣。熟習本領域者應當理解,他們可以容易地使用本揭示作為設計或修改其他製程及結構的基礎,以實現本文介紹的實施例的相同目的和/或實現其相同優點。熟習本領域者還應認識到,此類等效構造不脫離本揭示之精神及範疇,並且它們可以在不脫離本揭示之精神及範疇的情況下對本文進行各種改變、替換及變更。
60:半導體基板
62:元件
64:層間介電(ILD)層
66:觸點
70:互連結構
100:半導體元件
100A:互連級
100B:互連級
100N:互連級
100N-1:互連級
101:區域
104A:導電通孔
104B:導電通孔
104N:導電通孔
104N-1:導電通孔
108A:導電線
108B:導電線
108N:導電線
108N-1:導電線
110A:金屬間介電(IMD)層
110B:金屬間介電(IMD)層
110N:金屬間介電(IMD)層
110N-1:金屬間介電(IMD)層
112:導電特徵
114:介電層
202:蝕刻停止層(ESL)
202A:底部ESL
202B:中間ESL
202C:頂部ESL
204:通孔開口
206:介電層
208:溝槽
210:遮罩層
220:遮罩層
230:遮罩層
240:遮罩層
242:開口
250:光敏遮罩
250A:底層
250B:中間層
250C:頂層
260:光敏遮罩
260A:底層
260B:中間層
260C:頂層
290:導電材料
302:蝕刻停止層(ESL)
306:介電層
T
1:第一厚度
T
2:第二厚度
W
1:第一寬度
W
2:第二寬度
W
3:第三寬度
W
4:第四寬度
當結合附圖閱讀時,根據以下詳細描述可更好地理解本揭示案的態樣。應注意,根據工業標準實務,各種特徵未按比例繪製。事實上,為論述清楚,各特徵的尺寸可任意地增加或縮小。
第1圖根據一些實施例圖示一種半導體基板及積體電路之多層互連結構的橫截面視圖。
第2圖至第10圖根據一些實施例圖示半導體元件在製造之不同中間階段處的橫截面視圖。
第11圖根據一些實施例圖示半導體元件在製造之一中間階段處的橫截面視圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
無
60:半導體基板
62:元件
64:層間介電(ILD)層
66:觸點
70:互連結構
100:半導體元件
100A:互連級
100B:互連級
100N:互連級
100N-1:互連級
101:區域
104A:導電通孔
104B:導電通孔
104N:導電通孔
104N-1:導電通孔
108A:導電線
108B:導電線
108N:導電線
108N-1:導電線
110A:金屬間介電(IMD)層
110B:金屬間介電(IMD)層
110N:金屬間介電(IMD)層
110N-1:金屬間介電層
Claims (20)
- 一種方法,包括: 在一第一導電特徵上沉積一第一介電層; 在該第一介電層上沉積一第一遮罩層,該第一遮罩層包含碳化鎢; 在該第一遮罩層上沉積一第二遮罩層,該第二遮罩層包含氮化鈦; 在該第一遮罩層及該第二遮罩層中圖案化一第一開口,該第一開口具有一第一寬度; 在該第一開口之一底表面中圖案化一第二開口,該第二開口延伸至該第一介電層中,該第二開口具有一第二寬度,該第二寬度小於該第一寬度;以及 將該第一開口延伸至該第一介電層中,及將該第二開口延伸穿過該第一介電層以暴露該第一導電特徵之一頂表面。
- 如請求項1所述的方法,其中該第一遮罩層之一第一厚度在30 Å至200 Å之一範圍中。
- 如請求項1所述的方法,其中該第二遮罩層之一第二厚度在20 Å至100 Å之一範圍中。
- 如請求項1所述的方法,進一步包括用一導電材料填充該第一開口及該第二開口。
- 如請求項4所述的方法,其中填充該第一開口在該第一開口中形成一導電線,該導電線之一第三寬度在5 nm至40 nm之一範圍中。
- 如請求項4所述的方法,其中填充該第二開口在該第二開口中形成一導電通孔,該導電通孔之一第四寬度在5 nm至30 nm之一範圍中。
- 如請求項1所述的方法,進一步包括在該第二遮罩層上形成一第三遮罩層。
- 如請求項7所述的方法,其中該第三遮罩層包含氧化矽。
- 一種方法,包括: 在一低介電常數介電層上沉積一第一遮罩層,該第一遮罩層為氧化矽; 在該第一遮罩層上沉積一第二遮罩層,該第二遮罩層為碳化鎢; 在該第二遮罩層上沉積一第三遮罩層,該第三遮罩層為氮化鈦; 在該第三遮罩層上沉積一第四遮罩層,該第四遮罩層為氧化矽; 圖案化該第二遮罩層、該第三遮罩層、及該第四遮罩層以形成一溝槽; 藉由蝕刻穿過該第一遮罩層,將該溝槽延伸至該低介電常數介電層中; 藉由用一導電材料填充該溝槽而形成一導電線;以及 移除該第一遮罩層、該第二遮罩層、該第三遮罩層及該第四遮罩層。
- 如請求項9所述之方法,其中蝕刻穿過該第一遮罩層包括用一氟基蝕刻劑蝕刻該第一遮罩層。
- 如請求項9所述的方法,其中該第二遮罩層之一楊氏模數在500 MPa至2000 MPa之一範圍中。
- 如請求項9所述的方法,其中當蝕刻穿過該第一遮罩層時執行該第四遮罩層之移除。
- 如請求項9所述的方法,其中形成該導電線包括平面化該導電材料,並且其中藉由該平面化該導電材料移除該第一遮罩層、該第二遮罩層、及該第三遮罩層。
- 一種方法,包括: 在一第一介電層上形成一第一遮罩層,該第一介電層在一第一導電特徵上,該第一遮罩層包含碳化鎢; 在該第一遮罩層上沉積一第二遮罩層,該第二遮罩層包含氮化鈦; 圖案化該第一遮罩層及該第二遮罩層;以及 在圖案化該第一遮罩層及該第二遮罩層之後,使用該第一遮罩層及該第二遮罩層作為一蝕刻遮罩藉由用一氟基蝕刻劑蝕刻該第一介電層而形成延伸至該第一介電層中的一開口,該開口曝露該第一導電特徵之一頂表面,在一第一溫度下執行用該氟基蝕刻劑蝕刻該第一介電層,其中該氟基蝕刻劑與該第一遮罩層的一第一副產物的一沸點小於該第一溫度。
- 如請求項14所述的方法,其中該氟基蝕刻劑與該第二遮罩層的一第二副產物的一沸點大於該第一溫度。
- 如請求項15所述的方法,其中該第二副產物為TiF 4。
- 如請求項14所述的方法,其中該第一副產物為WF 6。
- 如請求項14所述的方法,其中用一電漿蝕刻製程執行該第一介電層之蝕刻,並且該氟基蝕刻劑為CF 4。
- 如請求項18所述的方法,其中在範圍在20°C至60°C之一溫度下執行該電漿蝕刻製程。
- 如請求項14所述的方法,其中該第一溫度為室溫。
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Application Number | Priority Date | Filing Date | Title |
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US17/399,262 US11842922B2 (en) | 2021-08-11 | 2021-08-11 | Method for forming interconnect structure |
US17/399,262 | 2021-08-11 |
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Publication Number | Publication Date |
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TW202308036A true TW202308036A (zh) | 2023-02-16 |
TWI837554B TWI837554B (zh) | 2024-04-01 |
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US20230050514A1 (en) | 2023-02-16 |
US11842922B2 (en) | 2023-12-12 |
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