CN115398612A - 具有辐射屏蔽的集成式封装中的系统 - Google Patents
具有辐射屏蔽的集成式封装中的系统 Download PDFInfo
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- CN115398612A CN115398612A CN202180028312.1A CN202180028312A CN115398612A CN 115398612 A CN115398612 A CN 115398612A CN 202180028312 A CN202180028312 A CN 202180028312A CN 115398612 A CN115398612 A CN 115398612A
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- 230000005855 radiation Effects 0.000 title description 3
- 230000000903 blocking effect Effects 0.000 claims abstract description 54
- 238000002161 passivation Methods 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000003989 dielectric material Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 137
- 238000000034 method Methods 0.000 claims description 39
- 238000000465 moulding Methods 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000011068 loading method Methods 0.000 claims description 9
- 238000005553 drilling Methods 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims 2
- 230000008569 process Effects 0.000 description 23
- 239000000463 material Substances 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
- 239000002390 adhesive tape Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 238000007747 plating Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 230000036039 immunity Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- WBHQEUPUMONIKF-UHFFFAOYSA-N PCB180 Chemical compound C1=C(Cl)C(Cl)=CC(Cl)=C1C1=CC(Cl)=C(Cl)C(Cl)=C1Cl WBHQEUPUMONIKF-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000006229 carbon black Substances 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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Abstract
封装中的系统(SIP)(195)包括载体层区域(107),这些载体层区域包括具有贯穿其中的金属柱(109)的介电材料,其中相邻载体层区域限定了间隙。驱动器IC管芯(110)定位于间隙中并具有节点,这些节点连接到通过第一钝化层(113)的顶侧中的开口暴露出的键合焊盘(111),其中键合焊盘朝上。介电层(116)位于第一钝化层和载体层区域(107)上,并且包括耦合到键合焊盘和金属柱(109)的填充通孔(116a)。光阻挡层(118)位于衬底的侧壁和底部上。第一器件(140)包括具有第一可键合特征部(151a)的光发射器。光阻挡层阻挡至少90%的入射光。第一可键合特征部被倒装安装到键合焊盘的第一部分。
Description
技术领域
本公开涉及封装中的系统(SIP)。
背景技术
一些SIP包括驱动器集成电路(IC)和一个或多个其它器件。驱动器IC包括一些数字电路,这些数字电路通常包括用于实际驱动器功能的信号处理和逻辑及模拟电路。例如,金属氧化物半导体场效应晶体管(MOSFET)驱动器取得从处理器或控制器接收低电平数字信号,并在其输出端处递送具有不同电压和电流的信号。SIP器件可包括发光器件(诸如发光二极管(LED)或半导体激光器(其通常是垂直发射激光器))以及其它器件(诸如无源器件,包括电感器或电容器)。
此类SIP的已知解决方案安装封装的驱动器IC管芯、特殊芯片(诸如发光器件和无源器件),所有这些都在客户的印刷电路板(PCB)上彼此横向放置。例如,一些已知的SIP布置将封装的驱动器IC和发光器件尽可能近地并排放置在PCB上,并使用用于阻挡光的有机密封物和用于最小化电磁干扰(EMI)的金属密封物来屏蔽封装的驱动器IC免受发光器件的辐射。用于阻挡光的有机密封物可包括模塑料。用于最小化EMI的金属密封物可包括可溅射到模塑料上的金属层。
发明内容
提供本概述以简化的形式介绍已公开的概念的简要选择,这些概念将在下文的具体实施方式(包括所提供的附图)中进一步描述。本概述不旨在限制要求保护的主题的范围。
本公开认识到面积受限的PCB和高速应用可从SIP中受益,该SIP包括:器件A,其包括驱动器IC管芯;器件B,其是也可生成EMI的发光器件;以及可选的器件C,其可以是无源器件,诸如电感器、电容器或电阻器。器件B和器件C并排堆叠在器件A上,同时满足若干需求。一种需求是器件A对从器件B接收到的光或EMI的抗扰性,并且也可能是对从器件C接收到的光或EMI的抗扰性。另一需求是在器件A和器件B之间以及当可选地包括器件C时器件A和器件C之间具有最短的互连长度,以最小化器件到器件互连的电感(和电阻)。另一需求是器件B和器件C对环境的低热阻(θJA),这可以被器件A的加热阻碍。已认识到对光和EMI/热性能的抗扰性以及SIP的邻近性/大小通常是相互冲突的需求。
尽管存在这些相互冲突的需求,本公开描述了通常提供上述所有需求的SIP,该SIP包括三维(3D)器件布置,其包括:器件A,在器件A上的器件B,以及可选地也在器件A上的器件C。因此公开的SIP包括:器件A,其是驱动器IC管芯;器件B,其是也可生成EMI的发光器件;以及可选地另一器件C。公开的SIP包括在器件A的顶部上的光阻挡层,该光阻挡层提供对来自器件B的光和/或EMI的抗扰性,以及对来自器件C(当也可选地提供C时)的光和/或EMI免于到达器件A的抗扰性。虽然器件A包括驱动器IC管芯,但器件B和器件C可以各自是IC管芯形式,或者也可以是一般任何形式的封装器件,诸如提供为有引线封装或无引线封装。
公开的一些方面包括一种SIP,该SIP包括包含介电材料的载体层区域,该介电材料具有穿过其厚度延伸的至少一个金属柱,其中相邻载体层区域限定了间隙。包括衬底的驱动器IC管芯位于间隙中并具有连接到通过第一钝化层的顶侧中的开口暴露出的键合焊盘的节点,其中键合焊盘朝上。介电层位于第一钝化层和载体层区域上并且包括用于耦合到键合焊盘和金属柱的填充通孔。光阻挡层位于衬底的侧壁和底部上。包括光发射器的第一器件具有第一可键合特征部。该光阻挡层可阻挡从光发射器接收的入射光的至少90%。第一可键合特征部通过焊料连接倒装到键合焊盘的第一部分。
附图说明
现在将参考附图,该附图不一定按比例绘制,在附图中:
图1A-图1I示出与形成公开的SIP的示例方法相对应的连续横截面视图。图1A示出在支撑载体上施加粘性胶带之后的结果。图1B示出在粘性胶带的顶部上施加可为光阻挡层的介电层之后的结果。图1C示出在介电层上形成多个载体层区域并在载体层区域之间的间隙中放置驱动器IC管芯之后的结果,每个载体层区域具有从其中穿过的至少一个金属柱。图1D示出在载体层区域和驱动器IC管芯之间的间隙中形成光阻挡层之后的结果。图1E示出将处理中的SIP器件的片材从支撑载体剥离之后的结果。图1F示出翻转处理中的SIP器件的片材并且然后在介电层中形成通孔之后的结果。图1G示出在施加包括金属特征部的光阻挡钝化层并且然后图案化片材的两侧之后的处理中的SIP器件的片材的结果,该金属特征部穿通光阻挡钝化层的片材的两侧。图1H示出在片材的两侧上的金属特征部上方形成焊料球之后的处理中的SIP器件的片材的结果。图1I示出对处理中的SIP器件的片材进行单片化以提供多个SIP器件之后的结果。图1J示出在单片化后将图1I中所示的SIP中的一个SIP组装到PCB上之后的结果。
图2A-图2E示出与形成公开的SIP的示例方法相对应的连续横截面视图。图2A示出包括引线框架金属的预模制引线框架,该引线框架金属包括管芯焊盘和多个引线或引线端子,其中管芯焊盘和引线或引线端子由模塑料(mold compound)隔开。图2B示出使用管芯附接材料将驱动器IC管芯顶部朝上进行管芯附接并进行镀覆以将金属柱(例如,包括铜)形成到驱动器IC管芯的相应侧面上的引线或引线端子上之后的处理中的SIP。图2C示出进行包覆成型以形成模塑料并且然后将模塑料打磨到期望最终厚度之后的处理中的SIP。图2D示出进行钻孔以贯穿驱动器IC管芯的顶侧上方的模塑料的厚度形成孔并且在钻孔后在驱动器IC管芯的键合焊盘上方所示区域中描绘的孔中形成金属以提供图示的键合特征部之后的处理中的SIP。图2E示出在使用图案化介电层镀覆图案化再分配层(RDL)以接触键合特征部并接触金属柱的顶侧之后的处理中的SIP。图2F示出附接器件B和器件C之后的SIP。图2G示出将SIP组装到PCB的承接焊盘(land pad)上之后的最终SIP布置。
图3示出示例SIP的横截面视图。
图4示出示例SIP的横截面视图。
图5示出另一示例SIP的横截面视图。
图6示出另一示例SIP的横截面视图。
具体实施方式
参考附图描述了一些示例方面,其中类似的附图标记被用于指示类似或等效的元素。动作或事件的图示顺序不应被视为限制,因为一些动作或事件可能以不同的顺序发生和/或与其它动作或事件同时发生。此外,根据本公开来实现方法可能不需要一些图示的动作或事件。
此外,本文中不加进一步限定的术语“耦合到”或“与……耦合”等旨在描述间接或直接电气连接。因此,如果第一器件“耦合”到第二器件,则该连接可以通过直接电气连接(在通路中只有寄生效应),或者经由中间项目(包括其它器件和连接件)进行间接电气连接。对于间接耦合,中间项目通常不修改信号的信息,但可以调节其电流水平、电压水平和/或功率水平。
图1A-图1I示出与形成公开的SIP的示例方法相对应的连续横截面视图,而图1J示出根据一个示例方面在将从SIP器件片材单片化后在图1I中示出为190的SIP之一组装到PCB 180之后的结果。图1A示出在将粘性胶带108应用到支撑载体106上之后的结果。粘性胶带108通常包括双面粘性胶带,其可以包括热胶带或光释放胶带。一种具体的双面胶带示例是由布鲁尔科学公司(Brewer Science)作为激光释放材料销售的商用粘合剂产品。
支撑载体106可以包括金属(诸如铜)或非金属衬底(诸如PCB或玻璃),其中支撑载体106具有足以形成包括多个SIP的二维(2D)SIP器件片材的面积。图1B示出在粘性胶带108的顶部应用可为光阻挡层的介电层116之后的结果。例如,介电层116可以包括含有碳负载的环氧树脂,其中负载水平足以阻挡光,诸如在一般在约10μm至100μm的范围内的厚度处具有0.1%至10%(通常为1%至10%)的炭黑含量。
图1C示出在介电层116上形成各自具有贯穿其中的至少一个金属柱109的多个载体层区域107并且然后在载体层区域107之间的间隙中放置驱动器IC管芯110之后的结果。用于载体层区域107的介电材料可以包括已知为由味之素集团公司(Ajinomoto Group)销售的味之素合成膜(ABF)的商用介质材料,已知其为一种三层聚合物体系,其具有聚对苯二甲酸乙二醇酯(PET)支撑膜、树脂层和覆盖膜。用于载体层区域107的介电材料还可以包括预浸料,该预浸料在本技术中已知为通常是环氧树脂的已预浸树脂体系的增强织物。
可以看到载体层区域107中的相邻载体层区域彼此隔开,以提供具有比驱动器IC管芯110的尺度更大的尺寸的间隙,使得驱动器IC管芯110能够被放置在间隙内。关于形成各自具有贯穿其中的金属柱109的载体层区域107的过程,金属柱109可以通过以下操作被预先形成在稍后变成载体层区域107的未图案化介电材料中:首先穿过介电材料进行通孔钻孔,然后进行籽晶沉积,然后进行镀覆(例如镀铜),然后进行蚀刻以在通孔中只留下金属柱109,然后在载体层区域107中的相邻载体层区域之间的介电材料中形成本文称为间隙的空腔。可以使用材料去除工艺(例如包括激光打孔)来形成这些间隙。然后在这些间隙中放置驱动器IC管芯110。
驱动器IC管芯110包括衬底105(诸如包含硅),其包括在其顶侧上与其电路160中的节点耦合的键合焊盘111,以及通常包含键合焊盘111上的铜的支柱(pillar)112。支柱112和键合焊盘111二者均显示在钝化层113内,该钝化层113在此也被称为第一钝化层。驱动器IC管芯110顶部朝下放置在相邻载体层区域107之间的间隙中的介电层116上。
驱动器IC管芯110上的电路160可以包括诸如在衬底105中形成的电路元件(包括晶体管以及通常的二极管、电阻器、电容器等),该衬底包括大块衬底材料上的外延层,其被配置在一起以实现至少一种驱动功能,以及可选的一种或多种其它电路功能。示例附加电路功能包括处理器以及模拟功能(例如放大器或功率转换器或负载开关)、射频(RF)功能、数字功能或非易失性存储器功能。
图1D示出形成光阻挡层118之后的结果,该光阻挡层118通常在载体层区域107与驱动器IC管芯110之间的间隙中提供高导热性。在该工艺流程中,如下所述,光阻挡层118还为驱动器IC管芯110提供管芯附接层。光阻挡层118可以是烧结Ag(银)层,或者可以包括焊料。形成光阻挡层118的工艺可以包括冲成型(flush molding),该冲成型包括填充载体层区域107的边缘与驱动器IC管芯110之间的间隙。然而,虽然没有示出,但可能存在也应用在这些间隙之外(包括也存在于处理中的SIP器件的片材的支撑载体106的背面上)的一些光阻挡层118。
图1E示出将处理中的SIP器件的片材从支撑载体106剥离之后的结果。例如,可以通过激光处理或通过用以导致粘性胶带108释放的热释放工艺来实现剥离。剥离操作通常在商用剥离器上进行,该剥离器通常用于形成穿通硅通孔(TSV)并用于形成扇出封装件。图1F示出在翻转处理中的SIP器件的片材并且然后在介电层116中形成示出为116a的通孔之后的结果。例如,可以通过激光烧蚀来形成通孔116a,诸如通过在驱动器IC管芯110的键合焊盘111上的支柱112所示的金属上停止的二氧化碳或紫外线(UV)激光器来执行。可以看出通孔116a的尺寸比支柱112的面积尺寸更大。
图1G示出在施加光阻挡钝化层121并且然后对片材的两侧进行图案化之后的处理中的SIP器件的片材的结果,其中该光阻挡钝化层121可以包括堆积层片材,该堆积层片材包括通到光阻挡钝化层121的片材的两侧的金属特征部122。片材的顶侧上的金属特征部122也填充了介电层116中的通孔116a,该金属填充的通孔被显示为119。为此目的通常执行相对于通孔116a的对准,并且光阻挡钝化层121的形成工艺可包括半增材镀覆工艺或减材蚀刻工艺。金属特征部122包括位于SIP两侧上的金属柱109上方的金属特征部。图1H示出在片材两侧上的金属特征部122上方形成焊料球126之后的处理中的SIP器件的片材的结果。
图1I示出对处理中的SIP器件的片材进行单片化以提供多个SIP器件之后的结果,每个SIP器件被显示为SIP 190。典型的单片化工艺可用于此目的,诸如包括采用金刚石刀片的机械锯切的工艺。图1J示出在将SIP 190之一组装到PCB 180的承接焊盘181上并且然后将彼此横向的器件B 140和器件C 150组装到驱动器IC管芯110的顶侧上示出的焊料球126上之后的SIP布置195。驱动器IC管芯110被示出为包括形成在衬底105中的其电路160。器件B 140和器件C 150分别包括示出为151a(称为第一可键合特征部)和151b(称为第二可键合特征部)的键合特征部,以用于接触焊料球126。
器件B 140可以包括一个或多个LED、麦克风,或半导体激光器,诸如垂直腔表面发射激光器(VCSEL),这已知为一种类型的半导体激光二极管,其提供垂直于器件的顶表面取向的激光束发射。器件C 150可以包括电容器(诸如表面贴装电容器、层压电容器、沟槽电容器(例如在硅中形成))、电感器,或可包括环境传感器的MEMS器件,其中器件B 140和器件C150可以各自焊接为表面贴装(SMT)器件。
在器件B 140和驱动器IC管芯110之间存在由SIP布置195提供的面对面互连件(参见下面描述的图3中标示的面对面互连件318)。所公开的在短长度上的面对面互连件提供通常为1pH至500pH的低电感,以及通常<1mOhm至约100mOhm的低电阻。
还提供了一种用于SIP布置195的低热阻路径,它通过包括光阻挡层118而用作驱动器IC管芯110的高导热性管芯附接材料,其中光阻挡层118通常也是扩散性的。扩散性是一种材料特性,其与耗散来自电力快速爆发的热量的热传导有关,对于器件B 140和器件C150来说,通常都是耗散关于驱动器IC管芯110的热量。光阻挡层118通常提供在20℃处至少为10W/m·K的热导率,以便为器件B 140和器件C 150提供导热路径,诸如光阻挡层118提供10W/m·K至150W/m·K的热导率。
如上所述,器件B 140和器件C 150可以各自是封装器件,或者也可以是IC管芯。器件B 140和器件C 150的键合特征部151a和151b分别可以包括焊料整饰过的底面凸块金属、化学镍浸金(ENIG)、化学镍浸钯浸金(ENIPIG)或有机焊锡防腐剂(OSP)。
图2A-图2E示出与形成公开的SIP的示例方法相对应的连续横截面视图,而图2F示出将器件B 140和器件C 150附接到驱动器IC管芯110上之后的结果。图2G示出将图2F中所示的SIP 250组装到PCB 180的承接焊盘181上之后的结果。
图2A示出包括引线框架金属的预模制引线框架217,该引线框架金属包括管芯焊盘217a和多个引线或引线端子217b,其中管芯焊盘217a和引线或引线端子217b由模塑料218分隔。图2A中所示的结构通常可以在商业上获得,其中预模制引线框架217显示在支撑载体106上。图2B示出在使用管芯附接材料221将驱动器IC管芯110顶部向上进行管芯附接之后以及在驱动器IC管芯110的相应侧面上的引线或引线端子217b上进行镀覆以形成示出为109a的金属柱(例如包括铜)之后的处理中的SIP。
图2C示出在进行包覆成型以形成模塑料231并且然后将模塑料231和金属柱109a打磨到期望的最终厚度之后的处理中的SIP。如图所示,在驱动器IC管芯110的顶侧上方存在一些模塑料231。图2D示出在进行钻孔以形成贯穿驱动器IC管芯110顶侧上方的模塑料231的厚度的孔并在钻孔后在驱动器IC管芯110的键合焊盘111上方所示区域中描绘的孔中形成金属(例如铜)以提供所示的键合特征部232之后的处理中的SIP。钻孔可以包括激光钻孔、化学湿法蚀刻或等离子体蚀刻。
图2E示出在使用图案化介电层243(诸如包括图案化焊料掩模层)对图案化RDL242进行镀覆以接触键合特征部232并接触金属柱109a的顶侧之后的处理中的SIP。虽然示出单个RDL 242,但正如本领域中所知,可以存在两个或更多个RDL层。图2F示出附接器件B140和器件C 150之后的SIP 250。图2G示出在将SIP 250组装到PCB 180的承接焊盘181上之后的示出为280的最终SIP布置。
图3示出示例SIP 300。SIP 300与图1J中所示的SIP 190相关,其将器件B140和器件C 150附接到驱动器IC管芯110的顶部上,其中与SIP 190一样,SIP300中的器件B 140和器件C 150分别包括键合特征部151a和151b。SIP 300示出器件C 150和驱动器IC管芯110之间的连接件包括所公开的标示为318的面对面互连件,其包括第一键合特征部151b、焊料球126、金属特征部122、支柱112和键合焊盘111。在器件B 150和驱动器IC管芯110之间也存在类似的面对面连接件(不包括图3中的附图标记)。所公开的面对面互连件通常长度较短,通常在5μm至200μm的长度(诸如5μm至25μm的长度)范围内,以提供低电感,并且如上所述具有通常为1pH至500pH的电感,以及通常<1mOhm至约100mOhm的低电阻。
虽然SIP 190具有光阻挡层118,但SIP 300具有光阻挡钝化层121(诸如预浸层),其由于诸如炭黑的不透明材料的高负载(意味着至少1%重量百分比)而能够阻挡光。驱动器IC管芯110的衬底105(其通常包括含有电路160的掺杂硅)与通常被公开为金属并因此可导电的(诸如包括焊料)的光阻挡层118之间的电耦合被阻止,因为衬底105在操作中通常会接地。因此,衬底105与光阻挡层118之间的任何耦合都会延伸到接地。在驱动器IC管芯110的底部处示为126a的焊料特征部(显示为未连接到电路160)用作热球栅阵列(BGA)特征部,用于在SIP 300的操作期间散热。与图1J中所示类似,在SIP 300的底部上也示出了驱动器IC管芯110上方的光阻挡钝化层121。
图4示出示例SIP 400,其包括嵌入式管芯四方扁平无引线(QFN)封装件。SIP 400与SIP 300的区别之处在于在驱动器IC管芯110的两侧都包括封装钝化层215,该封装钝化层215位于在光阻挡层118上的驱动器IC管芯110的顶侧上的第一钝化层113上。封装钝化层215可以包括预浸层。SIP 400还包括光阻挡钝化层121,该光阻挡钝化层121通常被形成为堆积层以包括延伸穿过光阻挡钝化层121的全厚度的129a上的导电特征部129b。因此,对于SIP 400,光阻挡钝化层121在封装钝化层215的顶部上。此外,对于SIP 400,虽然封装钝化层215通常不阻挡光,因为光阻挡是由光阻挡钝化层121提供的。然而,如果封装钝化层215包括碳负载,也有可能使封装钝化层215可选地阻挡光。
图5示出示例SIP 500。SIP 500与SIP 400的不同之处在于包括光阻挡粘合层518,该光阻挡粘合层可以包括具有高炭黑含量(通常为至少1%重量百分比)的环氧树脂或预浸层,其一般为10μm至100μm厚并位于第一钝化层113和封装钝化层215之间,该封装钝化层215也可称为第二钝化层。热BGA 126a被显示在SIP 500的底侧上。
图6示出示例SIP 600。SIP 600与图4所示的SIP 400的区别之处在于在驱动器IC管芯110的衬底105的背面上包括背面金属层610。
示例
所公开的一些方面由以下具体示例进一步示出,该示例不应被解释为以任何方式限制本公开的范围或内容。使用模拟来进行实验以评估公开的SIP的热性能和电性能,该SIP在驱动器IC管芯与器件B和器件C之间具有低电感和低串联电阻的面对面互连。下表包括该评估数据,其中对比显示了公开的SIP和参考SIP。
参考SIP包括VCSEL,该VCSEL对应于上面描述的器件B,该器件B安装在包括驱动器/控制器IC管芯的传统QFN封装件的顶部上。VCSEL和下面用于参考SIP的驱动器/控制器IC管芯之间的电气连接通过模具内通孔(vias-in-mold)布置来建立。虽然该参考SIP设计与并排的SIP设计相比在热性能上更优越,但在VCSEL和如表中示为“焊盘”的引线框架的管芯焊盘之间仍然存在很高的热阻。该高热阻由如下因素产生:VCSEL和驱动器/控制器IC管芯之间的厚模塑料,为热流提供有限传导路径的通孔结构和图案,以及管芯附接材料为非导热环氧树脂。
如上表所示,已发现一种公开的SIP可以通过最小化模具厚度,用实心铜焊盘取代通孔结构并且使管芯附接材料还包括热导率相对较高的烧结银管芯附接材料来显著降低热阻。对于所公开的SIP,已发现VCSEL和管芯焊盘之间的总热阻从42.1℃/W降低到26.7℃/W,降低了37%,这使得VCSEL在公开的SIP中与参考SIP相比能够多耗散53%的能量。
所公开的一些方面可以被集成到各种组装流程中,形成各种不同的SIP封装件和相关产品。SIP可以包括单个半导体管芯或多个半导体管芯,诸如包括多个堆叠半导体管芯的配置。可以使用多种封装衬底。半导体管芯可以包括其中的各种元件和/或其上的层,包括阻挡层、介电层、器件结构、有源元件和无源元件,包括源极区、漏极区、位线、底座、发射极、集电极、导电线、导电通孔等。此外,半导体管芯可以由多种工艺形成,包括双极、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS。
本公开所涉及的本领域技术人员将认识到,在所述发明的范围内,公开的方面可能有许多变化,并且对上述方面进行进一步的添加、删除、替换和修改而不脱离本公开的范围。
Claims (23)
1.一种封装中的系统SIP,其包括:
载体层区域,其包括具有贯穿其中的至少一个金属柱的介质材料,所述载体层区域中的相邻载体层区域限定了间隙,所述间隙具有足以在所述间隙内放置驱动器集成电路IC管芯的尺寸;
在所述间隙内的所述驱动器IC管芯,其包括衬底,所述衬底具有被配置用于一定功能的电路,其节点连接到通过第一钝化层顶侧的开口暴露出的键合焊盘,其中所述驱动器IC管芯以所述键合焊盘朝上定位;
在所述第一钝化层和所述载体层区域上的介电层,其包括贯穿其中耦合到所述键合焊盘和所述金属柱的填充通孔;
在所述衬底的侧壁和底侧上的光阻挡层;以及
第一器件,其包括用于发射一定波长的光的光发射器,所述光发射器具有在其上的第一可键合特征部,以及
其中所述第一可键合特征部被倒装安装,并且包括与所述键合焊盘的第一部分的焊料连接。
2.根据权利要求1所述的SIP,其中所述光阻挡层在20℃处具有至少10W/m·K的热导率,并且阻挡入射到其上的至少90%的光。
3.根据权利要求1所述的SIP,
进一步包括横向于所述第一器件定位的第二器件,所述第二器件具有第二可键合特征部,
其中所述第二可键合特征部被倒装安装,并且包括与所述键合焊盘的第二部分的焊料连接。
4.根据权利要求1所述的SIP,进一步包括在所述第一钝化层上的第二钝化层,以及在所述第二钝化层上的附加光阻挡钝化层。
5.根据权利要求1所述的SIP,进一步包括在所述第一钝化层上的光阻挡粘合层和在所述光阻挡粘合层上的第二钝化层。
6.根据权利要求1所述的SIP,进一步包括在所述驱动器IC管芯的背面上的背面金属层。
7.根据权利要求2所述的SIP,其中所述第二器件包括电阻器、电容器或电感器。
8.根据权利要求1所述的SIP,其中所述光发射器包括半导体激光器或发光二极管LED,并且其中所述波长为500nm至2000nm。
9.根据权利要求1所述的SIP,其中所述光阻挡层包括金属、金属合金或聚合物,所述聚合物包括处于至少1%重量百分比的负载水平的碳负载。
10.根据权利要求1所述的SIP,其中所述介电层包括用于阻挡光的处于至少1%重量百分比的负载水平的碳负载。
11.一种封装中的系统,其包括:
引线框架,其包括管芯焊盘和多个引线或引线端子,其中所述管芯焊盘与所述引线或引线端子被模塑料隔开;
在所述管芯焊盘上的驱动器集成电路IC管芯,其包括衬底,所述衬底具有被配置用于一定功能的电路,其节点连接到包括第一键合焊盘的多个键合焊盘,其中所述驱动器IC管芯以所述多个键合焊盘朝上定位于所述管芯焊盘上;
在所述驱动器IC管芯的顶侧上方的图案化再分配层RDL;
在所述驱动器IC管芯的侧面上的模塑料,所述模塑料具有贯穿其厚度并附接到所述引线或所述引线端子的金属柱;
其中所述RDL包括在所述第一键合焊盘上方的第一部分以及在所述多个键合焊盘中的一些键合焊盘与所述金属柱之间的迹线,以及
第一器件,其包括用于发射一定波长的光的光发射器,所述光发射器具有在所述RDL的所述第一部分上的第一可键合特征部。
12.根据权利要求11所述的封装中的系统,其中所述RDL阻挡入射到其上的至少90%的光。
13.一种形成封装中的系统SIP的方法,其包括:
提供载体层区域,所述载体层区域包括具有穿过所述载体层区域的厚度的至少一个金属柱的介电材料,所述载体层区域中的相邻载体层区域限定了间隙,所述间隙具有足以在所述间隙内放置驱动器集成电路IC管芯的尺寸;
将所述驱动器IC管芯定位在所述间隙内,所述驱动器IC管芯包括衬底,所述衬底具有被配置用于一定功能的电路,其节点连接到通过第一钝化层顶侧的开口暴露出的键合焊盘,其中所述驱动器IC管芯以所述键合焊盘朝上定位;
在所述第一钝化层和所述载体层区域上形成介电层,所述介电层包括贯穿其中耦合到所述键合焊盘和所述金属柱的填充通孔;
在所述衬底的侧壁上和底侧上形成光阻挡层,所述光阻挡层在20℃处具有至少10W/m·K的热导率;以及
倒装安装第一器件至所述键合焊盘的第一部分,所述第一器件包括用于发射一定波长的光的光发射器,所述光发射器具有第一可键合特征部,其中所述倒装安装包括形成焊料连接。
14.根据权利要求13所述的方法,其中所述光阻挡层在20℃处具有至少10W/m·K的热导率,并阻挡入射到其上的至少90%的光。
15.根据权利要求13所述的方法,进一步包括倒装安装横向于所述第一器件定位的第二器件至所述键合焊盘的第二部分,所述第二器件具有第二可键合特征部。
16.根据权利要求13所述的方法,进一步包括在所述第一钝化层上形成第二钝化层,并添加附加的光阻挡钝化层,所述附加的光阻挡钝化层包括在所述SIP的顶侧和底侧上的堆积层。
17.根据权利要求13所述的方法,进一步包括在所述第一钝化层上施加光阻挡粘合层,并在所述光阻挡粘合层上形成第二钝化层。
18.根据权利要求13所述的方法,进一步包括在所述驱动器IC管芯的背面上形成背面金属层。
19.根据权利要求13所述的方法,其中所述第二器件包括电阻器、电容器或电感器。
20.根据权利要求13所述的方法,其中所述光发射器包括半导体激光器或发光二极管LED,并且其中所述波长为500nm至2000nm。
21.根据权利要求13所述的方法,其中所述光阻挡层包括金属、金属合金或聚合物,所述聚合物包括处于至少1%重量百分比的负载水平的碳负载。
22.根据权利要求13所述的方法,进一步包括使用激光钻孔来形成所述间隙。
23.根据权利要求13所述的方法,进一步包括在所述键合焊盘上形成金属支柱。
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