CN115380387A - 用于超结器件的工艺和结构 - Google Patents
用于超结器件的工艺和结构 Download PDFInfo
- Publication number
- CN115380387A CN115380387A CN202180011391.5A CN202180011391A CN115380387A CN 115380387 A CN115380387 A CN 115380387A CN 202180011391 A CN202180011391 A CN 202180011391A CN 115380387 A CN115380387 A CN 115380387A
- Authority
- CN
- China
- Prior art keywords
- vertical pillar
- layer
- gate
- trench
- contact region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/152—Source regions of DMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/152—Source regions of DMOS transistors
- H10D62/154—Dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
- H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Composite Materials (AREA)
- Crystallography & Structural Chemistry (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/778,904 US11316042B2 (en) | 2020-01-31 | 2020-01-31 | Process and structure for a superjunction device |
| PCT/US2021/023142 WO2021155386A1 (en) | 2020-01-31 | 2021-03-19 | Process and structure for a superjunction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115380387A true CN115380387A (zh) | 2022-11-22 |
Family
ID=77062344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180011391.5A Pending CN115380387A (zh) | 2020-01-31 | 2021-03-19 | 用于超结器件的工艺和结构 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11316042B2 (https=) |
| EP (1) | EP4097763A4 (https=) |
| JP (1) | JP7631353B2 (https=) |
| KR (1) | KR102860640B1 (https=) |
| CN (1) | CN115380387A (https=) |
| WO (1) | WO2021155386A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11569345B2 (en) * | 2020-11-23 | 2023-01-31 | Alpha And Omega Semiconductor (Cayman) Ltd. | Gas dopant doped deep trench super junction high voltage MOSFET |
| US12074196B2 (en) * | 2021-07-08 | 2024-08-27 | Applied Materials, Inc. | Gradient doping epitaxy in superjunction to improve breakdown voltage |
| US20260068236A1 (en) * | 2024-08-29 | 2026-03-05 | Applied Materials, Inc. | Trench-based super junction structures via sidewall doping |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1234613A (zh) * | 1998-04-23 | 1999-11-10 | 国际整流器有限公司 | P沟道槽型金属氧化物半导体场效应晶体管结构 |
| US20100013010A1 (en) * | 2008-07-16 | 2010-01-21 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20100237416A1 (en) * | 2009-03-17 | 2010-09-23 | Alpha & Omega Semiconductor Incorporated | Bottom-drain ldmos power mosfet structure having a top drain strap |
| CN102709320A (zh) * | 2012-02-15 | 2012-10-03 | 中山大学 | 纵向导通的GaN基MISFET 器件及其制作方法 |
| US20140124851A1 (en) * | 2012-11-08 | 2014-05-08 | Infineon Technologies Austria Ag | Radiation-Hardened Power Semiconductor Devices and Methods of Forming Them |
| US20160268446A1 (en) * | 2015-03-10 | 2016-09-15 | United Silicon Carbide, Inc. | Trench vertical jfet with improved threshold voltage control |
| US20170148632A1 (en) * | 2014-09-24 | 2017-05-25 | Alpha And Omega Semiconductor Incorporated | Semiconductor device including superjunction structure formed using angled implant process |
| CN107302023A (zh) * | 2017-07-13 | 2017-10-27 | 深圳市金誉半导体有限公司 | 超结型沟槽功率mosfet器件及其制备方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313482B1 (en) | 1999-05-17 | 2001-11-06 | North Carolina State University | Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein |
| DE19943143B4 (de) * | 1999-09-09 | 2008-04-24 | Infineon Technologies Ag | Halbleiterbauelement für hohe Sperrspannungen bei gleichzeitig niedrigem Einschaltwiderstand und Verfahren zu dessen Herstellung |
| US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| US6573558B2 (en) | 2001-09-07 | 2003-06-03 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-layered extended drain structure |
| US7052982B2 (en) | 2003-12-19 | 2006-05-30 | Third Dimension (3D) Semiconductor, Inc. | Method for manufacturing a superjunction device with wide mesas |
| US7465986B2 (en) * | 2004-08-27 | 2008-12-16 | International Rectifier Corporation | Power semiconductor device including insulated source electrodes inside trenches |
| KR20090116702A (ko) | 2007-01-09 | 2009-11-11 | 맥스파워 세미컨덕터 인크. | 반도체 디바이스 |
| US8815744B2 (en) | 2008-04-24 | 2014-08-26 | Fairchild Semiconductor Corporation | Technique for controlling trench profile in semiconductor structures |
| US8373208B2 (en) | 2009-11-30 | 2013-02-12 | Alpha And Omega Semiconductor Incorporated | Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode |
| US8372717B2 (en) | 2009-12-28 | 2013-02-12 | Force Mos Technology Co., Ltd. | Method for manufacturing a super-junction trench MOSFET with resurf stepped oxides and trenched contacts |
| US8765609B2 (en) * | 2012-07-25 | 2014-07-01 | Power Integrations, Inc. | Deposit/etch for tapered oxide |
| US9564515B2 (en) | 2014-07-28 | 2017-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having super junction structure and method for manufacturing the same |
| JP6454447B2 (ja) | 2015-12-02 | 2019-01-16 | アーベーベー・シュバイツ・アーゲー | 半導体装置の製造方法 |
-
2020
- 2020-01-31 US US16/778,904 patent/US11316042B2/en active Active
-
2021
- 2021-03-19 JP JP2022545043A patent/JP7631353B2/ja active Active
- 2021-03-19 WO PCT/US2021/023142 patent/WO2021155386A1/en not_active Ceased
- 2021-03-19 CN CN202180011391.5A patent/CN115380387A/zh active Pending
- 2021-03-19 KR KR1020227026384A patent/KR102860640B1/ko active Active
- 2021-03-19 EP EP21747915.3A patent/EP4097763A4/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1234613A (zh) * | 1998-04-23 | 1999-11-10 | 国际整流器有限公司 | P沟道槽型金属氧化物半导体场效应晶体管结构 |
| US20100013010A1 (en) * | 2008-07-16 | 2010-01-21 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20100237416A1 (en) * | 2009-03-17 | 2010-09-23 | Alpha & Omega Semiconductor Incorporated | Bottom-drain ldmos power mosfet structure having a top drain strap |
| CN102709320A (zh) * | 2012-02-15 | 2012-10-03 | 中山大学 | 纵向导通的GaN基MISFET 器件及其制作方法 |
| US20140124851A1 (en) * | 2012-11-08 | 2014-05-08 | Infineon Technologies Austria Ag | Radiation-Hardened Power Semiconductor Devices and Methods of Forming Them |
| US20170148632A1 (en) * | 2014-09-24 | 2017-05-25 | Alpha And Omega Semiconductor Incorporated | Semiconductor device including superjunction structure formed using angled implant process |
| US20160268446A1 (en) * | 2015-03-10 | 2016-09-15 | United Silicon Carbide, Inc. | Trench vertical jfet with improved threshold voltage control |
| CN107302023A (zh) * | 2017-07-13 | 2017-10-27 | 深圳市金誉半导体有限公司 | 超结型沟槽功率mosfet器件及其制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20230062469A (ko) | 2023-05-09 |
| KR102860640B1 (ko) | 2025-09-15 |
| WO2021155386A1 (en) | 2021-08-05 |
| JP7631353B2 (ja) | 2025-02-18 |
| EP4097763A1 (en) | 2022-12-07 |
| US20210242338A1 (en) | 2021-08-05 |
| US11316042B2 (en) | 2022-04-26 |
| JP2024529567A (ja) | 2024-08-07 |
| EP4097763A4 (en) | 2023-11-15 |
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|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |