CN115377040A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN115377040A
CN115377040A CN202210305873.8A CN202210305873A CN115377040A CN 115377040 A CN115377040 A CN 115377040A CN 202210305873 A CN202210305873 A CN 202210305873A CN 115377040 A CN115377040 A CN 115377040A
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China
Prior art keywords
protective film
semiconductor module
semiconductor
solder layer
plating layer
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Pending
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CN202210305873.8A
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English (en)
Inventor
原康文
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Publication of CN115377040A publication Critical patent/CN115377040A/zh
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Abstract

本发明提供一种半导体模块。在半导体模块中，期望防止应力集中。半导体模块具备：半导体芯片，其具有半导体基板以及设置于半导体基板的上方的金属电极；保护膜，其设置于金属电极的上方；镀覆层，其在金属电极的上方，至少一部分设置于与保护膜相同的高度的位置；焊料层，其设置于镀覆层的上方；以及引线框架，其设置于焊料层的上方，镀覆层设置于不与保护膜接触的范围。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
以往以来，已知搭载有IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)等半导体芯片的半导体模块。在这样的半导体模块中，引线框架等布线部件与半导体芯片经由作为接合材料的焊料而接合(例如，参照专利文献1-3)。
现有技术文献
专利文献
专利文献1：日本特开2006-245182号公报
专利文献2：国际公开第2019-244492号
专利文献3：日本特开2019-186510号公报
发明内容
技术问题
在半导体模块中，期望防止应力集中。
技术方案
为了解决上述课题，在本发明的一个方式中，提供一种半导体模块。半导体模块可以具备半导体芯片。半导体芯片可以具有半导体基板以及设置于半导体基板的上方的金属电极。半导体模块可以具备保护膜。保护膜可以设置于金属电极的上方。半导体模块可以具备镀覆层。镀覆层可以在金属电极的上方，其至少一部分设置于与保护膜相同的高度的位置。半导体模块可以具备焊料层。焊料层可以设置于镀覆层的上方。半导体模块可以具备引线框架。引线框架可以设置于焊料层的上方。镀覆层可以设置于不与保护膜接触的范围。
焊料层可以设置于不与保护膜接触的范围。焊料层的至少一部分可以设置于与保护膜相同的高度的位置。保护膜可以在高度方向上设置于比引线框架低的位置。
半导体芯片可以具备温度感测二极管。温度感测二极管可以设置于半导体基板的上方。半导体芯片可以具备感测布线。感测布线可以与温度感测二极管连接。保护膜可以覆盖温度感测二极管和感测布线。覆盖温度感测二极管或感测布线的保护膜可以与焊料层和镀覆层分离。
引线框架可以包括与半导体芯片连接的芯片连接部。芯片连接部可以在俯视时不与温度感测二极管和感测布线重叠。
芯片连接部可以在保护膜的上方覆盖保护膜。半导体模块可以在芯片连接部与保护膜之间具有空间。半导体模块可以在保护膜的上方，在焊料层与保护膜之间具有空间。芯片连接部可以具有向焊料层侧突起的多个突起部。
半导体芯片可以具有金属栅极流道。金属栅极流道可以设置于半导体基板的上方。覆盖金属栅极流道的保护膜可以与焊料层和镀覆层分离。
半导体模块可以在镀覆层与保护膜之间填充有弹性模量比保护膜的弹性模量小的填充材料。半导体模块可以在镀覆层与保护膜之间填充有填充材料，该填充材料与镀覆层或焊料层之间的线性膨胀系数的差异比保护膜与镀覆层或焊料层之间的线性膨胀系数的差异小。可以在镀覆层与保护膜之间填充有填充材料，该填充材料与金属电极之间的紧贴性比保护膜与金属电极之间的紧贴性高。
半导体模块可以具备封装树脂。封装树脂可以将半导体芯片和引线框架封装。填充材料可以是与封装树脂不同的材料。
可以在镀覆层与保护膜之间设置有焊料层。焊料层可以将与焊料层接触的镀覆层的角部覆盖。
应予说明，上述发明内容并没有列举本发明的全部特征。另外，这些特征组的子组合也能够另外成为发明。
附图说明
图1是示出本发明的一个实施方式的半导体模块100的一例的图。
图2是示出俯视时的半导体芯片40的栅极流道48、阱区以及焊盘区的配置的一例的图。
图3是示出俯视时的半导体芯片40的保护膜150的配置的一例的图。
图4是示出比较例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的一例的图。
图5是示出图4的a-a截面处的半导体模块100的一例的图。
图6是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的一例的图。
图7是示出图6的b-b截面处的半导体模块100的一例的图。
图8是示出图6的c-c截面处的半导体模块100的一例的图。
图9是示出图6的b-b截面处的半导体模块100的另一例的图。
图10是示出图6的b-b截面处的半导体模块100的另一例的图。
图11是示出图6的b-b截面处的半导体模块100的另一例的图。
图12是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。
图13是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。
图14是示出图13的d-d截面处的半导体模块100的一例的图。
图15是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。
图16是示出图15的e-e截面处的半导体模块100的一例的图。
符号说明
10：树脂壳体；11：上表面；12：封装树脂；20：冷却部；21：绝缘基板；26：电路图案；30：焊料层；32：焊料层；36：镀覆层；37：角部；38：层间绝缘膜；40：半导体芯片；42：沟槽部；44：连接部；45：接触孔；47：金属栅极流道；48：栅极流道；50：栅极焊盘；52：金属电极；60：引线框架；62：芯片连接部；63：突起部；64：桥接部；66：电路图案连接部；68：脚部；94：空间；96：空间；100：半导体模块；102：端边；110：半导体基板；111：第一阱区；112：第二阱区；113：周边阱区；114：分割阱区；115：宽幅部；116：窄幅部；120：有源部；150：保护膜；160：填充材料；172：电流检测焊盘；174：阳极焊盘；176：阴极焊盘；178：温度感测二极管；180：感测布线；184：凹部
具体实施方式
以下，虽然通过发明的实施方式对本发明进行说明，但是以下的实施方式并不限定权利要求所涉及的发明。另外，实施方式中所说明的特征的全部组合未必是发明的技术方案所必须的。应予说明，在本说明书和附图中，对于实质上具有相同功能和结构的要素标注同一符号而省略重复说明，另外对与本发明没有直接关系的要素省略图示。另外，在一个附图中，有时针对具有相同功能和结构的要素代表性地标注符号，并且针对其他要素省略符号。
在本说明书中，将与半导体芯片的深度方向平行的方向上的一侧称为“上”，将另一侧称为“下”。在基板、层或其他部件的两个主面之中，将一个面称为上表面，将另一个面称为下表面。“上”、“下”的方向不限于重力方向或实际安装半导体模块时的方向。
在本说明书中，有时使用X轴、Y轴以及Z轴的直角坐标轴来说明技术事项。直角坐标轴只不过确定构成要素的相对位置，并不限定特定的方向。例如，Z轴并不限定表示相对于地面的高度方向。应予说明，+Z轴方向与-Z轴方向是彼此相反的方向。在不记载正负而记载为Z轴方向的情况下，是指与+Z轴和-Z轴平行的方向。在本说明书中，将与半导体基板的上表面和下表面平行的正交轴设为X轴和Y轴。另外，将与半导体基板的上表面和下表面垂直的轴设为Z轴。在本说明书中，有时将Z轴的方向称为深度方向。另外，在本说明书中，有时将包含X轴和Y轴且与半导体基板的上表面和下表面平行的方向称为水平方向。
在本说明书中，在称为“相同”或者“相等”的情况下，也可以包括具有因制造偏差等而引起的误差的情况。该误差例如在10％以内。
图1是示出本发明的一个实施方式的半导体模块100的一例的图。半导体模块100可以作为变换器等电力变换装置而发挥功能。半导体模块100具备一个以上的绝缘基板21。在绝缘基板21的任一面设置有预先设定的电路图案26，在绝缘基板21的另一面设置有冷却部20。电路图案26可以通过将铜板或铝板、或者对这些材料实施了镀覆而得的板直接接合于氮化硅陶瓷或氮化铝陶瓷等绝缘基板21或经由钎料层接合于氮化硅陶瓷或氮化铝陶瓷等绝缘基板21而构成。
在电路图案26载置有一个以上的半导体芯片40。在图1的例子中，载置有一个半导体芯片40。焊料层30将半导体芯片40与电路图案26接合。焊料层30可以是与后述的焊料层32相同的材料。半导体芯片40被包围绝缘基板21的树脂壳体10和填充于树脂壳体10的封装树脂12这样的树脂封装保护。应予说明，也可以不设置树脂壳体10，而利用封装树脂12的传递模塑等来保护半导体芯片40等。
半导体芯片40可以包括IGBT、FWD(Free Wheel Diode：续流二极管)等二极管和将它们组合而成的RC(Reverse Conducting：反向导通)-IGBT、以及MOS晶体管等。
本例的半导体芯片40是在上表面和下表面形成有金属电极(例如，发射电极和集电电极)的纵向型的芯片。半导体芯片40通过形成于下表面的金属电极与电路图案26连接，并通过形成于上表面的金属电极与布线部件(在本例中为引线框架60)连接。应予说明，半导体芯片40并不限于纵向型的芯片。半导体芯片40也可以在上表面具有通过导线等与电路图案26连接的金属电极。
在本例中，在半导体芯片40的金属电极的上方设置有镀覆层36。金属电极经由镀覆层36与布线部件连接。作为一例，镀覆层36为Ni镀覆。通过设置镀覆层36，能够改善半导体芯片40的金属电极与作为接合部件的焊料层的润湿性，并提高布线部件的接合性。镀覆层36可以设置于金属电极的整个上表面，镀覆层36也可以设置于金属电极的大部分上表面。
树脂壳体10以包围收容半导体芯片40的空间94的方式设置。绝缘基板21设置于树脂壳体10的下方。应予说明，空间94可以是绝缘基板21的上方的区域且被树脂壳体10包围的区域。
在本例中，树脂壳体10由能够通过注塑成型而形成的热固化型树脂、或者能够通过UV成型而形成的紫外线固化型树脂等树脂而成形。该树脂可以包含选自例如聚苯硫醚(PPS)树脂、聚对苯二甲酸丁二醇酯(PBT)树脂、聚酰胺(PA)树脂、丙烯腈丁二烯苯乙烯(ABS)树脂以及丙烯酸树脂等的一种或多种高分子材料。
冷却部20在内部包含水等制冷剂。冷却部20经由绝缘基板21等对半导体芯片40进行冷却。另外，也可以在冷却部20与绝缘基板21之间设置有散热板。冷却部20可以经由该散热板对半导体芯片40进行冷却。
半导体芯片40的上表面经由镀覆层36和作为接合部件的焊料层32连接于布线部件。本例的布线部件是引线框架60。引线框架60是由铜或铝等金属材料形成的部件。引线框架60的至少一部分表面可以被镍等镀覆。另外，引线框架60的至少一部分表面也可以被树脂等涂布。引线框架60可以具有板状的部分。板状是指对置地设置的两个主面的面积比其他面的面积大的形状。引线框架60至少与半导体芯片40连接的部分可以为板状。引线框架60可以通过将一张金属板弯折而形成。
引线框架60将半导体芯片40与电路图案26电连接。在引线框架60可以流通有主电流。在此，主电流是指在半导体芯片40流通的电流中的最大的电流。本例的引线框架60包括芯片连接部62、桥接部64、电路图案连接部66以及脚部68。芯片连接部62是与半导体芯片40的上表面连接的部分。电路图案连接部66是与电路图案26的上表面连接的部分。芯片连接部62和电路图案连接部66可以是与XY面大致平行的板状的部分。因此，芯片连接部62和电路图案连接部66可以是与半导体芯片40的上表面大致平行的板状的部分。应予说明，大致平行是指例如角度为10度以下的状态。
脚部68是沿Z轴方向延伸的部分。桥接部64经由脚部68将芯片连接部62和电路图案连接部66连接。桥接部64被设置为与电路图案26等导电部件分离。本例的桥接部64设置于电路图案26等的上方，并从芯片连接部62起以跨越电路图案26等的方式设置到电路图案连接部66为止。
在本例中，封装树脂12设置于树脂壳体10的内部。封装树脂12将半导体芯片40以及作为布线部件的引线框架60封装。即，封装树脂12以使半导体芯片40和引线框架60不露出的方式覆盖整个半导体芯片40和整个引线框架60。通过封装树脂12，能够保护半导体芯片40和引线框架60。
焊料层32形成于半导体芯片40的上表面与引线框架60的芯片连接部62的下表面之间，并将半导体芯片40与芯片连接部62机械连接且电连接。在本例中，焊料层32使用无铅焊料。无铅焊料以例如由锡-银-铜构成的合金、由锡-锌-铋构成的合金、由锡-铜构成的合金、由锡-银-铟-铋构成的合金中的至少任一种合金为主要成分。另外，焊料层32可以在侧面具有焊脚(fillet)。焊料层32也可以仅设置于半导体芯片40的上表面与引线框架60的芯片连接部62的下表面之间。
图2是示出俯视时的半导体芯片40的栅极流道48、阱区以及焊盘区的配置的一例的图。半导体芯片40具有半导体基板110。半导体基板110是由硅或化合物半导体等半导体材料形成的基板。半导体基板110在俯视时具有端边102。本例的半导体基板110具有在俯视时彼此相对的两组端边102。在图2中，示出了彼此相对的一组端边102-1和端边102-2。在图2中，将与端边102-1和端边102-2平行的方向设为X轴方向，将与端边102-1和端边102-2垂直的方向设为Y轴方向。
在半导体基板110设置有有源部120。在本例中，在半导体基板110设置有有源部120-1和有源部120-2。有源部120是在将半导体芯片40控制为导通状态的情况下，在半导体基板110的上表面与下表面之间沿深度方向流通有主电流的区域。因此，可以将图1中的阱区的内侧的区域设为有源部120。在有源部120可以设置有包括IGBT等晶体管元件的晶体管部。有源部120也可以设置有包括FWD等二极管元件的二极管部。有源部120可以是设置有晶体管部和二极管部中的至少一者的区域。有源部120也可以是在俯视时与上表面主电极重叠的区域。上表面主电极可以是设置于半导体基板110的上表面的上方的电极中的、俯视时的面积最大的电极。上表面主电极例如可以与晶体管部的发射区或源区电连接，也可以与二极管部的阳极区电连接。在图2的例子中，金属电极52是上表面主电极。
在半导体基板110设置有P型的阱区。阱区是浓度比晶体管部的基区或二极管部的阳极区的浓度高的P型区。基区是与栅电极对置地设置，并且在对栅电极施加了预先设定的栅极电压的情况下，在与栅电极对置的部分形成有沟道的P型区。半导体芯片40具有第一阱区111和第二阱区112。第一阱区111和第二阱区112在俯视时夹持有源部120而设置。第一阱区111和第二阱区112在预先设定的方向(在图2中为Y轴方向)上夹持有源部120而设置。两个阱区夹持有源部120是指在俯视时将两个阱区连结的任一条直线都通过有源部120的情况。
第一阱区111可以设置于端边102-1的附近。即，第一阱区111与端边102-1之间的距离比第一阱区111与端边102-2之间的距离小。第二阱区112可以设置于端边102-2的附近。即，第二阱区112与端边102-2之间的距离比第二阱区112与端边102-1之间的距离小。
本例的第一阱区111在Y轴方向上设置于有源部120与端边102-1之间。在第一阱区111与端边102-1之间不设置有源部120。即，第一阱区111设置于有源部120的Y轴方向上的端部与端边102-1之间。
本例的第二阱区112在Y轴方向上设置于有源部120与端边102-2之间。在第二阱区112与端边102-2之间不设置有源部120。即，第二阱区112设置于有源部120的Y轴方向上的端部与端边102-2之间。
第一阱区111和第二阱区112在X轴方向上可以设置于端边102-1和端边102-2的包括中央位置Xc的范围。第一阱区111可以在X轴方向上被有源部120夹持。第二阱区112可以在X轴方向上被有源部120夹持。第二阱区112可以比第一阱区111在X轴方向上设置于更宽的范围。
半导体芯片40可以具有在俯视时包围有源部120而设置的周边阱区113。周边阱区113可以与半导体基板110的各端边平行地设置。本例的周边阱区113是在俯视时包围有源部120的环状的区域。周边阱区113的垂直于各端边的方向上的宽度可以为恒定。
本例的第一阱区111和第二阱区112比周边阱区113更向有源部120的中央侧突出。在其他的例子中，第一阱区111和第二阱区112中的至少一者可以设置于周边阱区113与半导体基板110的端边102之间。在该情况下，第一阱区111和第二阱区112可以从周边阱区113向端边102一侧突出。
半导体芯片40可以具有在俯视时分割有源部120的分割阱区114。可以通过包括分割阱区114在内的阱区将有源部120分割为有源部120-1和有源部120-2。分割阱区114在预先设定的阱长度方向上具有长度。分割阱区114沿阱长度方向延伸而横穿有源部120。分割阱区114的阱长度方向为Y轴方向。
分割阱区114可以设置于第一阱区111与第二阱区112之间。分割阱区114的长度方向的一端可以与第一阱区111连接，另一端可以与第二阱区112连接。分割阱区114可以设置于与有源部120的中央重叠的区域。
分割阱区114可以具有在俯视时与阱长度方向垂直的方向(在本例中为X轴方向)上的宽度比其他部分更宽的宽幅部115。宽幅部115也设置于第一阱区111与第二阱区112之间。宽幅部115可以设置于与有源部120的中心重叠的区域。宽幅部115可以设置于分割阱区114的包括阱长度方向上的中央在内的区域。
在分割阱区114中，将在俯视时与阱长度方向垂直的方向(在本例中为X轴方向)上的宽度比宽幅部115的宽度窄的部分设为窄幅部116。分割阱区114具有设置于第一阱区111侧的窄幅部116-1和设置于第二阱区112侧的窄幅部116-2。宽幅部115的阱长度方向上的端部分别与窄幅部116-1和窄幅部116-2连接。
本例的半导体芯片40具有栅极焊盘50、电流检测焊盘172、阳极焊盘174以及阴极焊盘176等控制电极。栅极焊盘50设置于第一阱区111的上方。电流检测焊盘172、阳极焊盘174以及阴极焊盘176设置于第二阱区112的上方。
温度感测二极管178是由多晶硅等半导体材料形成的PN结二极管。温度感测二极管178设置于宽幅部115的上方。即，温度感测二极管178的至少一部分与宽幅部115的至少一部分重叠。本例的温度感测二极管178的俯视时的一半以上的区域与宽幅部115重叠。温度感测二极管178也可以整体与宽幅部115重叠。
金属电极52和各控制电极是包含铝等金属的电极。在金属电极52与半导体基板110之间、以及各控制电极与半导体基板110之间设置有层间绝缘膜。金属电极52与半导体基板110、以及各控制电极与半导体基板110经由设置于该层间绝缘膜的接触孔而连接。在图2中，省略了层间绝缘膜和接触孔。
金属电极52设置于有源部120的上方。金属电极52经由上述接触孔与有源部120连接。在金属电极52的上表面连接有布线部件，并被施加预先设定的发射极电压。金属电极52和各控制电极在俯视时彼此分离地设置。在各控制电极的上表面连接有导线等。金属电极52可以分别针对有源部120-1和有源部120-2而设置。另外，金属电极52也与阱区连接(参照图5)。
在栅极焊盘50施加有预先设定的栅极电压。施加到栅极焊盘50的栅极电压通过后述的栅极流道48等而被供给到有源部120的晶体管部。栅极焊盘50设置于第一阱区111的上方。即，栅极焊盘50的至少一部分与第一阱区111的至少一部分重叠。本例的栅极焊盘50的俯视时的一半以上的区域与第一阱区111重叠。栅极焊盘50也可以整体与第一阱区111重叠。本例的栅极焊盘50可以设置于半导体芯片40的端边102-1的附近。即，栅极焊盘50设置于金属电极52与半导体芯片40的端边102-1之间，并在栅极焊盘50与端边102-1之间不设置金属电极52。此外，栅极焊盘50可以设置于半导体芯片40的端边102-1的包括X轴方向上的中央位置Xc的区域。
电流检测焊盘172与电流检测部(未图示)连接，并检测流过电流检测部的电流。阳极焊盘174经由感测布线(参照图5)与温度感测二极管178的阳极区连接。阴极焊盘176经由感测布线(参照图5)与温度感测二极管178的阴极区连接。应予说明，感测布线可以设置于宽幅部115和窄幅部116-1的上方。
电流检测焊盘172、阳极焊盘174以及阴极焊盘176设置于第二阱区112的上方。针对电流检测焊盘172、阳极焊盘174以及阴极焊盘176的各控制电极，控制电极的至少一部分与第二阱区112的至少一部分重叠。本例的电流检测焊盘172、阳极焊盘174以及阴极焊盘176的俯视时的一半以上的区域与第二阱区112重叠。电流检测焊盘172、阳极焊盘174以及阴极焊盘176也可以整体与第二阱区112重叠。本例的电流检测焊盘172、阳极焊盘174以及阴极焊盘176的各控制电极可以设置于半导体芯片40的端边102-2的附近。即，电流检测焊盘172、阳极焊盘174以及阴极焊盘176的各控制电极设置于金属电极52与半导体芯片40的端边102-2之间，并且在各控制电极与端边102-2之间不设置金属电极52。此外，各控制电极可以设置于半导体芯片40的端边102-2的包含X轴方向上的中央位置Xc的区域。本例的栅极焊盘50、电流检测焊盘172、阳极焊盘174以及阴极焊盘176的各控制电极可以分别设置于半导体芯片40的相对的端边102-1、102-2。而且，本例的栅极焊盘50、电流检测焊盘172、阳极焊盘174以及阴极焊盘176的各控制电极可以隔着分割阱区114对置而设置。
在图2中，利用虚线表示栅极流道48。在本例中，栅极流道48是由添加有杂质的多晶硅形成的布线。栅极流道48可以由金属等导电材料形成。栅极流道48将施加到栅极焊盘50的栅极电压向设置于有源部120的晶体管部供给。栅极流道48可以设置于阱区的上方。
半导体芯片40可以具有在俯视时包围有源部120而设置的栅极流道48-3。栅极流道48-3可以设置于周边阱区113的上方。栅极流道48-3可以与后述的金属栅极流道连接。
半导体芯片40可以具有在俯视时包围第一阱区111的至少一部分区域的栅极流道48-1。栅极流道48-1可以在俯视时沿着第一阱区111的端边而设置。栅极流道48-1可以具有与第一阱区111的各端边平行的部分。
半导体芯片40可以具有在俯视时包围第二阱区112的至少一部分区域的栅极流道48-2。栅极流道48-2可以在俯视时沿着第二阱区112的端边而设置。栅极流道48-2可以具有与第二阱区112的各端边平行的部分。
半导体芯片40可以具有在俯视时设置于窄幅部116的上方的栅极流道48-4。半导体芯片40可以具有在俯视时包围宽幅部115的至少一部分区域的栅极流道48-5。栅极流道48-5可以在俯视时沿着宽幅部115的端边而设置。栅极流道48-5可以具有与宽幅部115的各端边平行的部分。栅极流道48-4和栅极流道48-5可以在俯视时分割有源部120。
半导体芯片40可以在周边阱区113与半导体基板110的端边之间具备边缘终端结构部。边缘终端结构部缓和半导体基板110的上表面侧的电场集中。边缘终端结构部例如具有包围有源部120而设置为环状的保护环、场板、降低表面电场以及将它们组合而成的结构。在本说明书中，省略了边缘终端结构部。
图3是示出俯视时的半导体芯片40的保护膜150的配置的一例的图。在图3中，利用斜阴影线表示配置有保护膜150的区域。保护膜150可以设置于金属电极52的上方和半导体基板110的上方。保护膜150可以与金属电极52的上表面接触。通过设置保护膜150，能够保护半导体芯片40的上表面。作为一例，保护膜150是聚酰亚胺膜。
半导体芯片40可以具有覆盖第一阱区111的保护膜150-1。保护膜150-1可以使栅极焊盘50的上表面的一部分露出。由此，能够在栅极焊盘50的上表面连接导线等。
半导体芯片40可以具有覆盖第二阱区112的保护膜150-2。保护膜150-2可以使电流检测焊盘172、阳极焊盘174以及阴极焊盘176的上表面的一部分露出。由此，能够在电流检测焊盘172、阳极焊盘174以及阴极焊盘176的上表面连接导线等。
半导体芯片40可以具有覆盖周边阱区113的保护膜150-3。保护膜150-3可以覆盖整个周边阱区113。半导体芯片40可以具有覆盖分割阱区114的保护膜150-4和保护膜150-7。可以利用保护膜150-4和保护膜150-7来覆盖整个分割阱区114。在本例中，保护膜150-4覆盖整个宽幅部115，保护膜150-7覆盖整个窄幅部116。
保护膜150使金属电极52的上表面的一部分露出。由此，能够在金属电极52的上表面容易地连接导线等。
半导体芯片40可以具有将半导体基板110的上表面分割的保护膜150-5和保护膜150-6。保护膜150-5和保护膜150-6可以被设置为沿X轴方向横穿半导体基板110的上表面。
图4是示出比较例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的一例的图。在图4中，示出了半导体芯片40中的引线框架60的芯片连接部62的配置的一例。在图4中，利用虚线表示与芯片连接部62重叠的保护膜150。另外，在图4中，用单点划线表示与芯片连接部62重叠的温度感测二极管178。
在本例中，芯片连接部62以在俯视时与保护膜150-4和保护膜150-7重叠的方式设置。因此，芯片连接部62在俯视时与温度感测二极管178和感测布线(在图4中未图示)重叠。
图5是示出图4的a-a截面处的半导体模块100的一例的图。a-a截面是XZ面的截面。在该截面中，半导体模块100具备焊料层32、镀覆层36、层间绝缘膜38、连接部44、栅极流道48-4、金属电极52、引线框架60的芯片连接部62、半导体基板110、保护膜150-7。在该截面中，省略了半导体基板110的下表面。
在半导体基板110的上表面11设置有沟槽部42。沟槽部42可以是栅极沟槽部。即，沟槽部42内的导电部可以与栅极焊盘50的控制电极电连接。沟槽部42可以具有绝缘膜。
在该截面中，在金属电极52与半导体基板110之间设置有层间绝缘膜38。另外，层间绝缘膜38具有接触孔45。金属电极52经由接触孔45与连接部44连接。
连接部44可以由与栅极流道48相同的材料形成。即，连接部44可以是由添加有杂质的多晶硅形成的布线。通过设置连接部44，能够将阱区(在本例中为分割阱区114的窄幅部116-2)与金属电极52电连接。
金属电极52设置于半导体基板110的上方。在本例中，金属电极52设置于层间绝缘膜38的上表面。
在该截面中，半导体模块100具备感测布线180。感测布线180-1将温度感测二极管178的阳极区与阳极焊盘174连接。感测布线180-2将温度感测二极管178的阴极区与阴极焊盘176连接。
感测布线180设置于半导体基板110的上方。在本例中，感测布线180设置于层间绝缘膜38的上表面。感测布线180的至少一部分可以设置于与金属电极52相同的高度的位置。
另外，虽然在该截面中图示了感测布线180，但是温度感测二极管178也可以设置于与感测布线180相同的高度的位置。即，温度感测二极管178可以设置于半导体基板110的上方。温度感测二极管178可以设置于层间绝缘膜38的上表面。温度感测二极管178的至少一部分可以设置于与金属电极52相同的高度的位置。
在该截面中，保护膜150-7设置于金属电极52的上方。保护膜150-7设置于感测布线180的上方。在本例中，保护膜150-7覆盖感测布线180。另外，在另一截面中，保护膜150-4可以设置于温度感测二极管178的上方。保护膜150-4可以覆盖温度感测二极管178。总之，保护膜150可以覆盖温度感测二极管178和感测布线180。保护膜150的厚度T1可以为1μm以上且20μm以下。
镀覆层36设置于金属电极52的上方。在本例中，镀覆层36设置于金属电极52的上表面。镀覆层36的至少一部分可以设置于与保护膜150相同的高度的位置。
焊料层32设置于镀覆层36的上方。在本例中，焊料层32设置于引线框架60的芯片连接部62与镀覆层36之间。另外，在图5中，焊料层32设置于保护膜150-7的上方。在本例中，焊料层32设置于引线框架60的芯片连接部62与保护膜150-7之间。引线框架60的芯片连接部62设置于焊料层32的上方。焊料层32的至少一部分可以设置于与保护膜150相同的高度的位置。另外，保护膜150在高度方向(Z轴方向)上设置于比引线框架60低的位置。在本例中，保护膜150设置于引线框架60的芯片连接部62的下方。
在本例中，存在焊料层32、镀覆层36以及保护膜150-7接触的点。将该点设为三重点G1。如果存在三重点G1，则因热而反复施加应力，而在三重点G1产生应力集中。因此，优选在半导体模块100中不设置三重点G1，防止应力集中。
图6是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的一例的图。在图6中，示出了半导体芯片40中的引线框架60的芯片连接部62的配置的一例。在图6中，将设置于有源部120-1的芯片连接部62设为芯片连接部62-1，并将设置于有源部120-2的芯片连接部62设为芯片连接部62-2。
图7是示出图6的b-b截面处的半导体模块100的一例的图。b-b截面是XZ面的截面。在该截面中，半导体模块100具备焊料层32、镀覆层36、层间绝缘膜38、连接部44、栅极流道48-4、金属电极52、引线框架60的芯片连接部62、半导体基板110、保护膜150-7。在该截面中，省略了半导体基板110的下表面。在该截面中，焊料层32、镀覆层36以及引线框架60的芯片连接部62的结构与图5的截面的结构不同。图7的除此以外的结构可以与图5相同。镀覆层36的至少一部分可以设置于与保护膜150相同的高度的位置。焊料层32的至少一部分可以设置于与保护膜150相同的高度的位置。
在本例中，镀覆层36设置于不与保护膜150接触的范围。在该截面中，镀覆层36不与保护膜150-7接触。镀覆层36与保护膜150-7分离。即，半导体模块100在镀覆层36与保护膜150-7之间具有空间96。通过使镀覆层36与保护膜150分离，从而不存在三重点。因此，能够防止由三重点所引起的应力集中。镀覆层36与保护膜150的最短距离D1可以为10μm以上且300μm以下。应予说明，在空间96内可以填充有上述封装树脂12。在本例中，省略了封装树脂12。
另外，在本例中，焊料层32设置于不与保护膜150接触的范围。在截面中，焊料层32不与保护膜150-7接触。焊料层32与保护膜150-7分离。即，半导体模块100在焊料层32与保护膜之间具有空间96。通过使焊料层32与保护膜150分离，从而不存在三重点。因此，能够防止由三重点所引起的应力集中。
在本例中，覆盖温度感测二极管178或感测布线180的保护膜150与焊料层32和镀覆层36分离。在该截面中，覆盖感测布线180的保护膜150-7与焊料层32和镀覆层36分离。另外，在另一截面(未示出)中，覆盖温度感测二极管178的保护膜150-4可以与焊料层32和镀覆层36分离。如此，由于覆盖温度感测二极管178或感测布线180的保护膜150与焊料层32和镀覆层36分离，所以在温度感测二极管178、感测布线180附近不存在三重点。因此，能够防止温度感测二极管178、感测布线180附近的应力集中。
另外，在图6中，芯片连接部62以在俯视时不与保护膜150-4和保护膜150-7重叠的方式设置。即，芯片连接部62能够以在俯视时不与温度感测二极管178和感测布线180重叠的方式设置。通过以在俯视时不与温度感测二极管178和感测布线180重叠的方式设置芯片连接部62，可以在保护膜150与芯片连接部62之间不设置焊料层32，能够将焊料层32设置于不与保护膜150接触的范围。应予说明，引线框架60的桥接部64、脚部68等也可以在俯视时与温度感测二极管178和感测布线180重叠。
另外，在图6中，芯片连接部62被分割为芯片连接部62-1和芯片连接部62-2。通过分割芯片连接部62，容易在栅极流道48-4附近填充封装树脂12，并且容易确保栅极流道48-4与感测布线180的绝缘性。
图8是示出图6的c-c截面处的半导体模块100的一例的图。c-c截面是XZ面的截面。在该截面中，半导体模块100具备镀覆层36、层间绝缘膜38、连接部44、金属栅极流道47、栅极流道48-3、金属电极52、引线框架60的芯片连接部62、半导体基板110以及保护膜150-3。在该截面中，省略了半导体基板110的下表面。在本例中，省略与图7相同的符号的说明。
金属栅极流道47设置于半导体基板110的上方。在本例中，金属栅极流道47设置于层间绝缘膜38的上表面。金属栅极流道47经由设置于层间绝缘膜38的接触孔45与栅极流道48-3电连接。金属栅极流道47可以与栅极焊盘50电连接，并被施加栅极电压。金属栅极流道47可以设置于周边阱区113的上方。
覆盖金属栅极流道47的保护膜150-3与镀覆层36分离。另外，覆盖金属栅极流道47的保护膜150-3与焊料层32(在图8中未图示)分离。通过使覆盖金属栅极流道47的保护膜150-3与镀覆层36和焊料层32分离，从而在金属栅极流道47附近不存在三重点。因此，能够防止金属栅极流道47附近的应力集中。
图9是示出图6的b-b截面处的半导体模块100的另一例的图。图9的b-b截面与图7的b-b截面的不同之处在于，在镀覆层36与保护膜150之间设置有填充材料160。图9的除此以外的结构可以与图7相同。
在本例中，在镀覆层36与保护膜150之间设置有填充材料160。在镀覆层36与保护膜150之间填充有填充材料160。另外，填充材料160可以设置于焊料层32与保护膜150之间。填充材料160可以设置于比引线框架60的芯片连接部62靠下侧的位置。这样的结构也能够防止三重点的产生。
填充材料160优选为比保护膜150更接近镀覆层36和焊料层32的材质。例如，填充材料160的弹性模量可以小于保护膜150的弹性模量。通过使填充材料160的弹性模量比保护膜150的弹性模量小，从而不易产生应力集中。在该情况下，作为一例，填充材料160为硅酮树脂。更优选地，为硅酮凝胶。
另外，对于填充材料160的线性膨胀系数而言，与保护膜150的线性膨胀系数相比，可以使填充材料160与镀覆层36之间的线性膨胀系数的差异更小。对于填充材料160的线性膨胀系数而言，与保护膜150的线性膨胀系数相比，可以使填充材料160的线性膨胀系数与焊料层32的线性膨胀系数之间的线性膨胀系数的差异更小。线性膨胀系数是表示物体的长度因温度上升而膨胀的比例的系数。与保护膜150的线性膨胀系数相比，通过使填充材料160的线性膨胀系数与镀覆层36或焊料层32的线性膨胀系数之间的线性膨胀系数的差异更小，从而使应力集中难以产生。在该情况下，作为一例，填充材料160是调整了无机填料的添加量而得的硅酮树脂和/或环氧树脂。
填充材料160与金属电极52之间的紧贴性可以比保护膜150与金属电极52之间的紧贴性高。通过提高填充材料160与金属电极52之间的紧贴性，从而能够防止保护膜150从金属电极52剥离。在该情况下，作为一例，填充材料160是调整了组成而得的硅酮树脂和/或环氧树脂。
填充材料160可以是与封装树脂12不同的材料。例如，封装树脂12优选为与半导体芯片40之间的线性膨胀系数的差异小的材料。另一方面，填充材料160优选为与镀覆层36或焊料层32之间的线性膨胀系数的差异小的材料。因此，填充材料160可以是线性膨胀系数比封装树脂12的线性膨胀系数大的材料。
封装树脂12为了减小热膨胀系数而增多无机填料的添加量，因此，封装树脂12的弹性模量有变大的倾向。因此，优选填充材料160的弹性模量比封装树脂12的弹性模量小。
另外，封装树脂12由于增多了无机填料的添加量，所以存在其与金属电极52之间的紧贴性变低的倾向。因此，优选填充材料160与金属电极52之间的紧贴性比封装树脂12与金属电极52之间的紧贴性高。
作为一例，封装树脂12是添加了50％体积以上且95％体积以下的无机填料而得的环氧树脂。应予说明，填充材料160也可以是与封装树脂12不同的材料。
图10是示出图6的b-b截面处的半导体模块100的另一例的图。图10的b-b截面与图7的b-b截面的不同之处在于，在镀覆层36与保护膜150之间设置有焊料层32。图10的除此以外的结构可以与图7相同。
在本例中，焊料层32设置于镀覆层36与保护膜150-7之间。另外，镀覆层36的侧面被焊料层32覆盖。在本例中，焊料层32将与焊料层32接触的镀覆层36的角部37覆盖。镀覆层36的角部37是镀覆层36的上表面与侧面交叉的部分。这样的结构也能够防止三重点的产生，并防止应力集中。应予说明，在本例中，焊料层32与保护膜150分离，但是焊料层32也可以与保护膜150接触。即使在焊料层32与保护膜150接触的情况下，也能够防止三重点的产生。
图11是示出图6的b-b截面处的半导体模块100的另一例的图。对于图11的b-b截面而言，焊料层32的结构与图10的b-b截面的焊料层32的结构不同。图11的除此以外的结构可以与图10相同。
在本例中，与图10同样地，焊料层32设置于镀覆层36与保护膜150-7之间。在本例中，与图10不同的是镀覆层36的侧面的一部分露出。即，镀覆层36的整体未被焊料层32覆盖。在本例中，焊料层32也覆盖与焊料层32接触的镀覆层36的角部37。这样的结构也能够防止三重点的产生，防止应力集中。
图12是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。图12的芯片连接部62的结构与图6的结构不同。图12的除此以外的结构可以与图6相同。
在本例中，芯片连接部62分别具有凹部184。凹部184可以沿着保护膜150的形状而设置。由于芯片连接部62具有凹部184，所以能够使保护膜150与焊料层32分离，能够防止三重点的产生。
图13是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。在图13中，示出了半导体芯片40中的引线框架60的芯片连接部62的配置的另一例。图13的俯视时的半导体芯片40、芯片连接部62的配置可以与图4的俯视时的半导体芯片40、芯片连接部62的配置相同。
图14是示出图13的d-d截面处的半导体模块100的一例的图。d-d截面是XZ面的截面。在该截面中，半导体模块100具备焊料层32、镀覆层36、层间绝缘膜38、连接部44、栅极流道48-4、金属电极52、引线框架60的芯片连接部62、半导体基板110、保护膜150-7。在该截面中，省略了半导体基板110的下表面。在该截面中，引线框架60的芯片连接部62的结构与图7的截面的结构不同。图14的除此以外的结构可以与图7相同。
在该截面中，镀覆层36也不与保护膜150-7接触。镀覆层36与保护膜150-7分离。即，半导体模块100在镀覆层36与保护膜150-7之间具有空间96。通过使镀覆层36与保护膜150分离，从而不存在三重点。因此，能够防止由三重点所引起的应力集中。镀覆层36与保护膜150的最短距离D1可以为10μm以上且300μm以下。
另外，在本例中，引线框架60的芯片连接部62设置于保护膜150-7的上方。芯片连接部62在保护膜150-7的上方覆盖保护膜150-7。另外，半导体模块100在芯片连接部62与保护膜150-7之间具有空间96。在本例中，在芯片连接部62和保护膜150-7之间未设置焊料层32。这样的结构也能够使镀覆层36与保护膜150分离，能够防止因三重点所引起的应力集中。
另外，在图13中，与图6不同的是芯片连接部62未被分割。由于不分割芯片连接部62，所以难以产生有源部120-1和有源部120-2的电流不平衡。另外，能够增大芯片连接部62的面积，并能够抑制因在引线框架60流通的电流所引起的发热。
图15是示出实施例的半导体模块100的俯视时的半导体芯片40、芯片连接部62的配置的另一例的图。在图15中，示出了半导体芯片40中的引线框架60的芯片连接部62的配置的另一例。图15与图13的不同之处在于，芯片连接部62具有突起部63。图15的除此以外的结构可以与图13相同。在图15中，利用虚线表示突起部63的配置。
芯片连接部62可以具有多个突起部63。在本例中，芯片连接部62具有四个突起部63。突起部63可以向焊料层32侧突起。在本例中，突起部63向-Z轴方向突起。优选整个突起部63设置于发射电极52的上方。
图16是示出图15的e-e截面处的半导体模块100的一例的图。e-e截面是XZ面的截面。在该截面中，半导体模块100具备焊料层32、镀覆层36、层间绝缘膜38、连接部44、栅极流道48-4、金属电极52、引线框架60的芯片连接部62、半导体基板110、保护膜150-7。在该截面中，省略了半导体基板110的下表面。在该截面中，焊料层32和引线框架60的芯片连接部62的结构与图14的截面的结构不同。图16的除此以外的结构可以与图14相同。
在本例中，与图14同样地，引线框架60的芯片连接部62也设置于保护膜150-7的上方。芯片连接部62在保护膜150-7的上方覆盖保护膜150-7。另外，半导体模块100在芯片连接部62与保护膜150-7之间具有空间96。
另外，在本例中，芯片连接部62具有向焊料层32侧突起的多个突起部63。因此，能够增大保护膜150-7与保护膜150-7的上方的芯片连接部62的部分的距离。因此，能够容易地确保空间96。
在图16中，在芯片连接部62与保护膜150-7之间设置有焊料层32。半导体模块100在保护膜150-7的上方，在焊料层32与保护膜150-7之间具有空间96。虽然由于突起部63，焊料层32向保护膜150-7的上方流动，但是在本例中确保了较宽的空间96，因此，能够防止三重点的产生，并且防止因三重点所引起的应力集中。
以上，虽然使用实施方式对本发明进行了说明，但是本发明的技术范围不限于上述实施方式所记载的范围。对本领域技术人员来说，能够对上述实施方式施加各种变更或改进是显而易见的。根据权利要求书的记载可知，施加了这样的变更或改良的方式也能够包括在本发明的技术范围内。

Claims (16)

1.一种半导体模块，其特征在于，具备：
半导体芯片，其具有半导体基板以及设置于所述半导体基板的上方的金属电极；
保护膜，其设置于所述金属电极的上方；
镀覆层，其在所述金属电极的上方，至少一部分设置于与所述保护膜相同的高度的位置；
焊料层，其设置于所述镀覆层的上方；以及
引线框架，其设置于所述焊料层的上方，
所述镀覆层设置于不与所述保护膜接触的范围。
2.根据权利要求1所述的半导体模块，其特征在于，
所述焊料层设置于不与所述保护膜接触的范围。
3.根据权利要求1或2所述的半导体模块，其特征在于，
所述焊料层的至少一部分设置于与所述保护膜相同的高度的位置。
4.根据权利要求1至3中任一项所述的半导体模块，其特征在于，
所述保护膜在高度方向上设置于比所述引线框架低的位置。
5.根据权利要求1至4中任一项所述的半导体模块，其特征在于，
所述半导体芯片还具有：
温度感测二极管，其设置于所述半导体基板的上方；以及
感测布线，其与所述温度感测二极管连接，
所述保护膜覆盖所述温度感测二极管和所述感测布线，
覆盖所述温度感测二极管或所述感测布线的所述保护膜与所述焊料层和所述镀覆层分离。
6.根据权利要求5所述的半导体模块，其特征在于，
所述引线框架包括与所述半导体芯片连接的芯片连接部，
所述芯片连接部在俯视时不与所述温度感测二极管和所述感测布线重叠。
7.根据权利要求1至5中任一项所述的半导体模块，其特征在于，
所述引线框架包括与所述半导体芯片连接的芯片连接部，
所述芯片连接部在所述保护膜的上方覆盖所述保护膜，
所述半导体模块在所述芯片连接部与所述保护膜之间具有空间。
8.根据权利要求7所述的半导体模块，其特征在于，
所述半导体模块在所述保护膜的上方，在所述焊料层与所述保护膜之间具有空间。
9.根据权利要求8所述的半导体模块，其特征在于，
所述芯片连接部具有向所述焊料层侧突起的多个突起部。
10.根据权利要求1至9中任一项所述的半导体模块，其特征在于，
所述半导体芯片还具有设置于所述半导体基板的上方的金属栅极流道，
覆盖所述金属栅极流道的所述保护膜与所述焊料层和所述镀覆层分离。
11.根据权利要求1至10中任一项所述的半导体模块，其特征在于，
所述半导体模块在所述镀覆层与所述保护膜之间填充有填充材料，所述填充材料的弹性模量比所述保护膜的弹性模量小。
12.根据权利要求1至10中任一项所述的半导体模块，其特征在于，
所述半导体模块在所述镀覆层与所述保护膜之间填充有填充材料，所述填充材料与所述镀覆层或所述焊料层之间的线性膨胀系数的差异比所述保护膜与所述镀覆层或所述焊料层之间的线性膨胀系数的差异小。
13.根据权利要求1至10中任一项所述的半导体模块，其特征在于，
所述半导体模块在所述镀覆层与所述保护膜之间填充有填充材料，所述填充材料与所述金属电极之间的紧贴性比所述保护膜与所述金属电极之间的紧贴性高。
14.根据权利要求11至13中任一项所述的半导体模块，其特征在于，
所述半导体模块还具备将所述半导体芯片和所述引线框架封装的封装树脂，
所述填充材料是与所述封装树脂不同的材料。
15.根据权利要求1至14中任一项所述的半导体模块，其特征在于，
所述半导体模块在所述镀覆层与所述保护膜之间设置有所述焊料层。
16.根据权利要求15所述的半导体模块，其特征在于，
所述焊料层将与所述焊料层接触的所述镀覆层的角部覆盖。
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