CN115332263A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN115332263A CN115332263A CN202110525263.4A CN202110525263A CN115332263A CN 115332263 A CN115332263 A CN 115332263A CN 202110525263 A CN202110525263 A CN 202110525263A CN 115332263 A CN115332263 A CN 115332263A
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- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 22
- 238000003860 storage Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly discloses a manufacturing method of a semiconductor device, which comprises the following steps: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding grid in the groove; etching the first insulating layer to form a grid electrode area in the upper part of the groove; etching the semiconductor substrate and the shielding grid to increase the width of the grid region; forming an n-type charge storage region, a gate dielectric layer and a gate, wherein the n-type charge storage region is positioned in the semiconductor substrate and below the gate region; the gate dielectric layer and the gate are located in the gate region. The manufacturing method of the semiconductor device of the invention forms the grid electrode after forming the shielding grid, can make the grid electrode have wider width, thus can make the grid electrode be drawn out by the external electrode more easily, can make the n-type charge storage region locate under the grid region accurately at the same time.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a semiconductor device.
Background
The manufacturing method of the semiconductor device of the prior art includes: forming a first trench in a semiconductor substrate; forming an n-type charge storage region in the semiconductor substrate below the first trench; then forming a gate dielectric layer and a gate on the side wall of the first groove; and etching the semiconductor substrate to form a second trench, and forming a field oxide layer and a shielding gate in the second trench. In the manufacturing method of the semiconductor device in the prior art, on one hand, the grid is formed first and then the shielding grid is formed, so that the width of the grid is small and the grid is not easy to be led out by an external electrode; on the other hand, the n-type charge storage region is formed after the first trench is formed, and when the gate dielectric layer and the field oxide layer are formed later, the n-type charge storage region is diffused due to high temperature, so that the position of the n-type charge storage region is not easily controlled precisely.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device, so as to reduce the manufacturing risk of the semiconductor device.
To achieve the above object of the present invention, the present invention provides a method of manufacturing a semiconductor device, comprising:
forming a trench in the provided semiconductor substrate;
forming a first insulating layer and a shielding grid in the groove;
etching the first insulating layer, and forming a grid electrode area in the upper part of the groove;
etching the semiconductor substrate and the shielding grid to increase the width of the grid region;
forming an n-type charge storage region and a gate dielectric layer, wherein the n-type charge storage region is positioned in the semiconductor substrate and below the gate region, and the gate dielectric layer is positioned in the gate region;
and forming a gate in the gate region.
Optionally, forming an n-type charge storage region and a gate dielectric layer, where the n-type charge storage region is located in the semiconductor substrate and below the gate region, and the gate dielectric layer is located in the gate region, includes:
carrying out ion implantation to form an n-type charge storage region positioned below the grid electrode region in the semiconductor substrate;
and forming a gate dielectric layer in the gate region.
Optionally, forming an n-type charge storage region and a gate dielectric layer, where the n-type charge storage region is located in the semiconductor substrate and below the gate region, and the gate dielectric layer is located in the gate region, includes:
forming a gate dielectric layer in the gate region;
and carrying out ion implantation to form an n-type charge storage region positioned below the grid electrode region in the semiconductor substrate.
Optionally, the method for manufacturing a semiconductor device of the present invention further includes:
forming a p-type body region in the semiconductor substrate;
an n-type emitter region is formed within the p-type body region.
Optionally, the first insulating layer is silicon oxide.
Optionally, when the semiconductor substrate and the shielding gate are etched to increase the width of the gate region, an isotropic etching method is used for etching.
The manufacturing method of the semiconductor device provided by the invention is characterized in that the grid electrode is formed after the shielding grid is formed, the grid electrode can have wider width, so that the grid electrode can be led out by an external electrode more easily, meanwhile, the n-type charge storage region is formed after the first insulating layer is formed, the diffusion times of the n-type charge storage region in the subsequent process can be reduced, the n-type charge storage region is accurately positioned below the grid electrode, and the device has smaller forward conduction voltage drop and shorter turn-off time under the same breakdown voltage.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments.
Fig. 1 to 7 are schematic cross-sectional structures of main structures in a manufacturing process of one embodiment of a method for manufacturing a semiconductor device provided by the present invention.
Detailed Description
The technical solution of the present invention will be fully described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 1 to 7 are schematic cross-sectional structures of main structures in a manufacturing process of one embodiment of a method for manufacturing a semiconductor device provided by the present invention.
First, as shown in fig. 1, trenches 30 are formed in a semiconductor substrate 20, the number of trenches 30 is determined by the specific specification of the semiconductor device to be designed, and only two trenches 30 are illustrated in the embodiment of the present invention. The semiconductor substrate 20 is typically a silicon substrate including a p-type substrate and an n-type epitaxial layer located over the p-type substrate. The process of forming the trench 30 includes: a hard mask layer is formed over the semiconductor substrate 20, then the position of the trench 30 is defined by a photolithography process, then the hard mask layer 30 is etched, and the semiconductor substrate 20 is continuously etched, so that the trench 30 is formed in the semiconductor substrate 20, and then the hard mask layer is removed.
Next, as shown in fig. 2, a first insulating layer 21 is formed in the trench, and then a first conductive layer is deposited and etched back to form a shield gate 22 in the trench. The first insulating layer 21 is preferably silicon oxide formed by thermal oxidation, deposition or a combination of thermal oxidation and deposition, and the shield grid 22 is preferably conductive polysilicon.
Next, as shown in fig. 3, the first insulating layer 21 is etched, and a gate region 31 is formed in an upper portion of the trench, the gate region 31 being interposed between the semiconductor substrate 20 and the shield gate 22.
Next, as shown in fig. 4, the semiconductor substrate 20 and the shield gate 21 are etched to increase the width of the gate region 31, and the semiconductor substrate 20 and the shield gate 21 are preferably etched by an isotropic etching method without an additional photolithography process.
Next, as shown in fig. 5, an n-type charge storage region 24 and a gate dielectric layer 23 are formed, wherein the n-type charge storage region 24 is located in the semiconductor substrate 20 and below the gate region 31, and the gate dielectric layer 23 is located in the gate region 31. Further, the n-type charge storage region 24 and the gate dielectric layer 23 are formed, the n-type charge storage region 24 may be formed first, and then the gate dielectric layer 23 may be formed. Specifically, ion implantation is performed to form an n-type charge storage region 24 under the gate region 31 in the semiconductor substrate 20, and then a gate dielectric layer 23 is formed in the gate region 31, where the gate dielectric layer 23 is usually formed by a thermal oxidation process, and at this time, the n-type charge storage region 24 is diffused to increase the area of the n-type charge storage region. Since the n-type charge storage region 24 is formed after the first insulating layer 21, the n-type charge storage region 24 is not affected by the thermal oxidation process when the first insulating layer 21 is formed, so that the position of the n-type charge storage region 24 can be more accurately controlled to be located below the gate region, and the device has smaller forward on-voltage drop and shorter off-time under the same breakdown voltage.
Optionally, the n-type charge storage region 24 may also be formed after the gate dielectric layer 23 is formed, at this time, the gate dielectric layer 23 is formed in the gate region 31, the gate dielectric layer 23 is usually formed through a thermal oxidation process, then ion implantation is performed, and the n-type charge storage region 24 located below the gate region 31 is formed in the semiconductor substrate 20, and under the influence of the gate dielectric layer 23, the energy of the ion implantation needs to be controlled. Since the gate dielectric layer 23 is formed first and then the n-type charge storage region 24 is formed, the formation region of the n-type charge storage region 24 is not affected by the preparation process of the gate dielectric layer 23, the n-type charge storage region 24 can be controlled to be accurately positioned below the gate region 31, and the device has smaller forward conduction voltage drop and shorter turn-off time under the same breakdown voltage.
Next, as shown in fig. 6, a gate 25 is formed in the gate region, and the specific forming process is: a conductive layer, such as conductive polysilicon, is deposited and then etched back to form gate 25 in the gate region.
Next, as shown in fig. 7, a p-type body region 26 is formed in semiconductor substrate 20, and an n-type emitter region 27 is formed in p-type body region 26.
Finally, the semiconductor device can be obtained according to conventional processes such as contact hole layer and metal layer.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.
Claims (6)
1. A method for manufacturing a semiconductor device, comprising:
forming a groove in the provided semiconductor substrate;
forming a first insulating layer and a shielding grid in the groove;
etching the first insulating layer, and forming a grid electrode area in the upper part of the groove;
etching the semiconductor substrate and the shielding grid to increase the width of the grid region;
forming an n-type charge storage region and a gate dielectric layer, wherein the n-type charge storage region is positioned in the semiconductor substrate and below the gate region, and the gate dielectric layer is positioned in the gate region;
and forming a gate in the gate region.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming an n-type charge storage region and a gate dielectric layer, the n-type charge storage region being located within the semiconductor substrate and below the gate region, the gate dielectric layer being located within the gate region, comprises:
carrying out ion implantation to form an n-type charge storage region positioned below the grid electrode region in the semiconductor substrate;
and forming a gate dielectric layer in the gate region.
3. The method of manufacturing a semiconductor device according to claim 1, wherein forming an n-type charge storage region and a gate dielectric layer, the n-type charge storage region being located within the semiconductor substrate and below the gate region, the gate dielectric layer being located within the gate region, comprises:
forming a gate dielectric layer in the gate region;
and carrying out ion implantation to form an n-type charge storage region below the gate region in the semiconductor substrate.
4. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a p-type body region in the semiconductor substrate;
an n-type emitter region is formed within the p-type body region.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating layer is silicon oxide.
6. The method for manufacturing a semiconductor device according to claim 1, wherein when the semiconductor substrate and the shield gate are etched to increase the width of the gate region, the etching is performed by an isotropic etching method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110525263.4A CN115332263A (en) | 2021-05-11 | 2021-05-11 | Method for manufacturing semiconductor device |
| PCT/CN2021/131556 WO2022237112A1 (en) | 2021-05-11 | 2021-11-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110525263.4A CN115332263A (en) | 2021-05-11 | 2021-05-11 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115332263A true CN115332263A (en) | 2022-11-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110525263.4A Pending CN115332263A (en) | 2021-05-11 | 2021-05-11 | Method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115332263A (en) |
| WO (1) | WO2022237112A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3319215B2 (en) * | 1995-03-31 | 2002-08-26 | 株式会社豊田中央研究所 | Insulated gate semiconductor device and method of manufacturing the same |
| CN105932042B (en) * | 2016-04-26 | 2018-09-21 | 电子科技大学 | A kind of pair of division trench gate charge storage type IGBT and its manufacturing method |
| CN106098777A (en) * | 2016-06-22 | 2016-11-09 | 电子科技大学 | A kind of splitting bar accumulation type DMOS device |
| CN110137249A (en) * | 2018-02-09 | 2019-08-16 | 苏州东微半导体有限公司 | IGBT power device and its manufacturing method |
| US20210320202A1 (en) * | 2020-04-10 | 2021-10-14 | Nami MOS CO., LTD. | Super Shielded Gate Trench MOSFET Having Superjunction Structure |
| CN112133759B (en) * | 2020-11-25 | 2021-02-05 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device having a shielded gate trench structure and method of manufacturing the same |
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2021
- 2021-05-11 CN CN202110525263.4A patent/CN115332263A/en active Pending
- 2021-11-18 WO PCT/CN2021/131556 patent/WO2022237112A1/en active Application Filing
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| Publication number | Publication date |
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| WO2022237112A1 (en) | 2022-11-17 |
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