CN115295430B - Flip-chip bonding surface encapsulation structure, flip-chip bonding surface encapsulation process and semiconductor device - Google Patents
Flip-chip bonding surface encapsulation structure, flip-chip bonding surface encapsulation process and semiconductor device Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
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Abstract
The invention discloses a flip-chip bonding surface encapsulation structure, which comprises a packaging body, wherein the packaging body internally comprises a plurality of electronic components and a chip frame, the electronic components are reversely attached to a groove on the chip frame to realize rewiring and circuit connection of the electronic components, three-surface or five-surface copper walls are formed on the outer surfaces of the side surface and the top surface of the packaging body, a metal film at the bottom of the packaging body is etched into an outer welding foot and an edge block, the side surface of the copper wall is connected with the side surface of the edge block, the copper wall at the top of the packaging body is contacted with the back surface of the electronic components, the copper wall at the side surface of the packaging body is connected with the side surface of the edge block to wrap a right-angle edge at the bottom of the packaging body, and the copper wall, the edge block and the outer welding foot are plated with tin oxidation-resistant layers.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a flip chip bonding surface encapsulation structure, a flip chip bonding surface encapsulation process and a semiconductor device.
Background
With the development of electronic products, semiconductor technology has been widely used to manufacture memories, central Processing Units (CPUs), liquid crystal display devices (LCDs), light Emitting Diodes (LEDs), laser diodes, and other devices or chip sets, and since electronic components have minute and fine circuits and structures, packaging technology is becoming more and more important, and packaging is a package for packaging electronic components, i.e., a housing for a semiconductor integrated circuit chip, which plays a role in placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating the internal world of the chip with an external circuit.
After the semiconductor chip is packaged to form a packaging structure, the packaging structure is connected or assembled with other device elements according to different use conditions, but the existing packaging structure is poor in heat dissipation and air tightness of packaging, low in packaging efficiency, incapable of achieving multidirectional shielding and one-way transmission of internal signals and further influencing product performance, and a packaging body is difficult to generate a tin climbing phenomenon in a subsequent welding process (such as welding the packaging body to a PCB (printed circuit board) through an outer welding pin, and difficult to master a welding effect.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a flip chip bonding surface encapsulation structure, a flip chip bonding surface encapsulation process and a semiconductor device.
In order to achieve the above object, the flip chip surface encapsulation process provided by the present application comprises the following steps:
(1) Providing a substrate covered with a metal film, prefabricating a patch frame on the metal film, and packaging the electronic component after inversely mounting the patch and exposing the back of the electronic component;
(2) Semi-cutting the packaging material until the metal film is exposed, and electroplating a copper wall on the cutting groove, the packaging body and the metal film to form three-surface packaging or five-surface packaging of the packaging body;
(3) Coating a film on the copper wall, baking and curing to bond the packaging body into a whole;
(4) Then the substrate is removed, and the metal film left on the packaging body is etched to form an outer welding leg connected with the circuit and an edge block at the edge of the bottom surface of the packaging body;
(5) The package is stripped and then scattered into a single product, and tin is plated on the copper wall, the outer welding leg and the edge block for oxidation resistance.
The step (1) further comprises that the metal film on the substrate is a copper film and has a thickness of 50-150 μm.
The step (1) further comprises that the patch frame is formed on the metal film surface of the metal film-coated substrate and is used for connecting pins of the electronic assembly to realize circuit connection and rerouting.
The step (1) further comprises that the patch frame is a prefabricated packaging structure which encapsulates the redistribution layer and the conducting layer, and the upper surface of the patch frame is provided with a groove, so that pins of the electronic component can be conveniently bonded with the groove in a patch mode when the electronic component is inverted.
The step (1) further comprises the step of plating a conductive block on the metal film surface of the substrate by the patch frame, plating a redistribution layer on the conductive block after the conductive block is exposed by packaging and grinding, plating a conductive post on the redistribution layer, etching and removing the conductive post after packaging, and forming a groove to realize the flip-chip patch, wherein the pins of the electronic component correspond to the grooves.
The step (2) further comprises that the thickness of the copper wall is 20-200 μm, the copper wall is positioned between the electronic component packaging bodies which are close to each other, and the copper wall on the top of the packaging bodies is contacted with the back surfaces of the electronic components.
The step (3) further comprises that the copper wall coating film is a photosensitive corrosion-resistant wet film, the top surface of the photosensitive corrosion-resistant wet film after coating is a horizontal plane, and the side surface of the photosensitive corrosion-resistant wet film after coating and the side surface of the metal film are the same vertical plane.
And the step (4) further comprises the step of etching the metal film left on the packaging body, namely photoetching and developing the metal film after coating a photosensitive corrosion-resistant dry film, and then removing the film, wherein the side surface of the copper wall is connected with the side surface of the edge block.
A flip-chip surface encapsulation structure comprising:
the packaging structure comprises a packaging body, a plurality of electronic assemblies and a patch frame, wherein the electronic assemblies are inversely attached to grooves on the patch frame to realize rewiring and circuit connection of the electronic assemblies;
the copper wall is formed by three or five surfaces on the outer surfaces of the side surface and the top surface of the packaging body;
and the side block is used for etching the metal film at the bottom of the packaging body into an outer welding leg and the side block, and the side surface of the copper wall is connected with the side surface of the side block.
Further, the copper wall on the top of the packaging body is in contact with the back of the electronic component.
Furthermore, the copper wall on the side surface of the packaging body is connected with the side surface of the side block to be used for wrapping the right-angle side at the bottom of the packaging body.
Furthermore, the copper wall, the edge block and the outer welding leg are plated with tin oxidation prevention layers.
A semiconductor device comprises the flip-chip bonding surface packaging structure.
The beneficial effects of the invention application are as follows:
(1) The electronic component is correspondingly pasted to the groove of the electronic component by prefabricating the pasting frame, the pasting frame can be put in storage for standby after one-step forming, and the electronic component can be directly taken and used during packaging, so that the working efficiency is increased and the cost is reduced compared with the existing packaging structure in which the electronic component is electroplated and packaged layer by layer;
(2) The copper wall at the top of the packaging body is arranged on the back of the electronic component, and compared with the existing plastic packaging material at intervals between the copper wall and the electronic component, the copper wall can conduct heat of the electronic component faster, prevents heat from being accumulated in the interval plastic packaging material, conducts heat fast, and has good heat dissipation effect because a plurality of copper walls form a plurality of faces to dissipate heat;
(3) Three-surface or five-surface encapsulation is formed on the surface of the packaging body, so that multidirectional shielding and unidirectional transmission of internal signals can be realized, and the packaging body is good in air tightness;
(4) The edge block is etched while the outer welding leg at the bottom of the packaging body is formed, the edge block is connected with the side face of the copper wall, two right-angle edges at the bottom of the packaging body are wrapped, and the packaging body is plated with tin for oxidation prevention, so that tin-climbing observation of a subsequent welding procedure of the packaging body is facilitated, the tin-out is obvious, and the process is simple.
Drawings
FIG. 1 is a process step diagram of a flip chip surface encapsulation process according to the present invention;
FIG. 2 is a schematic diagram of a die frame of a flip chip surface encapsulation process according to the present invention;
FIG. 3 is a schematic diagram of a flip chip for a flip chip surface encapsulation process according to the present invention;
FIG. 4 is a schematic diagram of a package for a flip chip surface mount encapsulation process of the present application;
FIG. 5 is a schematic diagram of a package cut after grinding for a flip chip surface encapsulation process according to the present invention;
FIG. 6 is a schematic structural diagram of a copper wall of a flip chip surface encapsulation process according to the present invention;
FIG. 7 is a schematic view of a copper wall coated wet photoresist film for a flip chip surface encapsulation process in accordance with the present invention;
FIG. 8 is a schematic illustration of a substrate removal for a flip chip surface encapsulation process according to the present invention;
FIG. 9 is a schematic view of a metal film coated photoresist dry film of a flip chip surface encapsulation process in accordance with the present invention;
FIG. 10 is a schematic illustration of metal film etching for a flip chip surface encapsulation process of the present application;
FIG. 11 is a schematic illustration of a stripping of a flip chip surface encapsulation process in accordance with the present invention;
FIG. 12 is a schematic structural diagram of a flip-chip surface package structure according to the present invention;
FIG. 13 is a schematic structural diagram of a three-sided encapsulation of a flip-chip surface encapsulation structure according to the present invention;
FIG. 14 is a schematic structural diagram of a five-sided encapsulation of a flip-chip surface encapsulation structure according to the present invention;
fig. 15 is a schematic diagram illustrating a solder climbing phenomenon of a flip chip surface package structure soldered to a PCB according to the present invention.
The symbols in the figure illustrate: the packaging structure comprises a packaging body 1, a metal film 2, a substrate 3, a groove 4, a cutting groove 5, an electronic component 6, a copper wall 7, a photosensitive corrosion-resistant wet film 8, a photosensitive corrosion-resistant dry film 9, an edge block 10, an outer welding leg 11 and a tin oxidation-resistant layer 12.
Detailed Description
For better understanding of the purpose, structure and function of the present application, a flip chip surface package structure, a flip chip surface package process and a semiconductor device according to the present application are described in detail below with reference to fig. 1 to 15.
Fig. 1 is a process step diagram of a flip chip surface encapsulation process according to the present invention, which includes the following steps:
s1, providing a substrate 3 coated with a metal film 2, prefabricating a patch frame on the metal film 2, and packaging and exposing the back of an electronic component 6 after the electronic component 6 is flip-chip mounted;
s2, semi-cutting the packaging material until the metal film 2 is exposed, and electroplating a copper wall 7 on the cutting groove 5, the packaging body 1 and the metal film 2 to form three-surface packaging or five-surface packaging of the packaging body 1;
s3, coating a film on the copper wall 7, baking and curing to bond the packaging body 1 into a whole;
s4, removing the substrate 3, and etching the metal film 2 left on the packaging body 1 to form an outer welding leg 11 connected with a circuit and an edge block 10 at the edge of the bottom surface of the packaging body 1;
and S5, removing the film of the packaging body 1, scattering the film into single products, and plating tin on the copper wall 7, the outer welding leg 11 and the edge block 10 for oxidation resistance.
Referring to S1 and fig. 2 to 5, providing a substrate 3 covered with a metal film 2, prefabricating a patch frame on the metal film 2, flip-chip mounting an electronic component 6, and then packaging and exposing the back of the electronic component 6; namely the common board level package in the field, the metal film 2 can be a copper film, a plurality of patch frames can be formed on the substrate 3, the present application takes two as an example, so two electronic components 6 are pasted, the electronic components 6 can be other devices such as chips or capacitors, etc., the electronic components 6 are pasted after pins are made, the present application has the specific process that copper or gold bumps (Bump) are made on the surface of a wafer (wafer) to form pins, the number of the pins of the electronic components 6 is established according to the actual production, a plurality of pins are regularly arranged on each electronic component 6 in the present application, then tin is plated on the bumps for the subsequent pasting, wherein the substrate 3 is a substrate commonly used in the field, such as an FR-4 plate, the copper film is coated on one upper surface of the substrate, the patch frames are formed on the metal film 2 surface of the substrate 3 coated with the metal film 2, and are used for connecting the pins of the electronic components 6 to realize the package structure of rewiring, the paster frame is formed by plating a conductive block on the surface of a metal film 2 of a substrate 3, packaging, grinding and exposing the conductive block, plating a redistribution layer on the conductive block, plating a conductive column on the redistribution layer, etching and removing the conductive column after packaging to form a groove 4, wherein the groove 4 corresponds to a plurality of pins arranged in order on an electronic component 6 one by one, then printing a tin material by using a steel mesh to realize welding and inversely mounting the paster, the pins of the electronic component 6 correspond to the groove 4, and all the process and size quantity requirements are adapted to the actual production requirements. The working efficiency is increased and the cost is reduced, and the thickness of the metal film 2 on the substrate 3 is 50-150 μm, which is related to the height of the required outer solder leg of the electronic component 6.
Referring to S2 and fig. 5 to 6, the encapsulant is half-cut until the metal film 2 is exposed, and a copper wall 7 is electroplated on the cutting groove 5, the package 1 and the metal film 2 to form a three-sided encapsulation or a five-sided encapsulation of the package 1; half cutting means that a cutting knife does not completely cut two packaging bodies 1 apart to cut until the metal film 2 is exposed, only two electronic components 6 are pasted to form a top view of the packaging body 1 when the packaging body 1 is seen to the substrate 3, a coordinate axis is established on the top view, the transverse direction is an X axis, the longitudinal direction is a Y axis, only downward vertical cutting along the Y direction is needed, if a plurality of electronic components 6 are pasted, namely downward vertical cutting along the X axis and the Y axis to the metal film 2 is needed, the cutting knife is a diamond knife commonly used in the field, the cutting width of the cutting knife can be adjusted to adapt to the width of the plastic packaging material between the two packaging bodies 1, the plastic package material is guaranteed to be cut only and electronic components 6 and circuits are not cut, a metal seed layer is formed on the cutting groove 5, the packaging body 1 and the metal film 2, three or five surfaces of each single product are formed, the forming mode is also a mode common in the field, for example, copper deposition or sputtering is carried out to be used as a base of an electroplated copper wall, and then the electroplated copper wall 7 is a common electroplating means in the field, the thickness of the copper wall 7 is 20-200 mu m, the side copper walls 7 are located between the packaging bodies 1 close to each other, the copper wall 7 at the top of the packaging body 1 is in contact with the back of the electronic components 6, heat conduction is fast, the copper walls 7 form multi-surface heat dissipation, and the heat dissipation effect is good.
Referring to S3 and fig. 7, the copper wall 7 is coated and baked to be cured to bond the package 1 into a whole; the copper wall 7 is coated with a photosensitive resist wet film 8, which is an etching-resistant electroplating-resistant ink mainly composed of photosensitive materials, a photosensitizer, a pigment, a solvent and the like, wherein the top surface of the photosensitive resist wet film 8 after coating is a horizontal plane, the side surface of the photosensitive resist wet film 8 after coating is the same vertical plane with the side surface of the metal film 2, and after coating, drying and curing are carried out, wherein the photosensitive resist wet film 8 is cured through baking to bond the packaging body 1 into a whole, and the whole is a cuboid.
Referring to S4 and fig. 7 to 10, the substrate 3 is removed, and the metal film 2 left on the package 1 is etched to form outer solder tails 11 for circuit connection and edge blocks 10 at the bottom edge of the package 1; the substrate 3 is peeled off in a mechanical mode, the metal film 2 is attached to the bottom of the packaging body 1, the bottom of the metal film 2 is coated with the photosensitive corrosion-resistant dry film 9, and then the film is removed through photoetching development, the photosensitive corrosion-resistant dry film 9 is a common etching mode in the field, the photosensitive corrosion-resistant dry film 9 is used for photoetching development protection, the metal film 2 at the coating position is not etched and is reserved to finally form the outer welding leg 11 and the edge block 10, the shapes of the outer welding leg 11 and the edge block 10 can be changed through the coated film, the outer welding leg 11 and the edge block 10 are cuboids with different sizes, the outer welding leg 11 is electrically connected with a Bump of the electronic component 6 through a conductive block and a rewiring layer in a patch frame, the side surface of the copper wall 7 is connected with the side surface of the edge block 10, so that the copper wall 7 and the edge block 10 form a whole to wrap a right-angle edge at the bottom of the packaging body 1.
Referring to S5, fig. 11 to 12, and fig. 13 to 14, the package 1 is peeled off and scattered into individual products, and plated with tin to prevent oxidation on the copper wall 7, the outer leg 11, and the edge block 10; the photosensitive dry film 9 and the photosensitive wet film 8 are stripped, the stripping solution with certain concentration and temperature is adopted for cleaning or soaking, the stripping solution can be NaOH solution and is a common mode in the field, the stripping solution and the photosensitive dry film 9 and the photosensitive wet film 8 are removed together, the stripping solution is scattered into a plurality of single products after stripping, the stripping solution is scattered into two single products, a tin oxidation preventing layer 12 is plated on a copper wall 7, an outer welding leg 11 and a side block 10, the side face of the side block 10 is connected with the side face of the copper wall 7 and is plated with tin, the side block 10 can be connected with the copper walls 7 on four sides and can also be connected with the copper walls 7 on two opposite sides, the stripping solution is connected with the copper walls 7 on four sides as an example, when the products are welded subsequently, tin paste is coated on the outer welding leg 11, the outer welding leg 11 is low in height and has a certain distance from the edge of a packaging body 1, tin climbing on the edge of the packaging body is observed, the side block 10 is consistent with the outer welding leg 11 in height, the welding condition can be judged by observing the tin climbing condition on the side block 10 and the bottom of the copper wall 7, if tin materials are stacked well, the welding condition that no tin stacking exists, the welding condition can be observed, and the condition that the welding is possibly poor welding condition that the false welding condition exists, and the welding condition exists.
Please refer to fig. 13 to 14, which are schematic structural diagrams of three-sided and five-sided encapsulation of a flip chip surface encapsulation structure according to the present invention, including:
the packaging structure comprises a packaging body 1, wherein the packaging body 1 internally comprises a plurality of electronic components 6 and a patch frame, the electronic components 6 are inversely attached to a groove 4 on the patch frame to realize rewiring and circuit connection of the electronic components 6, and a copper wall 7 at the top of the packaging body 1 is in contact with the back of the electronic components 6;
the copper wall 7, form the copper wall 7 of three-sided or five-sided on the external surface of side and top of the encapsulated body 1;
A semiconductor device comprises the flip-chip bonding surface packaging structure.
Referring to fig. 15, in a subsequent soldering process of a product, when the package body 1 is soldered to a PCB through the outer solder leg 11, the product in fig. 15 is a flip-chip surface encapsulation structure of the application, the PCB is below the product, and the product is soldered to the PCB through a solder material, because the outer solder leg 11 of the product is smaller in height and has a certain distance from the edge of the package body 1, the soldering of the solder is not obvious, the edge block 10 with the same height is arranged, and the edge block 10 is connected with the copper wall 7 to wrap the right-angle edge at the bottom of the package body 1, during soldering, the solder material is stacked at the edge block 10 and the copper wall 7, and a solder climbing phenomenon occurs, such as the solder material stacking visible on the side of the product in fig. 15, the soldering quality is determined through solder climbing observation, and the inspection is facilitated.
In the manufacturing process of the packaging body 1, in order to meet the packaging requirement, in the industry, the front of an electronic component 6 with a ball (Bump) planted is usually placed upwards, the back of the electronic component 6 is adhered to a substrate 3 through a DAF film, namely, the packaging body is normally installed, the substrate 3 is an epoxy resin substrate common in the field, and the surface is not covered with a copper film, then the electronic component 6 is electroplated and packaged layer by layer, specifically, the electronic component 6 is packaged, the upper plane of the electronic component 6 is ground until the Bump is exposed, a heavy wiring layer (RDL) and a conductive post are electroplated on the Bump, the conductive post is exposed after the packaging body is packaged again, and then an outer welding pin 11 is electroplated on the electronic component 6, namely, the packaging body 1 packaged layer by layer is completed, then the whole packaging body 1 is inverted on the substrate 3 to be cut or subjected to subsequent procedures, and in the application, the electronic component 6 is pasted on the surface by adopting a prefabricated paster frame, so that the efficiency can be improved, and the damage probability of the electronic component 6 can also be reduced during rework;
the thickness of the copper wall 7 can be controlled according to actual production requirements, the copper wall 7 at the top is directly contacted with the back of the electronic component 6, heat generated by the electronic component 6 is directly conducted and dissipated by the copper wall 7, and the heat dissipation effect is good;
three-surface or five-surface encapsulation is formed on the surface of the packaging body 1, so that multidirectional shielding and one-way transmission of internal signals can be realized, the air tightness of the packaging body 1 is good, and the cost can be saved by the three-surface encapsulation compared with the five-surface encapsulation when the requirements on heat dissipation, electromagnetic shielding, air tightness and tin climbing observation can be met;
the edge block 10 is etched at the same time as the bottom outer leg 11 of the package 1 is formed, and the outer leg 11 is finally formed without limitation in shape and number.
It is to be understood that the present application is described with respect to certain embodiments, and it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (13)
1. A flip chip surface encapsulation process is characterized by comprising the following steps:
(1) Providing a substrate covered with a metal film, prefabricating a patch frame on the metal film, inversely mounting the electronic component on the patch, packaging and exposing the back of the electronic component;
(2) Semi-cutting the packaging material until the metal film is exposed, and electroplating a copper wall on the cutting groove, the packaging body and the metal film to form three-surface packaging or five-surface packaging of the packaging body;
(3) Coating a film on the copper wall, baking and curing to bond the packaging body into a whole;
(4) Then the substrate is removed, the metal film left on the packaging body is etched to form an outer welding leg connected with a circuit and an edge block at the edge of the bottom surface of the packaging body, the side surface of the edge block is connected with the side surface of the copper wall and is plated with tin, the outer welding leg is low in height and has a certain distance from the edge of the packaging body, and the edge block is consistent with the outer welding leg in height;
(5) The package is stripped and then scattered into a single product, and tin is plated on the copper wall, the outer welding leg and the edge block for oxidation resistance.
2. The flip chip surface encapsulation process of claim 1, wherein the step (1) further comprises the step of forming the metal film on the substrate as a copper film with a thickness of 50-150 μm.
3. The flip chip surface encapsulation process of claim 2, wherein step (1) further comprises forming the die frame on the metal film side of the metal film-coated substrate for connecting the leads of the electronic component to the circuit and for rerouting the leads.
4. The flip chip surface encapsulation process of claim 3, wherein the step (1) further comprises the step of encapsulating the redistribution layer and the conductive layer by the die frame to form a pre-fabricated package structure, and the die frame is provided with a groove on an upper surface thereof for facilitating die bonding of the leads of the electronic component corresponding to the groove during flip chip mounting.
5. The flip chip surface packaging process of claim 3, wherein the chip frame is formed by plating a conductive block on a metal film surface of the substrate, polishing the package to expose the conductive block, plating a redistribution layer on the conductive block, plating a conductive post on the redistribution layer, and etching to remove the conductive post after packaging to form a recess for the flip chip, wherein the pins of the electronic component correspond to the recesses.
6. The flip chip surface encapsulation process of claim 1, wherein the step (2) further comprises the step of forming the copper walls with a thickness of 20-200 μm between the electronic package packages adjacent to each other, wherein the copper walls on the top of the electronic package are in contact with the back surfaces of the electronic packages.
7. The flip chip surface encapsulation process according to claim 1, wherein the step (3) further comprises coating the copper wall with a photoresist wet film, wherein the top surface of the photoresist wet film after coating is a horizontal surface, and the side surface of the photoresist wet film after coating is a vertical surface.
8. The flip chip surface encapsulation process of claim 1, wherein step (4) further comprises etching the metal film remaining on the package body, in particular by applying a photoresist dry film, followed by photolithography and developing to remove the film, wherein the side surfaces of the copper walls are bonded to the side surfaces of the side blocks.
9. A flip chip surface package structure, comprising:
the packaging structure comprises a packaging body, a plurality of electronic assemblies and a patch framework, wherein the electronic assemblies are inversely pasted on grooves on the patch framework to realize rewiring and circuit connection of the electronic assemblies;
the copper wall is formed by three or five surfaces on the outer surfaces of the side surface and the top surface of the packaging body;
and the side block is used for etching the metal film at the bottom of the packaging body into an outer welding leg and the side block, and the side surface of the copper wall is connected with the side surface of the side block.
10. The flip-chip surface package structure of claim 9, wherein the copper wall on the top of the package is in contact with the back side of the electronic component.
11. The flip chip surface package structure of claim 10, wherein the copper walls of the package side surface are joined to the side block side surface to wrap the right-angled edge of the package bottom.
12. The flip chip surface package of claim 11, wherein the copper walls, edge blocks and outer fillets are plated with an oxidation resistant layer of tin.
13. A semiconductor device comprising the flip-chip surface encapsulated structure of any one of claims 9-12.
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| CN108206170B (en) * | 2017-12-29 | 2020-03-06 | 江苏长电科技股份有限公司 | Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof |
| CN110364444A (en) * | 2019-08-01 | 2019-10-22 | 合肥矽迈微电子科技有限公司 | Attached metal wrapping encapsulating structure in three faces and preparation method thereof |
| CN110517962A (en) * | 2019-08-01 | 2019-11-29 | 合肥矽迈微电子科技有限公司 | Attached metal wrapping encapsulating structure in five faces and preparation method thereof |
| CN114783888B (en) * | 2022-06-16 | 2022-09-06 | 合肥矽迈微电子科技有限公司 | Chip package external exposure welding leg and processing method thereof |
| CN115148695A (en) * | 2022-07-25 | 2022-10-04 | 合肥矽迈微电子科技有限公司 | Pre-encapsulated substrate and manufacturing method thereof |
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