CN116313822A - Packaging method of chip and packaging piece - Google Patents

Packaging method of chip and packaging piece Download PDF

Info

Publication number
CN116313822A
CN116313822A CN202211091858.4A CN202211091858A CN116313822A CN 116313822 A CN116313822 A CN 116313822A CN 202211091858 A CN202211091858 A CN 202211091858A CN 116313822 A CN116313822 A CN 116313822A
Authority
CN
China
Prior art keywords
glass substrate
packaging
pins
package
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211091858.4A
Other languages
Chinese (zh)
Inventor
胡津津
高宸山
刘磊
张强波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sky Chip Interconnection Technology Co Ltd
Original Assignee
Sky Chip Interconnection Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sky Chip Interconnection Technology Co Ltd filed Critical Sky Chip Interconnection Technology Co Ltd
Priority to CN202211091858.4A priority Critical patent/CN116313822A/en
Publication of CN116313822A publication Critical patent/CN116313822A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

Abstract

The application discloses a packaging method and a packaging piece of a chip, wherein the packaging method of the chip comprises the following steps: providing a glass substrate with pins on two sides; welding a device on a pin on one surface of the glass substrate, and enabling a bonding pad on the device to be electrically connected with the pin on the glass substrate; and carrying out plastic packaging on the glass substrate and the device by using a plastic packaging material, exposing one surface of the glass substrate, which is away from the device, so as to package the side of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate. With the structure, the reliability of the glass substrate package is improved.

Description

Packaging method of chip and packaging piece
Technical Field
The present disclosure relates to the field of glass packaging technologies, and in particular, to a method for packaging a chip and a package.
Background
SIP (system in package) refers to integrating a circuit composed of a plurality of chips with different functions into a module to form a packaged integral structure, which integrates the advantages of the existing core resources and semiconductor production process, and realizes the complete system or subsystem functions of the electronic product. SiP was developed to improve semiconductor functions and density for the miniaturization of the whole system.
The SiP is used as a brand new integration method and packaging technology, has a series of unique technical advantages, meets the development requirements of lighter, smaller and thinner electronic products at present, and has wide application market and development prospect in the field of microelectronics.
The high-density system-in-module packaging structure of the existing glass substrate is mainly cut uniformly at last, and the edge of the cut glass substrate cannot be fully wrapped, so that the edge glass substrate is easy to laminate in a plastic sealing layer, and the reliability of a device is reduced; the internal devices cannot be effectively protected, so that the service life of the devices is short. In addition, the problem that the cutting yield of the whole device cannot meet the industry requirement due to low cutting yield of the glass substrate is also solved.
Disclosure of Invention
The technical problem that this application mainly solves is to provide a packaging method and package of chip to improve the reliability of glass substrate package, promote the product yield, reduce holistic cost etc..
The application provides a packaging method of a chip, wherein the packaging method of the chip comprises the following steps: providing a glass substrate with pins on two sides; welding a device on a pin on one surface of the glass substrate, and enabling a bonding pad on the device to be electrically connected with the pin on the glass substrate; and carrying out plastic packaging on the glass substrate and the device by using a plastic packaging material, exposing one surface of the glass substrate, which is away from the device, so as to package the side of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate.
The step of providing the glass substrate with the pins on two sides comprises the following steps: providing a flat glass substrate; manufacturing a through hole on the glass substrate; electroplating copper in the through hole to form a hole copper column; and manufacturing pins at positions of the opposite sides of the glass substrate corresponding to the hole copper columns, so that the pins of the opposite sides of the glass substrate are conducted through the hole copper columns.
Wherein, the step of manufacturing pins at positions of the two opposite sides of the glass substrate corresponding to the hole copper columns further comprises: coating PI glue on two opposite sides of the glass substrate; exposing and developing the PI glue to expose the surface of the hole copper column; and electroplating copper on the surface of the hole copper column to form the pin.
Wherein, the step of making the through hole on the glass substrate comprises the following steps: manufacturing a plurality of through holes on the glass substrate; electroplating copper within each of the vias to form the Kong Tongzhu; manufacturing pins at positions of two opposite sides of the glass substrate corresponding to the hole copper columns; cutting the glass substrate to obtain the glass substrate with the pins of the preset number; the number of the pins corresponds to the number of the hole copper columns.
The method comprises the steps of utilizing plastic packaging materials to carry out plastic packaging on the glass substrate and the device, exposing one surface of the glass substrate, which is far away from the device, so as to package the side wall of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate, and the method comprises the following steps: placing the other surface of the glass substrate on a carrier plate; using plastic packaging material to carry out plastic packaging on the glass substrate and the device on the surface of the carrier plate so as to package the side wall of the glass substrate and the device together; and removing the carrier plate to expose one surface of the glass substrate, which is away from the device.
The method comprises the steps of utilizing plastic packaging materials to carry out plastic packaging on the glass substrate and the device, exposing one surface of the glass substrate, deviating from the device, so as to package the side wall of the glass substrate and the device together, leading out a bonding pad on the device through a pin on the glass substrate, and further comprising the following steps: the other surfaces of the glass substrates are placed on the carrier plate at intervals; using plastic packaging material to carry out plastic packaging on the glass substrate and the device on the surface of the carrier plate so as to package the side wall of the glass substrate and the device together; removing the carrier plate to expose one surface of the glass substrate, which is away from the device; and cutting along the middle positions of two adjacent glass substrates to obtain a plurality of independent single-chip packages which are packaged together by the side walls of the glass substrates and the devices.
Wherein, remove the carrier plate, expose the step of the one side of glass substrate deviating from the device, still include: and cutting along the middle of the two spaced glass substrates to obtain a plurality of mutually independent double-chip packaging bodies which are packaged together by the side walls of the glass substrates and the devices.
The method comprises the steps of using plastic packaging material to carry out plastic packaging on the glass substrate and the device, exposing one surface of the glass substrate, deviating from the device, packaging the side edge of the glass substrate and the device together, leading out a bonding pad on the device through a pin on the glass substrate, and then further comprises the following steps: and manufacturing a ball-planting on a pin on one surface of the glass substrate, which is away from the device, so as to lead out a bonding pad on the device through the ball-planting.
Wherein the device is a radio frequency device; the plastic package material is epoxy resin.
The application also provides a package, wherein the package includes: the device comprises a glass substrate, wherein pins are arranged on two opposite surfaces of the glass substrate; the device is provided with a bonding pad, and the device is welded on a pin on one side of the glass substrate through the bonding pad; and the plastic packaging material encapsulates the side wall of the glass substrate and the device, and exposes one surface of the glass substrate, which is away from the device.
The beneficial effects of this application are: the device is welded on the glass substrate, the device and the glass substrate are packaged together by using the plastic package material, and one surface of the glass substrate provided with the pins is exposed, so that the purpose of packaging the device is achieved, the edge of the glass substrate is not exposed, and the risk of layering of the glass substrate and the plastic package material is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a first embodiment of a method for packaging a chip of the present application;
FIG. 2 is a flowchart illustrating the step S11 of FIG. 1 according to an embodiment;
FIG. 3 is a flowchart illustrating the step S13 of FIG. 1 according to an embodiment;
FIG. 4 is a flow chart of a second embodiment of a method for packaging a chip according to the present application;
FIG. 5 is a schematic diagram showing the variation of the package structure in steps S41-S52 in FIG. 4;
FIG. 6a is a schematic top view of a first cutting mode of a glass substrate according to the present application;
FIG. 6b is a schematic top view of a second embodiment of a glass substrate;
FIG. 7 is a schematic view of a first embodiment of a package of the present application;
fig. 8 is a schematic structural diagram of a second embodiment of the package of the present application.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It should be noted that, in the embodiment of the present application, directional indications (such as up, down, left, right, front, and rear … …) are referred to, and the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic flow chart of a first embodiment of a method for packaging a chip of the present application, and as shown in fig. 1, the method for packaging a chip includes:
step S11: provided is a glass substrate with pins provided on both sides.
In this embodiment, pins are disposed on two opposite sides of the glass substrate, and the pins on the two opposite sides are electrically connected to each other, so that the pins on one side are led out through the pins on the other side.
In one embodiment, the glass substrate is a thin glass sheet with a flat surface, and then double-sided pins are fabricated on the glass substrate. Among them, the production method of the glass substrate includes a float process, an overflow down-draw process, a slot down-draw process, and the like.
Specifically, referring to fig. 2, fig. 2 is a flow chart of an embodiment of step S11 in fig. 1. As shown in fig. 2, step S11 specifically includes:
step S21: a flat glass substrate is provided.
Wherein, the glass substrate is a complete glass substrate with a flat surface.
Step S22: and manufacturing a through hole on the glass substrate.
Specifically, one or more through holes are formed in preset positions of the glass substrate by utilizing a laser ablation or chemical etching process, wherein the through holes penetrate through the glass substrate. The number of the through holes can be set according to actual requirements, or can be set according to the number of the bonding pads on the device or the chip, and is not limited herein.
Step S23: and electroplating copper in the through hole to form a hole copper column.
And (5) fully plating copper in the through hole by using an electroplating process to form a hole copper column.
Step S24: pins are manufactured at positions of the two opposite sides of the glass substrate corresponding to the hole copper columns, so that the pins on the two opposite sides of the glass substrate are conducted through the hole copper columns.
The method comprises the steps of manufacturing patterns on the surfaces of two opposite sides of a glass substrate, and then manufacturing pins on the two opposite sides of the glass substrate, wherein the number and the spacing of the pins can be correspondingly set according to the number and the spacing of bonding pads on a device.
The method specifically comprises the following steps: first, PI glue is coated on two opposite sides of a glass substrate. The PI glue covers the whole surfaces of the two opposite sides of the glass substrate. And secondly, performing exposure and development treatment on the PI glue to expose the surface of the hole copper column. The method further comprises the step of curing the PI adhesive. And (3) preparing a graphical dry film on the surface of the PI adhesive, and etching the PI adhesive by using etching liquid medicine to expose the surface of the hole copper column below the PI adhesive. Thirdly, electroplating copper on the surface of the hole copper column to form the pin. In one embodiment, the pins are fabricated above the hole copper pillars and disposed in correspondence with the hole copper pillars, and in another embodiment, the pins are not disposed directly in correspondence with the hole copper pillars, but are at least partially connected to the hole copper pillars, so that the pins on opposite sides are connected through the hole copper pillars in preparation for subsequent soldering of the device pads.
The step S24 further includes cutting the glass substrate, specifically, cutting according to the number of pins on the surface of the glass substrate, so that the single glass substrate meets the requirement of the soldering device.
Step S12: and welding the device on a pin on one surface of the glass substrate, and electrically connecting a bonding pad on the device with the pin on the glass substrate.
Specifically, the bonding pad on the device is welded with the pin on one side of the glass substrate, and the bonding pad on the device is led to the pin on the other side of the glass substrate through the pin on one side of the glass substrate, so that the bonding pad of the device can be electrically connected with other devices or external devices through the pin on the other side of the glass substrate.
In this embodiment, the number of pins on opposite sides of the glass substrate is the same, and the number of pins corresponds to the number of hole copper pillars, specifically, the number of pins is twice the number of hole copper pillars.
In one embodiment, the number of pins on one surface of the glass substrate is the same as the number of pads on the device, so as to facilitate corresponding soldering. In another embodiment, the number of pins on one side of the glass substrate is greater than the number of pads on the device. In this embodiment, the number of pins on the glass substrate is at least greater than the number of pads on the device, but may be greater than twice the number of pads on the device.
When the number of pins on the glass substrate is more than twice the number of bonding pads on the device, the method further comprises cutting the glass substrate before the step to obtain a plurality of glass substrates with pins arranged on two opposite sides, and picking out defective products from the glass substrates. The cutting may be performed according to the number of pins on opposite sides of the glass substrate, specifically, according to the number of pads on the device, so that the number of pins on one side of the glass substrate is the same as the number of pads on the device. The method further comprises the following steps: and selecting one from a plurality of glass substrates with pins on two opposite sides to be welded with a bonding pad of one device.
Wherein, the device is welded on the glass substrate by using a flip-chip bonding process and forms a whole with the glass substrate.
In other embodiments, a plurality of devices may be soldered to the glass substrate, without limitation.
Step S13: and (3) carrying out plastic packaging on the glass substrate and the device by using the plastic packaging material, exposing one surface of the glass substrate, which is away from the device, so as to package the side of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate.
In one embodiment, the glass substrate and the device are encapsulated with a carrier plate. Specifically, referring to fig. 3, fig. 3 is a flow chart illustrating an embodiment of step S13 in fig. 1. As shown in fig. 3, step S13 specifically includes:
step S31: and placing the other surface of the glass substrate on the carrier plate.
The other side of the glass substrate refers to the side of the glass substrate away from the device, and is opposite to one side of the glass substrate.
The carrier plate is used for placing the to-be-packaged piece so as to facilitate packaging and shaping.
Step S32: and manufacturing plastic packaging materials on the surfaces of the carrier plates so that the plastic packaging materials cover the surfaces and the side walls of the glass substrate and the device.
And placing the glass substrate welded with the device on a carrier plate, and then integrally packaging the glass substrate and the device by using a plastic packaging material, so that the plastic packaging material wraps the five surfaces, namely the top surface and the side wall, of the glass substrate and the device.
Step S33: and removing the carrier plate to expose the other surface of the glass substrate.
And removing the carrier plate to expose the bottom surface of the glass substrate, so as to obtain the five-sided packaged glass substrate and the six-sided packaged device.
In this embodiment, the device and the glass substrate are packaged together as a whole, so that the edge of the glass substrate is not exposed, and meanwhile, the risk of delamination of the glass substrate and the plastic package material at the junction is reduced.
The beneficial effects of this embodiment are: the device is welded on the glass substrate, the device and the glass substrate are packaged together by using the plastic package material, and one surface of the glass substrate provided with the pins is exposed, so that the purpose of packaging the device is achieved, the edge of the glass substrate is not exposed, and the risk of layering of the glass substrate and the plastic package material is reduced.
The present application further provides a second method for packaging a chip, referring to fig. 4 and fig. 5 specifically, fig. 4 is a flow chart of a second embodiment of the method for packaging a chip of the present application, and fig. 5 is a schematic diagram of a change of a package structure in steps S41-S52 in fig. 4. As shown in fig. 4, includes:
step S41: provided is a glass substrate.
The specific structure is shown in fig. 5 a.
Step S42: and manufacturing a through hole on the glass substrate.
The specific structure is shown in fig. 5B.
Step S43: and electroplating copper in the through hole to form a hole copper column.
The specific structure is shown in fig. 5C.
Step S44: PI glue was applied to opposite sides of the glass substrate to cover the surface of Kong Tongzhu with PI glue.
The specific structure is shown in fig. 5D.
Step S45: and exposing and developing the PI glue to expose the surface of the hole copper column.
The specific structure is shown in fig. 5E.
Step S46: copper is electroplated on the surface of the hole copper column to form the two-sided pin.
The specific structure is shown as F in fig. 5.
Step S47: cutting the glass substrate.
The specific structure is shown in fig. 5G. Through cutting the glass substrate, defective products can be selected from the glass substrate, so that the yield of the glass substrate is ensured.
The method comprises the steps of cutting a glass substrate based on the number of pins on the glass substrate, and enabling the number of pins on one side surface of the single glass substrate to be not smaller than the number of bonding pads on a device.
Step S48: and welding a device on the pin on one surface of the glass substrate, and enabling the bonding pad on the device to be electrically connected with the pin on the glass substrate.
The specific structure is shown as H in fig. 5. In step S48, after the glass substrate is placed on the carrier, the device may be soldered on the lead on the side of the glass substrate facing away from the carrier in step S49. The order of fabrication is not limited herein.
Step S49: and placing the other surface of the glass substrate on the carrier plate.
The specific structure is shown as I in FIG. 5. One surface of the glass substrate, which is away from the device, is placed on the carrier plate so as to facilitate packaging of the device.
It can be understood that the to-be-packaged body formed by the glass substrates and the devices is placed on the surface of the carrier plate, and after packaging is completed, cutting is performed according to the number requirements, so that a single package body is obtained.
Step S50: and manufacturing plastic packaging materials on the surfaces of the carrier plates so that the plastic packaging materials cover the surfaces and the side walls of the glass substrate and the device.
The specific structure is shown as J in FIG. 5. And the side edges of the glass substrate on the carrier plate and the surfaces and the side edges of the devices are encapsulated by using the plastic packaging material, so that the glass substrate and the devices are encapsulated together, the encapsulation efficiency is improved, and the layering of the encapsulation layers of the glass substrate and the devices is avoided.
Step S51: and removing the carrier plate, exposing the other surface of the glass substrate, and manufacturing the implanting balls on the pins on the other surface of the glass substrate to obtain the packaged glass substrate and device.
The specific structure is shown as K in fig. 5.
Step S52: the encapsulated glass substrate and device are diced.
Please refer to fig. 5, L. Specifically, dicing is performed along the middle of two adjacent glass substrates to obtain a plurality of packages.
The step S52 may further cut the plurality of packages on the carrier before the step S51, that is, before the carrier is removed. Wherein, the package body at least comprises a glass substrate and a device.
In one embodiment, the method comprises the following steps: and the other surfaces of the glass substrates are arranged on the carrier plate at intervals, the glass substrates and the devices are packaged at the same time, and the glass substrates are cut along the middle of two adjacent glass substrates, so that a plurality of mutually independent single-chip packages are obtained. Specifically, referring to fig. 6a, fig. 6a is a schematic top view of a first cutting method of a glass substrate according to the present application. As shown in fig. 6a, a device 62 is placed on each of a plurality of glass substrates 61, and the plurality of glass substrates 61 are placed on a carrier 63 in an array arrangement. The cutting is performed along the dotted line in fig. 6a to obtain a plurality of single chip packages, and the cutting method can manufacture a plurality of single chip packages at the same time.
In another specific embodiment, the method comprises the steps of: the cutting is performed along the middle of an even number or along two glass substrates spaced apart to obtain a plurality of mutually independent dual-chip packages, referring to fig. 6b, fig. 6b is a schematic top view structure of a second cutting mode of the glass substrates in the present application. As shown in fig. 6b, the cutting is performed along the dotted line in fig. 6b to obtain a plurality of dual chip packages, and the cutting may be performed in such a manner that a plurality of dual chip packages are fabricated at the same time. In other embodiments, dicing may also be performed along edges of the plurality of glass substrates to obtain a plurality of multi-chip packages, which is not limited herein.
In this embodiment, the device may be a radio frequency device. The glass substrate is used for carrying out auxiliary packaging on the radio frequency device, so that the packaging reliability of the radio frequency device is ensured, and the signal interference of other packaging materials on the radio frequency device is avoided.
In this embodiment, the material of the molding compound is an epoxy resin material.
The beneficial effects of this embodiment are: the glass substrate is cut firstly, then the flip-chip device and pins of the glass substrate are welded partially, defective products of the cut glass substrate can be removed effectively, the device is welded on the good glass substrate finally, and the glass substrate and the device are packaged integrally, so that the edge of the glass substrate is not exposed, the purpose of five-sided protection is achieved, the layering risk of the substrate and plastic packaging materials is reduced, the packaging yield of the device is improved, in addition, when the glass substrate is manufactured, the glass substrate with defective cutting or defective yield is removed, the improvement of the yield of the finished product is facilitated, and meanwhile, the glass substrate is used for packaging the device, so that the packaging cost is reduced.
The present application further provides a package, and particularly referring to fig. 7, fig. 7 is a schematic structural diagram of a first embodiment of the package of the present application. As shown in fig. 7, the package includes a glass substrate 71, and pins 711 are provided on opposite sides of the glass substrate 71. The device 72 is provided with a bonding pad 721, and the bonding pad 721 on the device 72 is soldered to a lead 711 on one surface of the glass substrate 71 to form an electrical connection with the lead 711. The molding compound 73, the molding compound 73 encapsulates the five sides of the glass substrate 71 and the device 72, and exposes the leads 711 on the other side of the glass substrate 71.
In the present embodiment, one device 72 is provided corresponding to one glass substrate 71.
In other embodiments, multiple devices 72 may be soldered on the glass substrate 71, and the multiple devices 72 may be packaged simultaneously to obtain a multi-core packaged package.
Wherein the pads 721 on the device 72 are flip-chip bonded to the glass substrate 71.
The number of pins on the glass substrate 71 corresponds to the number of pads on the device 72. Specifically, the number of pins 711 on the glass substrate 71 is twice the number of pads 721 on the device 72.
In this embodiment, the glass substrate 71 is further covered with a PI glue layer 712, and the PI glue layer 712 is disposed on two opposite sides of the glass substrate 71 and has the same height as the pins 711, so as to maintain the flatness of the glass substrate 71.
In the present embodiment, a plurality of solder balls 74 are soldered on the leads 711 on the other surface of the glass substrate 71 to electrically connect with external devices through the solder balls 74.
The beneficial effects of this embodiment are: the device is welded on the glass substrate, the device and the glass substrate are packaged together by using the plastic package material, and one surface of the glass substrate provided with the pins is exposed, so that the purpose of packaging the device is achieved, the edge of the glass substrate is not exposed, and the risk of layering of the glass substrate and the plastic package material is reduced.
The present application further provides a second package, and in particular, referring to fig. 8, fig. 8 is a schematic structural diagram of a second embodiment of the package of the present application. As shown in fig. 8, the package includes a glass substrate 81, and pins 811 are provided on opposite sides of the glass substrate 81. The device 82, the device 82 is provided with a bonding pad 821, and the bonding pad 821 on the device 82 is soldered to a pin 811 on one surface of the glass substrate 81 to form an electrical connection with the pin 811. The molding compound 83, the molding compound 83 encapsulates the five sides of the glass substrate 81 and the device 82, and exposes the leads 811 on the other side of the glass substrate 81.
In the present embodiment, at least two devices 82 are soldered to the surface of the glass substrate 81.
In this embodiment, the number of pins 811 on one side of the glass substrate 81 is at least greater than the sum of the numbers of pads 821 of two devices 82.
In the present embodiment, the molding compound 83 encapsulates at least two devices 82 and one glass substrate 81 as a whole.
The glass substrate 81 is further covered with a PI glue layer 812, and the PI glue layer 812 is disposed on two opposite sides of the glass substrate 81 and has the same height as the pins 811 to maintain the flatness of the glass substrate 81.
A plurality of solder balls 84 may be soldered to the leads 811 on the other surface of the glass substrate 81 to electrically connect the solder balls 84 to external devices.
The beneficial effects of this embodiment are: packaging of multiple chips is achieved by soldering at least two devices to the same glass substrate.
The foregoing is only the embodiments of the present application, and not the patent scope of the present application is limited by the foregoing description, but all equivalent structures or equivalent processes using the contents of the present application and the accompanying drawings, or directly or indirectly applied to other related technical fields, which are included in the patent protection scope of the present application.

Claims (10)

1. The packaging method of the chip is characterized by comprising the following steps of:
providing a glass substrate with pins on two sides;
welding a device on a pin on one surface of the glass substrate, and enabling a bonding pad on the device to be electrically connected with the pin on the glass substrate;
and carrying out plastic packaging on the glass substrate and the device by using a plastic packaging material, exposing one surface of the glass substrate, which is away from the device, so as to package the side of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate.
2. The method of packaging a chip according to claim 1, wherein the step of providing a glass substrate with pins provided on both sides includes:
providing a flat glass substrate;
manufacturing a through hole on the glass substrate;
electroplating copper in the through hole to form a hole copper column;
and manufacturing pins at positions of the opposite sides of the glass substrate corresponding to the hole copper columns, so that the pins of the opposite sides of the glass substrate are conducted through the hole copper columns.
3. The method of packaging a chip of claim 2, wherein the step of fabricating pins at positions on opposite sides of the glass substrate corresponding to the hole copper pillars further comprises:
coating PI glue on two opposite sides of the glass substrate;
exposing and developing the PI glue to expose the surface of the hole copper column;
and electroplating copper on the surface of the hole copper column to form the pin.
4. The method of packaging a chip of claim 2, wherein the step of fabricating a via hole in the glass substrate comprises:
manufacturing a plurality of through holes on the glass substrate;
electroplating copper within each of the vias to form the Kong Tongzhu;
manufacturing pins at positions of two opposite sides of the glass substrate corresponding to the hole copper columns;
cutting the glass substrate to obtain the glass substrate with the pins of the preset number; the number of the pins corresponds to the number of the hole copper columns.
5. The method of packaging a chip according to claim 1, wherein the step of using a molding compound to mold the glass substrate and the device, exposing a surface of the glass substrate facing away from the device, so as to package the side wall of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate comprises:
placing the other surface of the glass substrate on a carrier plate;
using plastic packaging material to carry out plastic packaging on the glass substrate and the device on the surface of the carrier plate so as to package the side wall of the glass substrate and the device together;
and removing the carrier plate to expose one surface of the glass substrate, which is away from the device.
6. The method of packaging a chip according to claim 5, wherein the step of using a molding compound to mold the glass substrate and the device, exposing a surface of the glass substrate facing away from the device, so as to package the side wall of the glass substrate and the device together, and leading out a bonding pad on the device through a pin on the glass substrate, further comprises:
the other surfaces of the glass substrates are placed on the carrier plate at intervals;
using plastic packaging material to carry out plastic packaging on the glass substrate and the device on the surface of the carrier plate so as to package the side wall of the glass substrate and the device together;
removing the carrier plate to expose one surface of the glass substrate, which is away from the device;
and cutting along the middle positions of two adjacent glass substrates to obtain a plurality of independent single-chip packages which are packaged together by the side walls of the glass substrates and the devices.
7. The method of claim 6, wherein the step of removing the carrier plate to expose a side of the glass substrate facing away from the device further comprises:
and cutting along the middle of the two spaced glass substrates to obtain a plurality of mutually independent double-chip packaging bodies which are packaged together by the side walls of the glass substrates and the devices.
8. The method of packaging a chip according to claim 1, wherein after the step of using a molding compound to mold the glass substrate and the device and exposing a surface of the glass substrate facing away from the device to package the side edge of the glass substrate and the device together and lead out a bonding pad on the device through a pin on the glass substrate, the method further comprises:
and manufacturing a ball-planting on a pin on one surface of the glass substrate, which is away from the device, so as to lead out a bonding pad on the device through the ball-planting.
9. The method of packaging a chip of claim 1, wherein the device is a radio frequency device. The plastic package material is epoxy resin.
10. A package, the package comprising:
the device comprises a glass substrate, wherein pins are arranged on two opposite surfaces of the glass substrate;
the device is provided with a bonding pad, and the device is welded on a pin on one side of the glass substrate through the bonding pad;
and the plastic packaging material encapsulates the side wall of the glass substrate and the device, and exposes one surface of the glass substrate, which is away from the device.
CN202211091858.4A 2022-09-07 2022-09-07 Packaging method of chip and packaging piece Pending CN116313822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211091858.4A CN116313822A (en) 2022-09-07 2022-09-07 Packaging method of chip and packaging piece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211091858.4A CN116313822A (en) 2022-09-07 2022-09-07 Packaging method of chip and packaging piece

Publications (1)

Publication Number Publication Date
CN116313822A true CN116313822A (en) 2023-06-23

Family

ID=86827430

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211091858.4A Pending CN116313822A (en) 2022-09-07 2022-09-07 Packaging method of chip and packaging piece

Country Status (1)

Country Link
CN (1) CN116313822A (en)

Similar Documents

Publication Publication Date Title
US7344915B2 (en) Method for manufacturing a semiconductor package with a laminated chip cavity
TWI426587B (en) Chip scale package and fabrication method thereof
CN109494202B (en) Semiconductor chip packaging method and packaging structure
US7679178B2 (en) Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
CN103730429B (en) Encapsulating structure
US20100288541A1 (en) Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
JP2003078106A (en) Chip-stacked package and its manufacturing method
KR20090034081A (en) Stack-type semiconductor package apparatus and manufacturing method the same
US20120299199A1 (en) Stacked wafer level package having a reduced size
CN109509727B (en) Semiconductor chip packaging method and packaging structure
JP2001035998A (en) Wafer level stack package and its manufacturing method
US9299650B1 (en) Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
WO2020253146A1 (en) Method for packaging chip
TWI534951B (en) Semiconductor package substrate, package system using the same and method for manufacturing thereof
CN112768437B (en) Multilayer stack packaging structure and preparation method thereof
JP2000124354A (en) Chip-size package and its manufacture
US20230352373A1 (en) Three dimensional package for semiconductor devices and external components
US7727861B2 (en) Method and device for contacting semiconductor chips
CN113161335B (en) Heart rate module packaging structure, preparation method thereof and wearable electronic device
CN116313822A (en) Packaging method of chip and packaging piece
JP2004006670A (en) Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
CN215266271U (en) Front and back chip integrated packaging structure based on copper foil carrier plate
CN211428156U (en) Packaging structure for reducing three-dimensional heterogeneous physical connection
CN113299564A (en) Packaging structure of board-level fan-out flexible packaging substrate and preparation method thereof
CN104517895B (en) Semiconductor package and fabrication method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination