CN115280495A - 功率模块 - Google Patents

功率模块 Download PDF

Info

Publication number
CN115280495A
CN115280495A CN202180019999.2A CN202180019999A CN115280495A CN 115280495 A CN115280495 A CN 115280495A CN 202180019999 A CN202180019999 A CN 202180019999A CN 115280495 A CN115280495 A CN 115280495A
Authority
CN
China
Prior art keywords
power module
additional circuit
circuit carrier
substrate
rigid insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180019999.2A
Other languages
English (en)
Inventor
奥勒·米尔费尔德
克劳斯·奥勒森
马蒂亚斯·贝克
霍尔格·乌尔里希
马丁·贝克尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Danfoss Silicon Power GmbH
Original Assignee
Danfoss Silicon Power GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power GmbH filed Critical Danfoss Silicon Power GmbH
Publication of CN115280495A publication Critical patent/CN115280495A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

披露了一种包括安装在基板(4)上的刚性绝缘衬底(10)的功率模块(2)。附加电路载体(6，8)与该刚性绝缘衬底(10)相邻地安装在该基板(4)上。该附加电路载体(6，8)的刚度小于该刚性绝缘衬底(10)的刚度。

Description

功率模块
技术领域
本发明总体上涉及一种功率模块。本发明更特别地涉及一种包括安装在基板上的刚性绝缘衬底的功率模块。
背景技术
直接敷铜(DBC)衬底因其良好的导热性而广泛用于功率模块中。DBC衬底由陶瓷层和键合到该陶瓷层的一侧或两侧的铜片构成。为了提供对DBC衬底的充分冷却，通常例如通过将DBC衬底的底部铜层焊接到散热器上来将衬底附接到散热器。
DBC衬底被选择为功率模块中裸半导体芯片的电路材料是因为这种衬底可以高效地消散来自半导体的废热并延长模块的使用寿命。然而，工艺和生产工程师最初必须构建这些模块。这项任务需要小心地接合和连接多个部件，以提供所需的电、热、化学和机械功能。
尽管DBC衬底在其消散废热能力方面具有优势，但通常并不是整个功率模块都需要这种能力。事实上，在发热较少或不存在发热的那些区域中，所需的废热消散能力非常低。由于DBC衬底较为昂贵，因此期望能够提供适合于构建功率模块的替代方案。
因此，本发明的目的在于提供减少或甚至消除现有技术的上述缺点的功率模块。本发明的一个目的是提供比现有技术的功率模块更便宜的功率模块。
发明内容
本发明的目的可以由如权利要求1所述的功率模块实现。优选实施例在从属权利要求中定义、在以下描述中解释、并且在附图中展示。
根据本发明的功率模块是一种包括安装在基板上的刚性绝缘衬底的功率模块，其中，附加电路载体与刚性绝缘衬底相邻地安装在基板上，其中，附加电路载体的刚度小于刚性绝缘衬底的刚度。
由此，可以提供一种比现有技术的功率模块更便宜的功率模块。可以通过应用附加电路载体减小刚性绝缘衬底的面积来降低功率模块的成本。
刚性绝缘衬底和附加电路载体可以通过使用任何合适的附接方法附接到基板。可以使用焊料层、烧结层或胶水(导热和/或导电)将刚性绝缘衬底和附加电路载体电连接和机械紧固到基板。同样，可以通过使用焊料层、烧结层或胶水(导热和/或导电)将功率部件电连接和机械紧固到刚性绝缘衬底。
在一个实施例中，刚性绝缘衬底是陶瓷绝缘衬底。
在优选实施例中，刚性绝缘衬底是绝缘金属衬底。
可以有利的是，刚性绝缘衬底是DBC衬底。
在一个实施例中，刚性绝缘衬底是直接敷铝(DBA)衬底。
在一个实施例中，刚性绝缘衬底是活性金属钎焊(AMB)衬底。
在一个实施例中，附加电路载体电连接到布置在刚性绝缘衬底上的一个或多个部件。
在一个实施例中，附加电路载体电连接到布置在DBC衬底上的一个或多个部件。
可以有利的是，附加电路载体在操作期间具有低于200W/cm2的功耗。由此，可以实现对附加电路载体的充分冷却。
在一个实施例中，安装在附加电路载体上或使用该附加电路载体的部件在操作期间具有低于100W/cm2的功耗。由此，可以更容易实现对附加电路载体的充分冷却。
在一个实施例中，附加电路载体在操作期间具有低于50W/cm2的功耗。
在一个实施例中，附加电路载体在操作期间具有低于25W/cm2的功耗。
在一个实施例中，附加电路载体是印刷电路板(PCB)。
在一个实施例中，PCB是由编织玻璃纤维布和具有阻燃性的环氧树脂粘合剂构成的玻璃增强环氧树脂层压材料。这种PCB有时被称为FR-4(或FR4)。
可以有利的是，附加电路载体是柔性电路板。由此，柔性电路板可以以柔性电路板延伸出功率模块壳体的构型布置。这种实施例允许将柔性电路板连接到相邻的PCB(例如，其上驱动电路提供信号以驱动功率模块中的开关的PCB)。
使用柔性电路板是有利的，因为柔性电路板可以以该柔性电路板伸出功率模块的壳体的构型布置，无需使用插头或插口。
在一个实施例中，附加电路载体从功率模块的壳体伸出。
在一个实施例中，附加电路载体是从功率模块的壳体伸出的柔性电路板。
在一个实施例中，附加电路载体直接键合在基板上。将附加电路载体(例如，柔性电路板)直接安装在基板上使得可以在柔性电路的部分上布置部件，以创建完整的驱动电路或驱动电路的一部分。
在一个实施例中，DBC衬底覆盖的面积小于基板面积的90％。由此，附加电路载体可以构成基板(顶侧)的面积的至少10％。
在一个实施例中，DBC衬底覆盖的面积小于基板(顶侧)面积的80％。
在一个实施例中，DBC覆盖的面积小于基板(顶侧)面积的70％。
在一个实施例中，DBC衬底覆盖的面积小于基板(顶侧)面积的60％。
在一个实施例中，DBC衬底覆盖的面积小于基板(顶侧)面积的50％。
可以有利的是，附加电路载体比DBC衬底薄。通过应用比DBC衬底薄的附加电路载体，可以降低功率模块的成本。
可以有利的是，该附加电路载体包括至少部分地沿DBC衬底的第一侧和第二侧延伸的L形或C形部分。
在一个实施例中，附加电路载体包括E形部分。可以有益的是，E形附加电路载体至少部分地沿DBC衬底的第一侧和第二侧延伸。
在一个实施例中，附加电路载体是L形的。
在一个实施例中，附加电路载体是C形的。
在一个实施例中，附加电路载体包括设置在附加电路载体的远端中的一个或多个连接结构。
在一个实施例中，附加电路载体包括设置在附加电路载体从功率模块的壳体伸出的部分的远端中的一个或多个连接结构。
在一个实施例中，附加电路载体是柔性电路板，该柔性电路板包括设置在柔性电路板从功率模块的壳体伸出的部分的远端中的一个或多个连接结构。
在一个实施例中，附加电路载体的至少一部分是非平面的。
术语“非平面”意指“不位于或不能够被限制在单个平面内”。
在一个实施例中，非平面部分的至少一部分是弧形部分。
可以有利的是，附加电路载体包括多层。
附图说明
从下文中给出的详细描述中，本发明将被更充分地理解。附图仅通过图示的方式给出，因此，它们不是对本发明的限制。在附图中：
图1A示出了根据本发明的功率模块的示意性俯视图；
图1B示出了根据本发明的另一个功率模块的示意性俯视图；
图1C示出了根据本发明的功率模块的截面图；
图2A示出了根据本发明的功率模块的示意性俯视图；
图2B示出了根据本发明的另一个功率模块的示意性俯视图；
图2C示出了根据本发明的又另一个功率模块的示意性俯视图；
图3A示出了根据本发明的功率模块的一部分的截面图，该部分；
图3B示出了根据本发明的功率模块的一部分的截面图，该部分包括柔性电路板；
图3C示出了根据本发明的功率模块的截面图；
图4示出了根据本发明的功率模块模制件的边缘的俯视图；
图5示出了根据本发明的功率模块的截面图；以及
图6示出了根据本发明的功率模块的截面图。
具体实施方式
现在出于展示本发明的优选实施例的目的而详细参考附图，图1A中展示了本发明的功率模块2。
图1A是根据本发明的功率模块2的示意性俯视图。功率模块2包括基板4和附接至其的PCB 6。功率模块2还包括多个刚性绝缘衬底10。刚性绝缘衬底10可以形成为直接敷铜(DBC)衬底。刚性绝缘衬底10被PCB 6的一部分单独间隔开并包围。包围。功率模块2包括靠近功率模块2外围布置的信号连接器16。
当将PCB 6的表面积与刚性绝缘衬底10的表面积进行比较时，可以看出PCB 6的表面积显著大于刚性绝缘衬底10的表面积。由于刚性绝缘衬底10较为昂贵，因此可以通过应用PCB 6代替仅使用刚性绝缘衬底10覆盖基板4来降低功率模块2的总成本。
图1B展示了根据本发明的另一个功率模块2的示意性俯视图。功率模块2包括基板4，在该基板上附接有柔性电路板8。功率模块2还包括两个彼此分隔开的刚性绝缘衬底10。刚性绝缘衬底10形成为DBC衬底。信号连接器16靠近功率模块2外围布置。
柔性电路板8的表面积基本上相当于刚性绝缘衬底10的表面积。由此，使用柔性电路板8可以降低功率模块2的总成本。
图1C展示了根据本发明的功率模块2的截面图。功率模块2包括基板4。两个刚性绝缘衬底10安装在基板4上。刚性绝缘衬底10通过接合材料14固定到基板4，该接合材料可以是焊料层、烧结层或胶水(导热和/或导电)。
设置有轨道32′的柔性电路板8安装在两个刚性绝缘衬底10之间的基板4上。设置有轨道32、32′的PCB 6与两个刚性绝缘衬底10中的每一个相邻放置。柔性电路板8以及PCB6通过使用接合材料14固定到基板4。接合材料14可以是焊料层、烧结层或胶水。半导体12放置在两个刚性绝缘衬底10中的每一个的顶部上。刚性绝缘衬底10可以是DBC衬底。
图2A展示了根据本发明的功率模块2的示意性俯视图。功率模块2包括布置在封装(壳体)内的基板4，该封装具有用虚线指示的边缘44。
功率模块2设置有从功率模块模制件的边缘44伸出的三个功率连接器38。功率连接器38中的两个功率连接器电连接到刚性绝缘衬底(例如，DBC衬底)10。然而，布置在右侧的功率连接器38电连接到结构(板)42。结构42可以是刚性绝缘衬底。
由于没有功率部件布置在结构42上，因此不需要很高的消散废热能力。因此，结构42可以是PCB或柔性电路板。
半导体12放置在布置在结构42左侧的每个刚性绝缘衬底10上。引线键合40用于将半导体12电连接到相邻的刚性绝缘衬底10或结构42。引线键合40还用于将半导体12电连接到柔性电路板8的轨道。
柔性电路板8包括从功率模块模制件的边缘44伸出的部分。由此，柔性电路板8构成具有“插头”46功能的结构，该“插头”可从功率模块模制件44的外部触及。“插头”46可以优选地包括控制连接和感测连接二者。使用这种从模块伸出的柔性电路板允许有机会进行现有技术模块不可实现的连接，在现有技术模块中，必须靠近模块的模制表面来进行连接。在本发明的这个实施例中，可以在距模块的模制表面一定距离处进行连接，使连接能够在不同的平面上或成一定角度进行，而这对于较短的刚性连接来说是不可实现的。与模块的模制表面的距离也可以在相关情况下改善爬电或间隙限制。
图2B展示了根据本发明的另一个功率模块2的示意性俯视图。功率模块2包括基板4和布置在基板4上的柔性电路板8。两个对称布置的T形PCB 6和布置在其间的细长矩形PCB6。此外，功率模块2包括四个刚性绝缘衬底10。
图2C展示了根据本发明的又另一个功率模块2的示意性俯视图。功率模块2包括基板4，在该基板上附接有C形柔性电路板8。功率模块2包括两个布置在中心的刚性绝缘衬底10。
图3A展示了根据本发明的功率模块的一部分的截面图，该部分包括附接到基板4的刚性绝缘衬底10。功率模块包括基板4和通过诸如焊料层、烧结层或胶水等接合材料14固定在该基板上的刚性绝缘衬底10。刚性绝缘衬底10包括夹设在下金属板36与上金属板36′之间的绝缘体34。半导体12通过接合材料14(例如，焊料层、烧结层或胶水)附接到上金属板36′的顶侧。
图3B展示了根据本发明的功率模块的一部分的截面图，该部分包括通过接合材料14(例如，焊料层、烧结层或胶水)附接到基板4的柔性电路板8。在柔性电路板8的顶部设置有多个分隔开的金属轨道32、32′。
图3C展示了根据本发明的功率模块的一部分的截面图，该部分包括基板4和通过接合材料14(其可以是焊料层、烧结层或胶水)附接到该基板的PCB 6。PCB 6包括夹设在金属层36与三个金属轨道32、32′之间的绝缘体34。
图4展示了功率模块的一部分的俯视图，该部分包括替代性外部连接。可以看出，功率模块包括从功率模块模制件的边缘44伸出的控制和感测连接48。感测连接48电连接到布置在功率模块的基板4上的柔性电路板8。
图5示出了根据本发明的功率模块的截面图。功率模块2包括布置在模制封装(壳体)49内的基板4。设置有轨道32、32’的柔性电路板8安装在基板4上。柔性电路板8通过使用接合材料14固定到基板4。接合材料14可以是焊料层、烧结层或胶水。柔性电路板8包括从功率模块模制件49的边缘伸出的部分。由此，柔性电路板8构成具有“插头”46功能的结构，该“插头”可从功率模块模制件49的外部触及。“插头”46可以优选地包括控制连接和感测连接二者。
图6示出了在图2A所示的实施例中的根据本发明的功率模块的截面图并且表示了沿图2A中标记为“VI-VI”的线的截面。功率模块2包括布置在模制封装(壳体)49内的基板4。功率模块2设置有从功率模块模制件49伸出的功率连接器38。功率连接器38电连接到刚性绝缘衬底(例如，DBC衬底)10。半导体12放置在刚性绝缘衬底10上。引线键合40用于将半导体12电连接到柔性电路板8的轨道32’。柔性电路板8包括从功率模块模制件49的边缘伸出的部分。由此，柔性电路板8构成具有“插头”46功能的结构，该“插头”可从功率模块模制件44的外部触及。“插头”46可以优选地包括控制连接和感测连接二者。
附图标记清单
2 功率模块
4 基板
6 印刷电路板(PCB)
8 柔性电路板
10 刚性绝缘衬底(例如，直接敷铜(DBC)衬底)
12 半导体
14 接合材料
16 信号连接器
18，18′ 端部部分
20，22 控制引脚
24，26 栅极驱动器
28 部件
32，32′ 轨道
34 绝缘体
36，36′ 金属
38 功率连接器
40 引线键合
42 结构
44 功率模块模制件的边缘
46 插头
48 控制和感测连接
49 模制件

Claims (10)

1.一种包括安装在基板(4)上的刚性绝缘衬底(10)的功率模块(2)，其特征在于，附加电路载体(6，8)与该刚性绝缘衬底(10)相邻地安装在该基板(4)上，其中，该附加电路载体(6，8)的刚度小于该刚性绝缘衬底(10)的刚度。
2.根据权利要求1所述的功率模块(2)，其特征在于，该附加电路载体(6，8)是印刷电路板(PCB)。
3.根据权利要求1所述的功率模块(2)，其特征在于，该附加电路载体(6，8)是柔性电路板(8)。
4.根据权利要求1所述的功率模块(2)，其特征在于，该附加电路载体(6，8)直接键合在该基板(4)上。
5.根据前述权利要求之一所述的功率模块(2)，其特征在于，该DBC衬底(10)覆盖的面积小于该基板(4)面积的90％。
6.根据前述权利要求之一所述的功率模块(2)，其特征在于，该附加电路载体(6，8)比该DBC衬底(10)薄。
7.根据前述权利要求之一所述的功率模块(2)，其特征在于，该附加电路载体(6，8)包括作为至少部分地沿该DBC衬底(10)的第一侧和第二侧延伸的L形或C形部分的部分。
8.根据前述权利要求之一所述的功率模块(2)，其特征在于，该附加电路载体(6，8)包括设置在该附加电路载体(6，8)远端中的一个或多个连接结构。
9.根据前述权利要求之一所述的功率模块(2)，其特征在于，该附加电路载体(6，8)的至少一部分是非平面的。
10.根据前述权利要求之一所述的功率模块(2)，其特征在于，该附加电路载体(6，8)包括多层。
CN202180019999.2A 2020-03-09 2021-03-08 功率模块 Pending CN115280495A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102020106385.7 2020-03-09
DE102020106385.7A DE102020106385A1 (de) 2020-03-09 2020-03-09 Leistungsmodul
PCT/EP2021/055804 WO2021180660A1 (en) 2020-03-09 2021-03-08 Power module

Publications (1)

Publication Number Publication Date
CN115280495A true CN115280495A (zh) 2022-11-01

Family

ID=74874798

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180019999.2A Pending CN115280495A (zh) 2020-03-09 2021-03-08 功率模块

Country Status (4)

Country Link
US (1) US20230114396A1 (zh)
CN (1) CN115280495A (zh)
DE (1) DE102020106385A1 (zh)
WO (1) WO2021180660A1 (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3206717B2 (ja) 1996-04-02 2001-09-10 富士電機株式会社 電力用半導体モジュール
CN103262238B (zh) * 2010-09-24 2016-06-22 半导体元件工业有限责任公司 电路装置
WO2013001999A1 (ja) * 2011-06-29 2013-01-03 日本碍子株式会社 大容量モジュールの周辺回路用の回路基板、及び当該回路基板を用いる周辺回路を含む大容量モジュール
DE112012006007T5 (de) * 2012-03-09 2014-11-20 Mitsubishi Electric Corp. Halbleitermodul

Also Published As

Publication number Publication date
WO2021180660A1 (en) 2021-09-16
US20230114396A1 (en) 2023-04-13
DE102020106385A1 (de) 2021-09-09

Similar Documents

Publication Publication Date Title
KR102332362B1 (ko) 초박형 임베디드 반도체 소자 패키지 및 그 제조 방법
KR0169265B1 (ko) 반도체장치
US6972479B2 (en) Package with stacked substrates
JP5106519B2 (ja) 熱伝導基板及びその電子部品実装方法
KR100752239B1 (ko) 전력 모듈 패키지 구조체
JP2002537655A (ja) リードレスキャリア設計および構造
JP3466329B2 (ja) 半導体パワーモジュール
US6882538B1 (en) Intelligent power module
US8174839B2 (en) Mounting structure of semiconductor package and plasma display device having the same
CN1979836A (zh) 半导体装置以及使用该半导体装置的电子控制装置
JP5975856B2 (ja) 電力用半導体装置
JP4882562B2 (ja) 熱伝導基板とその製造方法及び電源ユニット及び電子機器
US7688591B2 (en) Electronic-component-mounting board
JP2004063604A (ja) パワーモジュール及びこのパワーモジュールを用いた冷蔵庫
US6011692A (en) Chip supporting element
KR101115403B1 (ko) 발광 장치
CN115280495A (zh) 功率模块
JP2007134572A (ja) パワーモジュール
US6989590B2 (en) Power semiconductor device with a control circuit board that includes filled through holes
JPH10173095A (ja) プラスチックピングリッドアレイパッケージ
JP4527292B2 (ja) 半導体パワーモジュール
KR20030063178A (ko) 전기 장치
US20240114614A1 (en) Thermal Conduction - Electrical Conduction Isolated Circuit Board with Ceramic Substrate and Power Transistor Embedded
US20230411334A1 (en) Power module for high-frequency use and method for manufacturing the same
JP2008021817A (ja) 熱伝導基板とその製造方法及び電源ユニット及び電子機器

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination