CN115279014A

CN115279014A - Printed circuit board structure and preparation method thereof

Info

Publication number: CN115279014A
Application number: CN202210695867.8A
Authority: CN
Inventors: 吴玲丽; 黄燕清
Original assignee: Changzhou Pc Specialties Co ltd
Current assignee: Changzhou Pc Specialties Co ltd
Priority date: 2022-06-20
Filing date: 2022-06-20
Publication date: 2022-11-01

Abstract

The invention relates to the technical field of integrated circuits, and provides a printed circuit board structure and a preparation method thereof, wherein the printed circuit board structure comprises a silicon through hole and a glass through hole, wherein the silicon through hole is provided with a dense wiring area and a non-dense wiring area, the silicon through hole is provided with a groove, and the dense wiring area and the non-dense wiring area are exposed out of the groove; the glass through holes are distributed with dense wiring areas and non-dense wiring areas, the dense wiring areas are distributed with a first dense wiring area, a second dense wiring area and a third dense wiring area, and the first dense wiring area, the second dense wiring area and the third dense wiring area are distributed with dense wiring area pads and dense wiring; the silicon through hole dense wiring area is vertically corresponding to the glass through hole dense wiring area, and the silicon through hole non-dense wiring area is vertically corresponding to the glass through hole non-dense wiring area. The structure integrates the advantages of fan-out wiring of the silicon through holes and the glass through holes, partition fan-out wiring is achieved, meanwhile, signal lines are shortened through an embedded design, loss is reduced, and electromagnetic interference of devices is reduced.

Description

Printed circuit board structure and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a printed circuit board structure and a manufacturing method thereof.

Background

In the prior art, through silicon via technology is often adopted, for example, patent of "through silicon via design, three-dimensional integrated circuit and manufacturing method thereof" with patent number CN110534507B of taiji cheng electronic publication, IC chips are designed in a laminated manner by Through Silicon Via (TSV) design, so that the density of wiring is increased and the power consumption is reduced.

Hua was published in 2022 at 04/05 by CN114287057a "a chip stack package and terminal device", which has limitations: the chips are interconnected in a staggered manner, heat dissipation of the chips is facilitated, but the interconnection of the two chips perpendicular to the structure is limited by processing density, the structure has high application value in analog chips (large lines), but is not suitable for interconnection of digital chips (nm-level line width), the digital chips with two nm-level line widths are directly interconnected, and great challenge is caused to the processing of RDL layers. Meanwhile, the two chips are staggered, and the combination stress problem (easy fracture) exists at the joint of the RDL layer and the digital chip due to the heterogeneous design.

Chinese electron science and technology group corporation fifty eight research institute patent publication No. CN107393900B "embedded TSV adapter plate structure of extremely multi-layer wiring" discloses that: the wiring adapter plate with extremely multi-layer wiring is embedded in the adapter plate body, so that the number of wiring layers of the adapter plate body can be increased, the defect that the TSV adapter plate body is limited by the number of RDL (remote desktop library) wiring layers is overcome, and the application requirement of high-performance and high-integration-density micro-system packaging can be met.

At present, two main problems exist in the TSV adapter plate: 1) The cost is high, a silicon etching process is adopted for manufacturing a Through Silicon Via (TSV), and then the TSV needs technologies such as an oxidation insulating layer and a thin wafer; 2) The electrical property is poor, the silicon material belongs to a semiconductor material, when the transmission line transmits signals, the signals and the substrate material have a strong electromagnetic coupling effect, and an eddy current phenomenon is generated in the substrate, so that the signal integrity (insertion loss, crosstalk and the like) is poor. As a possible material to replace silicon-based interposer, a Through Glass Via (TGV) interposer is becoming a research hotspot of semiconductor enterprises and scientific research institutes at home and abroad due to its many advantages. Compared with a silicon-based adapter plate, the glass adapter plate has the following advantages that: 1) The cost is low; 2) Excellent high-frequency electrical characteristics; 3) The large-size ultrathin glass substrate is easy to obtain; 4) The process flow is simple. However, unlike TSV, TGV has a large pore diameter, and most of the TGV is through holes, so that the electroplating time is long and the cost is high; on the other hand, unlike silicon materials, glass has a smooth surface and has poor adhesion to common metals (such as Cu), which is likely to cause delamination between the glass substrate and the metal layer, resulting in curling and even peeling of the metal layer.

Disclosure of Invention

In order to overcome the defects, the invention provides a printed circuit board structure, which solves the technical problems of easy breakage of combined stress, limitation of fan-out of fine line wiring, larger diameter of TGV (triglycidyl isocyanurate) in the prior art and limitation of wiring density in the Huacheng patent CN 114287057A.

In a first aspect, the present invention provides a printed circuit board structure, which includes:

including through-silicon via, glass through-hole, insulating layer, its characterized in that: the through silicon via is distributed with a through silicon via dense wiring area and a through silicon via non-dense wiring area, the through silicon via is formed with a through silicon via groove, and the through silicon via dense wiring area and the through silicon via non-dense wiring area are exposed out of the through silicon via groove.

The glass through hole is distributed with a glass through hole dense wiring area and a glass through hole non-dense wiring area, the glass through hole dense wiring area is distributed with a glass through hole first dense wiring area, a glass through hole second dense wiring area and a glass through hole third dense wiring area, and the glass through hole first dense wiring area, the glass through hole second dense wiring area and the glass through hole third dense wiring area are distributed with a glass through hole dense wiring area pad and a glass through hole dense wiring;

the dense silicon through hole wiring area is vertically corresponding to the dense glass through hole wiring area, and the non-dense silicon through hole wiring area is vertically corresponding to the non-dense glass through hole wiring area.

And the insulating layer is used for plastically packaging the silicon through hole and the glass through hole.

The dense wiring area of through-silicon via distributes and has first dense wiring district, second dense wiring district, third dense wiring district and fourth dense wiring district, first dense wiring district second dense wiring district, third dense wiring district and fourth dense wiring district form the first pad of dense wiring district, dense wiring district second pad and dense wiring district wiring.

And the active device is bonded with the first pad of the dense wiring area and the second pad of the dense wiring area, and fan-out wiring is wired through the dense wiring area.

Preferably, the active devices are stacked such that at least one of the active devices has a lead facing upward, the lead being exposed from the insulating layer.

The first dense wiring area of the glass through holes vertically corresponds to the first dense wiring area of the silicon through holes; the glass through hole second dense wiring area is vertically corresponding to the first dense wiring area of the through silicon via dense wiring area.

The active device in the silicon through hole dense wiring area fans out wiring to the glass through holes from the pins facing upwards, the pads in the glass through hole dense wiring area and the glass through hole dense wiring.

The silicon through hole non-dense wiring area is distributed with a first non-dense wiring area and a second non-dense wiring area, the first non-dense wiring area and the second non-dense wiring area form a first pad of the non-dense wiring area, a second pad of the non-dense wiring area, a third pad of the non-dense wiring area, a fourth pad of the non-dense wiring area and non-dense wiring area wiring.

The first non-dense wiring area is provided with a second bonding pad bonding passive device in the non-dense wiring area, the second non-dense wiring area is provided with a third bonding pad bonding passive device in the non-dense wiring area, and the passive devices are electrically interconnected through the non-dense wiring area.

The second bonding pads of the non-dense wiring areas of the first non-dense wiring areas are conducted with the glass through holes through solder balls, and the third bonding pads of the non-dense wiring areas of the second non-dense wiring areas are conducted with the glass through holes through solder balls.

Radiating fins are arranged in the silicon through hole non-dense wiring area of the silicon through hole groove, each radiating fin comprises a radiating fin cavity and a radiating fin body, each radiating fin body comprises a radiating fin body substrate and a radiating fin body protruding part, and each radiating fin body protruding part extends towards the outside of the silicon through hole.

Preferably, the heat dissipation fins are vertically stacked, and the projections of the overlapped heat dissipation fin cavities can cover the through-silicon-via dense wiring region.

The radiating fin body is fixed by the insulating layer in a plastic package mode and is abutted to the through silicon hole and the through glass hole, and the protruding portion of the radiating fin body is exposed out of the insulating layer.

In a second aspect, the present invention provides a method for manufacturing a printed circuit board structure, specifically comprising:

s1: providing a silicon-based wafer, performing mask protection on a non-etching area, etching by adopting the existing etching process to form the silicon through hole groove, and grinding and polishing;

s2: performing mask protection on the silicon through hole groove, and processing layer by adopting the existing silicon through hole processing technology and the conventional CMOS process to form non-dense wiring area wiring;

s3: removing the mask, performing mask protection on the formed non-dense wiring region, and performing deep processing by adopting the existing through silicon via processing technology and the conventional CMOS process or the stacked CMOS process to form dense wiring region wiring with the aspect ratio of 5-15;

s4: carrying out pad ball planting or additive method on the through silicon via with the formed offset to form a copper column and a salient point, bonding the active device and the passive device with the through silicon via, encapsulating and plastically packaging the insulating layer, and leveling and exposing the solder ball, the copper column or the salient point required by the conduction of the active device by a grinding plate;

s5: performing deep processing on the glass through hole by adopting at least one of a photosensitive glass method, a plasma etching method, an electrochemical method or a laser induced etching method, and forming an RDL layer by adopting a conventional CMOS process;

s6: and (4) aligning and calibrating, namely pressing the glass through hole formed in the step (S5) to be butted with a silicon through hole, performing interconnection and conduction through at least one of a solder ball, a copper column or a salient point, and performing secondary glue filling and plastic packaging.

In a third aspect, the present invention provides a package module manufactured by the above printed circuit board structure, which includes:

1) The carrier plate is electrically connected with the glass through hole of the printed circuit board structure through the solder ball;

2) The active device is electrically connected with pads of the glass through hole dense wiring areas of the first glass through hole dense wiring area, the second glass through hole dense wiring area and the third glass through hole dense wiring area, and fans out wiring to the glass through holes;

3) The insulating layer is used for plastically packaging the printed circuit board structure, the carrier plate and the active device.

Preferably, the heat dissipation fins can be placed between the printed circuit board structure and the carrier plate, so that the heat dissipation efficiency of the side edge is increased.

Preferably, the insulating layer is at least one of polypropylene, epoxy resin and ABF.

The invention provides a printed circuit board structure, which has the following beneficial effects:

(1) Forming a through silicon via with a offset structure, and forming a dense wiring area in the through silicon via groove, wherein the dense wiring area is used for the electrical connection of an active device and is beneficial to the fan-out of a fine circuit of the active device;

(2) Forming a through silicon via with a step structure, forming a non-dense wiring area in the through silicon via groove, wherein the non-dense wiring area is used for electrical connection of a passive device, and realizing sectored fan-out wiring;

(3) Forming a through silicon via with a step structure, forming an intensive wiring area in a through silicon via groove, and shortening an interconnection signal line, which is beneficial to reducing the signal loss of an active device;

(4) The through silicon via forming the offset structure is beneficial to the embedding of devices, reduces the thickness deviation of the whole plate brought by surface mounting, has the size exceeding the tolerance and reduces the electromagnetic interference among the devices;

(5) The silicon through hole forming the offset structure can design the vertical distance of the upper and lower stacked active devices according to the specification requirement of wiring fan-out of the active devices, adjust the size of the offset, and can embed and stack devices with different sizes according to the size of the offset, thereby improving the integration density of the devices;

(6) The CMOS in the prior art is adopted to form the silicon through holes with dense wiring and small through hole diameters, the glass through holes with limited dense wiring and large through hole diameters are pressed, the dense wiring areas of the glass through holes are aligned and conducted with the dense wiring areas of the silicon through holes, the wiring can be fanned out to the micron level layer by layer, and meanwhile, the glass through holes are limited in dense wiring and large in through hole diameters and can be bonded to conduct simulation chips of large circuits;

(7) In the cavity structure formed by the silicon through hole and the glass through hole, cross-layer conduction can be realized through solder balls and copper columns, and heat dissipation fins can also be arranged, so that the heat dissipation efficiency of the side edge of the printed circuit board structure in the X-Y horizontal direction is improved.

Drawings

FIG. 1 is a front view of a through silicon via structure according to an embodiment;

FIG. 2 is a front view of a through silicon via structure of a mounted device according to an embodiment;

FIG. 3 is a front view of another through-silicon-via structure of a mounted device according to an embodiment;

FIG. 4 is a front view of a through-hole of a second glass according to the embodiment;

FIG. 5 is a front view of a second printed circuit board structure of the embodiment;

FIG. 6 is a front view of an electrical connection carrier of a third PCB structure of the embodiment;

FIG. 7 is a front view of a package module with a three-PCB structure according to an embodiment;

FIG. 8 is another front view of the package module with three printed circuit board structures according to the embodiment;

FIG. 9 is a front view of a package module with a four-PCB structure according to an embodiment;

FIG. 10 is a top view of heat dissipation fins in a four-printed circuit board structure according to an embodiment;

FIG. 11 is a top view of a stacked heat sink fin in a four-printed circuit board configuration according to an embodiment;

fig. 12 is a left side view of the heat dissipation fins in the structure of the four-printed circuit board according to the embodiment.

Icon: through-silicon vias 100, a through-silicon via dense wiring region 101, a first dense wiring region 101a, a second dense wiring region 101b, a third dense wiring region 101c, a fourth dense wiring region 101d, a through-silicon via non-dense wiring region 102, a first non-dense wiring region 102a, a second non-dense wiring region 102b, a dense wiring region first pad 103a, a dense wiring region second pad 103b, a non-dense wiring region first pad 103c, a non-dense wiring region second pad 103d, a non-dense wiring region third pad 103e, a non-dense wiring region fourth pad 103f, a dense wiring region wiring 104a, a non-dense wiring region wiring 104b, a silicon layer 105, a first through-silicon via groove 1001, a second through-silicon via groove 1002, a break h1, a break h2, a first through-silicon via groove width L1, a second through-silicon via groove width L2, an active device 106a, an active device 106b, an active device 106c, an active device 106d, a 107, a passive device 107, a passive device 107b, a solder ball 108a, a solder ball 108b, a solder ball 108c, a solder ball 108d, a solder ball 108e, a bonding wire 109, a glass via 200a, a glass via 200b, a glass via dense wiring region 201, a glass via first dense wiring region 201a, a glass via second dense wiring region 201b, a glass via third dense wiring region 201c, a glass via non-dense wiring region 202, a glass via non-dense first wiring layer 202a, a glass via non-dense second wiring layer 202b, a glass via dense wiring region pad 203, a glass via dense wiring 204, a glass substrate 205, an active device 206a, an active device 206b, an active device 206c, an active device 206d, a printed circuit board structure POP package module 300, a heat sink fin 301, a heat sink fin cavity 3001, a heat sink fin body 3002, a heat sink body substrate 3002a, a heat sink body protrusion 3002b, a heat sink body inner and outer diameter difference L3, the width L4 of the radiating fin cavity, the width h3 of the protruding part of the radiating fin body, the interval h4 of the protruding part of the radiating fin body and the height h5 of the protruding part of the radiating fin body.

Detailed Description

The following examples are given to illustrate the present invention in detail, and the following examples are given to illustrate the detailed embodiments and specific procedures of the present invention, but the scope of the present invention is not limited to the following examples.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

The first embodiment is as follows:

a printed circuit board structure, as shown in fig. 1, is as follows:

fig. 1 shows a structure of a tsv 100 of a printed circuit board structure, which forms a first tsv 1001 with a step difference h1 and a second tsv 1002 with a step difference h2 in a silicon layer 105, wherein the first tsv has a groove width of L1, and the second tsv has a groove width of L2. The through-silicon-via 100 structure forms a dense through-silicon-via wiring area 101 and a non-dense through-silicon-via wiring area 102, wherein the dense through-silicon-via wiring area 101 is formed with a first dense wiring area 101a, a second dense wiring area 101b, a third dense wiring area 101c and a fourth dense wiring area 101d, and the left and right non-dense through-silicon-via wiring areas 102 form a first non-dense wiring area 102a and a second non-dense wiring area 102b.

The first dense wiring region 101a, the second dense wiring region 101b, and the left-side through-silicon-via non-dense wiring region 102a are exposed from the first through-silicon-via groove 1001; the third dense wiring region 101c, the fourth dense wiring region 101d, and the right second non-dense wiring region 102b are exposed from the second through-silicon-via groove 1002.

The first dense wiring area 101a and the second dense wiring area 101b form a dense wiring area second pad 103b and a non-dense wiring area second pad 103d, and the dense wiring area second pad 103b and the non-dense wiring area second pad 103d are exposed from the first tsv recess 1001; the left through-silicon-via non-dense wiring region 102a also forms a non-dense wiring region first pad 103c. The dense wiring area second pad 103b, the non-dense wiring area second pad 103d, and the non-dense wiring area first pad 103c are electrically connected to each other through the dense wiring area wiring 104a and the dense wiring area wiring 104 b.

The third dense wiring area 101c and the fourth dense wiring area 101d form a dense wiring area first pad 103a and a non-dense wiring area third pad 103e, and the dense wiring area first pad 103a and the non-dense wiring area third pad 103e are exposed from the second tsv recess 1002; the right through-silicon via non-dense wiring region 102b also forms a non-dense wiring region fourth pad 103f. The first pad 103a of the dense wiring area, the third pad 103e of the non-dense wiring area, and the fourth pad 103f of the non-dense wiring area are interconnected and conducted through the dense wiring area wiring 104a and the non-dense wiring area wiring 104 b.

The offset is h1 and h2, and can be adjusted and designed according to the number of vertically stacked components and the thicknesses of the components; the first silicon through hole groove width L1 and the second silicon through hole groove width L2 can be adjusted and designed according to the horizontal placement number of the components and the length and width of the components.

In some embodiments, as shown in fig. 2, the dense routing area 104a formed in the dense routing area 101 of the through-silicon via is a fine line electrically connected to the

active devices

106a and 106b through the first pads 103a and the solder balls 108a (which may include bonding wires 109) of the dense routing area for fanning out the dense routing of the

active devices

106a and 106 b. Wherein the

active devices

106a and 106b are respectively bonded to the third dense wiring region 101c and the fourth dense wiring region 101d in the through-silicon-via dense wiring region 101. Meanwhile, the

active devices

106a, 106b may be packaged face up with solder balls 108c for the vertically stacked active devices 106 a.

In some embodiments, as shown in fig. 2, the first non-dense wiring region 102a and the second non-dense wiring region 102b in the non-dense wiring region 102 of the through-silicon via may be electrically interconnected with the passive device 107 through the non-dense wiring region 104 b.

In some embodiments, as shown in fig. 2, the first non-dense wiring region 102a and the second non-dense wiring region 102b in the non-dense wiring region 102 of the through-silicon via may be electrically interconnected through the non-dense wiring region 104b and the solder balls 108 b.

In some specific embodiments, as shown in fig. 3, the first through-silicon-via recess 1001 may encapsulate the

active devices

106c, 106d, 107b; the second through silicon via recess 1002 may encapsulate the active device 106a, the active device 106b, and the passive device 107a. The

active devices

106a, 106b, 106c and 106d are packaged in the dense silicon via wiring area 101, and the

passive devices

107a and 107b are packaged in the non-dense silicon via wiring area 102. The

active devices

106a, 106b, 106c, and 106d may be electrically interconnected with the

passive devices

107a and 107b through the dense wiring region wires 104a and the non-dense wiring region wires 104 b.

The second embodiment:

a printed circuit board structure, as shown in fig. 4 to 5, specifically comprising:

as shown in fig. 4, a glass via 200 based on a glass substrate 205 is formed in the printed circuit board structure, the glass via 200 forms a glass via dense wiring area 201 and a glass via non-dense wiring area 202, wherein the glass via dense wiring area 201 includes a glass via first dense wiring area 201a, a glass via second dense wiring area 201b, and a glass via third dense wiring area 201c, the glass via first dense wiring area 201a, the glass via second dense wiring area 201b, and the glass via third dense wiring area 201c form a glass via dense wiring area pad 203, and the lines among the glass via first dense wiring area 201a, the glass via second dense wiring area 201b, and the glass via third dense wiring area 201c are connected through the glass via dense wiring 204. The glass via non-dense wiring region 202 is formed with a glass via non-dense first wiring layer 202a and a glass via non-dense second wiring layer 202b, and the glass via non-dense first wiring layer 202a and the glass via non-dense second wiring layer 202b can be conducted across layers.

As shown in fig. 5, the glass via 200a and the glass via 200b are respectively bonded to the printed circuit board structure 100 according to the first embodiment, wherein the first dense wiring region 201a of the glass via 200a and the second dense wiring region 201b of the glass via are respectively bonded to the active device 206c and the active device 206d of the through silicon via 100 through solder balls 108c, and the first non-dense wiring region 202a of the glass via is connected to the through silicon via 100 through solder balls 108 b; the first dense wiring region 201a and the second dense wiring region 201b of the glass via 200b are respectively connected to the active device 206a and the active device 206b in the through-silicon-via 100 by bonding via solder balls 108c, and the first non-dense wiring layer 202a of the glass via is connected to the through-silicon-via 100 by the solder balls 108 b.

A printed circuit board structure is prepared by the following steps:

s1: providing a silicon-based wafer, performing mask protection on a non-etching area, etching by adopting the existing etching process to form a first silicon through hole groove 1001 and a second silicon through hole groove 1002, grinding and polishing;

s2: performing mask protection on the first through-silicon-via groove 1001 and the second through-silicon-via groove 100, and processing layer by adopting the existing through-silicon-via processing technology and the conventional CMOS (complementary metal oxide semiconductor) process to form non-dense wiring area wiring;

s4: carrying out pad ball planting or additive method on the silicon through hole structure with the formed offset to form a copper column and a bump, bonding an active device and a passive device with the silicon through hole structure, pouring glue and carrying out plastic package, and flattening and exposing the tin ball, the copper column or the bump required by the conduction of the active device by a grinding plate;

s6: and (4) aligning and calibrating, pressing the glass through hole formed in the step S5 into a butt joint silicon through hole, carrying out interconnection and conduction through at least one of a solder ball, a copper column or a bump, and carrying out secondary glue pouring and plastic packaging.

Example three:

a printed circuit board structure package module, as shown in fig. 6-8, specifically comprising:

as shown in fig. 6, the printed circuit board structure of the second embodiment is planarized by removing the paste to expose the non-dense first wiring layer 202a of the glass vias 200b or the non-dense second wiring layer 202b of the glass vias, and an IC shunt is provided, which is conductively connected to the non-dense first wiring layer 202a of the glass vias or the non-dense second wiring layer 202b of the printed circuit board structure of the second embodiment through solder balls 108 b.

As shown in fig. 7, the printed circuit board structure in the second embodiment is subjected to glue removal and leveling to expose the first non-dense wiring layer 202a of the glass vias 200b or the second non-dense wiring layer 202b of the glass vias and expose the pads 203 of the dense wiring region of the glass vias in the third dense wiring region 201c of the glass vias. The active device 206a is bonded by at least one of solder balls 108e, copper pillars, or bumps.

As shown in fig. 8, in some specific embodiments, the printed circuit board structure of the second embodiment is planarized by removing the glue, so as to expose the non-dense first wiring layer 202a or the non-dense second wiring layer 202b of the glass vias 200a and expose the pads 203 of the dense glass via wiring region of the third dense glass via wiring region 201 c. The

active devices

206b, 206c, 206d are bonded by at least one of solder balls 108f, copper pillars, or bumps.

Example four:

a printed circuit board structure package module, as shown in fig. 9-12, specifically comprising:

as shown in fig. 9, a POP package module 300 with a printed circuit board structure includes a printed circuit board structure and heat dissipation fins 301 according to the third embodiment, wherein the heat dissipation fins 301 are disposed in the first through-silicon-via groove 1001 and the second through-silicon-via groove 1002 and abut against the glass through-

holes

200a and 200b. The heat sink fin 301 includes a heat sink fin cavity 3001 and a heat sink fin body 3002, the heat sink fin body 3002 includes a heat sink fin body substrate 3002a and a heat sink fin body protrusion 3002b, and the heat sink fin body protrusion 3002b extends to the outside of the printed circuit board structure according to the third embodiment.

As shown in fig. 10 to 12, the top projection and the left projection of the heat sink fins are shown, the difference L3 between the inner and outer diameters of the heat sink fin body is smaller than the width L1 of the first through-silicon-via groove and the width L2 of the second through-silicon-via groove, and the width L4 of the cavity projection of the vertically stacked heat sink fins is larger than the width of the dense silicon-via wiring area 101, so that the heat sink fins can be accommodated by the first through-silicon-via groove and the second through-silicon-via groove. The width h3 of the protruding part of the radiating fin body and the interval h4 of the protruding part of the radiating fin body are both smaller than the offset h1 and the offset h2, and the height h5 of the protruding part of the radiating fin body is smaller than the width L1 of the groove of the first silicon through hole and the width L2 of the groove of the second silicon through hole.

The invention provides a printed circuit board structure, which has the following beneficial effects: (1) Forming a dense wiring area in the silicon through hole groove, wherein the dense wiring area is used for electrical connection of the active device and is beneficial to fine line fan-out of the active device; (2) Forming a non-dense wiring area in the silicon through hole groove, wherein the non-dense wiring area is used for electrical connection of a passive device and can realize fan-out wiring of a partition; (3) An intensive wiring area is formed in the silicon through hole groove, and the interconnection signal wire is shortened, so that the signal loss of an active device is reduced; (4) The through silicon via of the printed circuit board structure with the offset structure is beneficial to the embedding of devices, reduces the thickness deviation of the whole board caused by the surface attachment of the devices, ensures that the size exceeds the tolerance, and reduces the electromagnetic interference among the devices; (5) Through silicon vias of the printed circuit board structure with the offset structure can design the vertical distance of the upper and lower stacked active devices according to the specification requirement of wiring fan-out of the active devices, adjust the offset size, and embed and stack devices with different sizes according to the offset size, thereby improving the integration density of the devices; (6) Forming silicon through holes of a printed circuit board structure with dense wiring and small through hole diameters, crimping glass through holes with limited dense wiring and large through hole diameters, aligning and conducting dense wiring areas of the glass through holes and dense wiring areas of the silicon through holes, facilitating fan-out of wiring layer by layer to micron level, simultaneously limiting dense wiring of the glass through holes and large through hole diameters, and bonding and conducting analog chips of large circuits; (7) In a cavity structure formed by the silicon through hole and the glass through hole of the printed circuit board structure, cross-layer conduction can be realized through solder balls and copper columns, and heat dissipation fins can also be arranged, so that the heat dissipation efficiency of the side edge of the printed circuit board structure in the X-Y horizontal direction is improved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. The protection scope of the present invention should be subject to the appended claims.

Claims

1. The utility model provides a printed circuit board structure, includes through-silicon via (100), glass through-hole (200), insulating layer, its characterized in that: the silicon through holes (100) are distributed with silicon through hole dense wiring areas (101) and silicon through hole non-dense wiring areas (102), silicon through hole grooves (1001/1002) are formed in the silicon through holes (100), and the silicon through hole dense wiring areas (101) and the silicon through hole non-dense wiring areas (102) are exposed out of the silicon through hole grooves (1001/1002);

the glass through hole (200) is distributed with a glass through hole dense wiring area (201) and a glass through hole non-dense wiring area (202), the glass through hole dense wiring area (201) is distributed with a glass through hole first dense wiring area (201 a), a glass through hole second dense wiring area (201 b) and a glass through hole third dense wiring area (201 c), and the glass through hole first dense wiring area (201 a), the glass through hole second dense wiring area (201 b) and the glass through hole third dense wiring area (201 c) are distributed with a glass through hole dense wiring area pad (203) and a glass through hole dense wiring (204);

the silicon through hole dense wiring area (101) is vertically corresponding to the glass through hole dense wiring area (201), and the silicon through hole non-dense wiring area (102) is vertically corresponding to the glass through hole non-dense wiring area (202);

the insulating layer is used for plastically packaging the silicon through hole (100) and the glass through hole (200).

2. A printed circuit board structure according to claim 1, wherein: the dense wiring area (101) of through-silicon via distributes and has first dense wiring area (101 a), second dense wiring area (101 b), third dense wiring area (101 c) and fourth dense wiring area (101 d), first dense wiring area (101 a) second dense wiring area (101 b), third dense wiring area (101 c) and fourth dense wiring area (101 d) form first pad (103 a) of dense wiring area, dense wiring area second pad (103 b) and dense wiring area wiring (104 a).

3. The printed circuit board structure of claim 2, wherein: an active device (106) is bonded with the first pad (103 a) of the dense wiring area and the second pad (103 b) of the dense wiring area, and fan-out wiring is conducted through the dense wiring area (104 a);

the active devices (106) are stacked such that a lead of at least one of the active devices (106) faces upward, the lead being exposed from the insulating layer.

4. A printed circuit board structure according to claim 3, wherein: the glass through hole first dense wiring region (201 a) vertically corresponds to the first dense wiring region (101 a) of the through silicon via dense wiring region (101); the glass through hole second dense wiring area (201 b) vertically corresponds to the first dense wiring area (101 b) of the through silicon via dense wiring area (101);

the active devices (106) of the through-silicon-via dense wiring area (101) fan out wiring to the glass vias (200) from the pins, the glass-via dense wiring area pads (203), and the glass-via dense wiring (204) facing upward.

5. A printed circuit board structure according to claim 1, wherein: the silicon through hole non-dense wiring area (102) is distributed with a first non-dense wiring area (102 a) and a second non-dense wiring area (102 b), and the first non-dense wiring area (102 a) and the second non-dense wiring area (102 b) form a first pad (103 c) of the non-dense wiring area, a second pad (103 d) of the non-dense wiring area, a third pad (103 e) of the non-dense wiring area, a fourth pad (103 f) of the non-dense wiring area and non-dense wiring area wiring (104 b).

6. A printed circuit board structure according to claim 5, wherein: the non-dense wiring area second pad (103 d) of the first non-dense wiring area (102 a) is bonded with a passive device (107), the non-dense wiring area third pad (103 e) of the second non-dense wiring area (102 b) is bonded with a passive device (107), and the passive devices (107) are electrically interconnected through the non-dense wiring area wiring (104 b).

7. The printed circuit board structure of claim 6, wherein: the non-densely-arranged second pads (103 c) of the first non-densely-arranged area (102 a) are connected to the glass via (200 a) through solder balls (108), and the non-densely-arranged third pads (103 f) of the second non-densely-arranged area (102 b) are connected to the glass via (200 b) through solder balls (108).

8. A printed circuit board structure according to claim 1, wherein: the heat dissipation fin body (3002) comprises a heat dissipation fin body substrate (3002 a) and a heat dissipation fin body protrusion (3002 b), and the heat dissipation fin body protrusion (3002 b) extends towards the outside of the through silicon via;

vertically stacking the heat dissipation fins (301), wherein the projection of the overlapped heat dissipation fin cavity (3001) can cover the through-silicon-via dense wiring region (101);

the radiating fin body (3002) is fixed by the insulating layer plastic envelope, and abuts against the through-silicon via (100) and the through-glass via (200), and the radiating fin body protruding portion (3002 b) of the radiating fin body (3002) is exposed from the insulating layer.

9. Use of a printed circuit board structure according to claims 1-8 in a package module, characterized in that:

-including at least one printed circuit board structure according to claims 1-8, a carrier board electrically connected to said glass vias (200 b) of said printed circuit board structure through said solder balls (108), and at least one active device (206), said active device (206) electrically connected to said glass via dense wiring area pads (203) of said glass via first dense wiring area (201 a), said glass via second dense wiring area (201 b) and said glass via third dense wiring area (201 c), fan out wiring to said glass vias (200);

the insulating layer plastically encapsulates the printed circuit board structure, the carrier plate and the active device (206).

10. A method for manufacturing a printed circuit board structure is characterized in that:

s1: providing a silicon-based wafer, performing mask protection on a non-etching area, etching by adopting the existing etching process to form the silicon through hole groove (1001/1002), and grinding and polishing;

s2: performing mask protection on the silicon through hole groove (1001/1002), and processing layer by adopting the existing silicon through hole processing technology and the conventional CMOS process to form non-dense wiring area wiring;

s3: removing the mask, performing mask protection on the formed non-dense wiring region, and performing deep processing by adopting the conventional through silicon via processing technology and the conventional CMOS process or the stacked CMOS process to form dense wiring region wiring with the aspect ratio of 5-15;

s4: carrying out pad ball planting or additive method on the through silicon via (100) with the formed offset to form a copper column and a bump, bonding the active device (106) and the passive device (107) with the through silicon via (100), pouring glue into the insulating layer for plastic package, and flattening the grinding plate to expose the solder ball (108), the copper column or the bump required by the conduction of the active device (106);

s5: deep processing of the glass through hole (200) is carried out by adopting at least one of a photosensitive glass method, a plasma etching method, an electrochemical method or a laser induced etching method, and an RDL layer is formed layer by adopting a conventional CMOS process;

s6: and (4) aligning and calibrating, namely pressing the glass through hole (200) formed in the step (S5) to be butted with the silicon through hole (100), carrying out interconnection and conduction through at least one of a solder ball (108), a copper column or a bump, and carrying out secondary glue filling and plastic packaging.