CN115241273A - High-voltage diode and manufacturing method thereof - Google Patents
High-voltage diode and manufacturing method thereof Download PDFInfo
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
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Abstract
The embodiment of the application provides a high-voltage diode and a manufacturing method of the high-voltage diode, and relates to the field of semiconductor power devices and manufacturing. In the embodiment of the application, the diffusion regions penetrating through the first semiconductor layer and the second semiconductor layer are formed at the two opposite ends of the first semiconductor layer and the second semiconductor layer of the high-voltage diode, so that the high-voltage diode can bear large high voltage (for example, voltage over 1800V), meanwhile, the terminal of the high-voltage diode is reduced, the size of a product is reduced, the manufacturing cost can be saved, meanwhile, the power consumption can be reduced, and the packaging is facilitated.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor power devices and manufacturing, in particular to a high-voltage diode and a manufacturing method of the high-voltage diode.
Background
A High Voltage Diode (High Voltage Diode) is a semiconductor device for converting alternating current power into direct current power, and the most important characteristic of the High Voltage Diode is unidirectional conductivity. When applied to a circuit, current flows from the anode of the high voltage diode into the cathode. Typically it comprises a PN junction and two terminals, positive and negative. The high-voltage diode is mainly applied to the fields of industrial frequency conversion, digital generators and the like, and can be expanded to the fields of charging piles, direct-current electronic load instruments, UPS, industrial three-phase rectifier modules, power supplies and household appliances.
However, the terminal size of the existing high-voltage diode is large, which causes the large size of the high-voltage diode itself and the increase of the manufacturing cost, and then causes the large power consumption of the tube core and influences the use efficiency of the product; finally, the die size is too large, which results in an unsatisfactory package profile and also affects the packaging of the module with other products.
Disclosure of Invention
In order to overcome the technical problems mentioned in the background, embodiments of the present application provide a high voltage diode and a method for manufacturing the high voltage diode.
In a first aspect of the present application, there is provided a high voltage diode comprising:
the semiconductor device comprises a first semiconductor layer, a silicon wafer and a second semiconductor layer which are arranged in a stacked mode;
the diffusion regions are positioned at two opposite ends of the first semiconductor layer, the silicon wafer and the second semiconductor layer and penetrate through the first semiconductor layer, the silicon wafer and the second semiconductor layer;
the mesa structure is positioned on one side of the second semiconductor layer, which is far away from the first semiconductor layer, and is in contact with the diffusion region;
a first electrode layer located on the second semiconductor layer and far away from the first semiconductor layer, wherein the first electrode layer is insulated from the mesa structure;
and the second electrode layer is positioned on the first semiconductor layer and is far away from the second semiconductor layer.
In one possible embodiment of the present application, the first semiconductor layer is a P + -type semiconductor layer;
the second semiconductor layer is an N + type semiconductor layer;
the silicon wafer is an N-type semiconductor layer;
the diffusion region is a P-type region;
the first electrode layer is an anode layer;
the second electrode layer is a cathode layer.
In a second aspect of the present application, a method for manufacturing a high voltage diode is provided, the method comprising:
providing a silicon wafer, and polishing the silicon wafer;
carrying out diffusion treatment on the polished silicon wafer, and growing an oxide layer on the surface of the silicon wafer;
etching the oxide layers on two opposite sides of the silicon wafer to form an isolation region;
forming aluminum metal layers on two opposite sides of the silicon wafer;
corroding the aluminum metal layer, determining a region needing to be penetrated on the silicon wafer, and forming a diffusion region penetrating through the silicon wafer through diffusion treatment;
forming a first semiconductor layer and a second semiconductor layer on two opposite sides of the silicon wafer through diffusion treatment;
manufacturing a mesa structure connected with the diffusion region on one side of the second semiconductor layer far away from the first semiconductor layer;
manufacturing a first electrode layer on one side of the second semiconductor layer far away from the first semiconductor layer;
and manufacturing a second electrode layer on one side of the first semiconductor layer, which is far away from the second semiconductor layer.
In one possible embodiment of the present application, the step of providing a silicon wafer and performing a polishing process on the silicon wafer includes:
providing an N-type silicon wafer with any crystal orientation;
and carrying out double-sided polishing treatment on the silicon wafer.
In a possible embodiment of the present application, the step of performing diffusion treatment on the polished silicon wafer to grow an oxide layer on the surface of the silicon wafer includes:
and putting the silicon wafer into a diffusion furnace with the furnace temperature of 1145-1155 ℃, and growing an oxidation layer with the thickness of 1.2-2.2 um on the surface of the silicon wafer for 300-320 min by wet oxygen oxidation treatment, wherein the flow of oxygen introduced into the diffusion furnace in the wet oxygen oxidation treatment process is 5.0SLM/min, and the flow of hydrogen introduced into the diffusion furnace is 7.0SLM/min.
In a possible embodiment of the present application, the step of etching the oxide layers on two opposite sides of the silicon wafer to form the isolation region includes:
coating photoresist layers on two opposite sides of the silicon wafer;
obtaining an isolation region pattern by developing and exposing the photoresist layer;
placing the silicon wafer into a mixed solution of HF and BOE for etching to form the isolation region;
the step of forming aluminum metal layers on opposite sides of the silicon wafer comprises:
and respectively evaporating aluminum metal layers with the thickness of 0.5-1.5 um on two opposite sides of the silicon wafer.
In one possible embodiment of the present application, the step of etching the aluminum metal layer, determining a region on the silicon wafer to be penetrated, and forming a diffusion region penetrating through the silicon wafer by a diffusion process includes:
photoetching the aluminum metal layer, and preparing a region corresponding to the diffusion region on the silicon wafer;
putting the silicon wafer into corrosive liquid to corrode the aluminum metal layer to form a region needing to be penetrated;
and putting the silicon wafer into a diffusion furnace with the furnace temperature of 1283-1293 ℃ for punch-through diffusion to form the diffusion area, wherein the diffusion time is 4 hours, the flow of introduced nitrogen is 1.7SLM/min, the flow of introduced oxygen is 1.7SLM/min, and the minimum width of the diffusion area is 90-110 um.
In one possible embodiment of the present application, the step of forming a first semiconductor layer and a second semiconductor layer on two opposite sides of the silicon wafer by diffusion processing includes:
placing the silicon wafer into a diffusion furnace with the furnace temperature of 1250-1260 ℃ for high-temperature diffusion to form a first semiconductor layer on one side of the silicon wafer, and generating an oxide layer with the thickness of 0.5-1.5 um on the surface of the silicon wafer, wherein the first semiconductor layer is a P + type semiconductor layer, the high-temperature diffusion time is 30 hours, the flow of introduced nitrogen is 5.0SLM/min, and the flow of introduced oxygen is 5.0SLM/min;
manufacturing a photoresist protective layer on one side of the silicon wafer where the first semiconductor layer is formed;
the silicon wafer is placed into a diffusion furnace with the furnace temperature of 1250-1260 ℃ for high-temperature diffusion, the second semiconductor layer is formed on the other side of the silicon wafer, an oxide layer with the thickness of 0.9-1.9 um is formed on the surface of the silicon wafer, the second semiconductor layer is an N + type semiconductor layer, a PN junction with the junction depth of 28-32 um is formed between the first semiconductor layer and the second semiconductor layer, the high-temperature diffusion time is 90-110 min, the flow of introduced oxygen is 5.0SLM/min, and the flow of introduced hydrogen is 7.0SLM/min.
In a possible embodiment of the present application, the step of forming a mesa structure connected to the diffusion region on a side of the second semiconductor layer away from the first semiconductor layer includes:
corroding the silicon wafer by using a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, and corroding a groove connected with the diffusion region on one side of the second semiconductor layer, which is far away from the first semiconductor layer;
filling glass powder into the groove;
and sintering the glass powder to obtain the mesa structure.
In one possible embodiment of the present application, the step of forming the first electrode layer on the side of the second semiconductor layer away from the first semiconductor layer includes:
manufacturing a metal layer with the thickness of 5.5-6.5 um on one side of the second semiconductor layer, which is far away from the first semiconductor layer, as the first electrode layer;
the step of manufacturing a second electrode layer on the side of the first semiconductor layer far away from the second semiconductor layer includes:
at the first semiconductor layer away from the first semiconductor layerOne side of the second semiconductor layer is sequentially evaporated with a Ti metal layer, a Ni metal layer and an Ag metal layer as the second electrode layer, wherein the Ti metal layer has a thickness of
The thickness of the Ni metal layer is
The thickness of the Ag metal layer is
According to the high-voltage diode and the manufacturing method of the high-voltage diode, the diffusion regions penetrating through the first semiconductor layer and the second semiconductor layer are formed at the two opposite ends of the first semiconductor layer and the second semiconductor layer, so that the high-voltage diode can bear larger high voltage (for example, voltage over 1800V), meanwhile, the terminal of the high-voltage diode is reduced, the size of a product is reduced, and the manufacturing cost can be saved; the size reduction of the high-voltage diode can reduce power consumption and is convenient to package.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a film structure of a high voltage diode in the prior art.
Fig. 2 is a schematic diagram of a film structure of the high voltage diode provided in this embodiment.
Fig. 3 is a schematic step diagram of a method for manufacturing a high voltage diode according to an embodiment of the present disclosure.
Fig. 4-5 are process diagrams corresponding to the method of fig. 3.
An icon:
10-a high voltage diode; 101-a silicon wafer; 102-an oxide layer; 103-isolation regions; 104-aluminum metal layer; 110-a first semiconductor layer; 120-a second semiconductor layer; 130-diffusion region; 140-mesa structure; 150-a first electrode layer; 160-second electrode layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, unless expressly stated or limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In the prior art, a field limiting ring + aluminum field plate process technology can be adopted for the high-voltage diode, as shown in fig. 1, the terminal size H1 of the high-voltage diode with the structure is too large, generally, the terminal size H1 is 500um-600um, and firstly, the size of the high-voltage diode is too large, which causes too high cost; secondly, the power consumption of the high-voltage diode is overlarge, and the use efficiency of the product is influenced; finally, the high-voltage diode is overlarge in size, so that some packaging shapes cannot be met, and the effect of combining and packaging the high-voltage diode with other products into a module is also influenced.
In the prior art, the high-voltage diode can also adopt a boron diffusion mode to form a through area, the diffusion time is too long and needs 100 hours, the production efficiency is seriously influenced, and meanwhile, the condition of silicon powder infiltration easily occurs in the scribing process, and the reliability and the quality of a product can be influenced.
To solve the above-mentioned technical problems, an embodiment of the present invention provides a high voltage diode, please refer to fig. 2, fig. 2 is a schematic diagram of a film structure of the high voltage diode provided in the embodiment, and the high voltage diode is described in detail below with reference to fig. 2.
In this embodiment, the high voltage diode 10 may include a first semiconductor layer 110, a silicon wafer 101, and a second semiconductor layer 120, which are stacked, wherein a PN junction (not shown) is formed on an interface between the first semiconductor layer 110 and the second semiconductor layer 120, and a depth of the PN junction may be 28um to 32um.
The high voltage diode 10 may further include a diffusion region 130, a mesa structure 140, a first electrode layer 150, and a second electrode layer 160. The diffusion regions 130 are located at two opposite ends of the first semiconductor layer 110, the silicon chip 101 and the second semiconductor layer 120, and penetrate the first semiconductor layer 110, the silicon chip 101 and the second semiconductor layer 120; the mesa structure 140 is located on a side of the second semiconductor layer 120 away from the first semiconductor layer 110, and contacts the diffusion region 130; the first electrode layer 150 is located on a side of the second semiconductor layer 120 away from the first semiconductor layer 110; the second electrode layer 160 is located on a side of the first semiconductor layer 110 away from the second semiconductor layer 120.
In this embodiment, the first semiconductor layer 110 may be a P + -type semiconductor layer, the second semiconductor layer 120 may be an N + -type semiconductor layer, the silicon wafer 101 is an N-type semiconductor layer, the diffusion region 130 is a P-type region, the first electrode layer 150 may be an anode layer, and the second electrode layer 160 may be a cathode layer.
In the above structure, the diffusion regions 130 penetrating the first semiconductor layer 110 and the second semiconductor layer 120 are formed at two opposite ends of the first semiconductor layer 110 and the second semiconductor layer 120, so that the high voltage diode 10 can bear a large high voltage (for example, a voltage of 1800V or more), and meanwhile, the high voltage diode 10 has a small terminal, a small product size, and a low manufacturing cost; the reduced size of the high voltage diode 10 reduces power consumption and also facilitates packaging.
Fig. 3 to 5 show a schematic flow chart of the high voltage diode manufacturing method, fig. 3 shows a process diagram corresponding to the high voltage diode manufacturing method, fig. 4 and 5 show process diagrams corresponding to the high voltage diode manufacturing method, and the manufacturing process of the high voltage diode is described in detail below with reference to fig. 3 to 5.
Step S11, providing a silicon wafer 101, and polishing the silicon wafer 101.
In this step, a silicon wafer 101 with N-type random crystal orientation can be provided, and the silicon wafer 101 is subjected to double-side polishing treatment, so that the surface of the silicon wafer 101 is smooth and clean without contamination and defects.
And S12, performing diffusion treatment on the polished silicon wafer 101, and growing an oxide layer 102 on the surface of the silicon wafer 101.
In the step, the silicon wafer 101 is placed in a diffusion furnace with the furnace temperature of 1145 ℃ to 1155 ℃, the wet oxygen oxidation treatment is carried out for 300min to 320min, and an oxide layer 102 with the thickness of 1.2um to 2.2um grows on the surface of the silicon wafer 101, wherein the flow of oxygen introduced into the diffusion furnace in the wet oxygen oxidation treatment process is 5.0SLM/min, and the flow of hydrogen introduced into the diffusion furnace is 7.0SLM/min.
Step S13, etching the oxide layers 102 on the two opposite sides of the silicon wafer 101 to etch the isolation region 103.
In this embodiment, step S13 can be implemented by:
firstly, coating photoresist layers on two opposite sides of a silicon wafer 101;
then, developing and exposing the photoresist layer to obtain an isolation region pattern;
and finally, the silicon wafer is placed into a mixed solution of HF and BOE for etching, and the isolation region 103 is etched.
Step S14, forming aluminum metal layers 104 on two opposite sides of the silicon wafer 101.
In the step, aluminum metal layers 104 with a thickness of 0.5um to 1.5um are respectively evaporated on two opposite sides of the silicon wafer 101.
In step S15, the aluminum metal layer 104 is etched to determine a region on the silicon wafer 101 to be penetrated, and a diffusion region 130 penetrating through the silicon wafer 101 is formed by diffusion.
In this embodiment, step S15 can be implemented by:
firstly, photoetching an aluminum metal layer 104, and preparing a region corresponding to a diffusion region 130 on a silicon wafer 101;
then, putting the silicon wafer 101 into an etching solution to etch the aluminum metal layer 104 to form a region needing punch-through;
then, the silicon chip is placed into a diffusion furnace with the furnace temperature of 1283-1293 ℃ to carry out punch-through diffusion to form a diffusion area 130, wherein the diffusion time is 4 hours, the flow rate of the introduced nitrogen is 1.7SLM/min, the flow rate of the introduced oxygen is 1.7SLM/min, and the minimum width of the diffusion area is 90-110 um.
In step S16, a first semiconductor layer 110 and a second semiconductor layer 120 are formed on opposite sides of the silicon wafer 101 by diffusion processing.
In the present embodiment, step S16 can be implemented by:
firstly, placing a silicon wafer 101 into a diffusion furnace with the furnace temperature of 1250-1260 ℃ for high-temperature diffusion to form a first semiconductor layer 110 on one side of the silicon wafer 101, generating an oxide layer with the thickness of 0.5-1.5 um on the surface of the silicon wafer 101, wherein the first semiconductor layer 110 is a P + type semiconductor layer, the high-temperature diffusion time is 30 hours, the flow of introduced nitrogen is 5.0SLM/min, and the flow of introduced oxygen is 5.0SLM/min;
then, a photoresist protective layer is manufactured on one side of the silicon wafer 101 where the first semiconductor layer 110 is formed;
and finally, placing the silicon wafer 101 into a diffusion furnace with the furnace temperature of 1250-1260 ℃ for high-temperature diffusion to form a second semiconductor layer 120 on the other side of the silicon wafer, and generating an oxide layer with the thickness of 0.9-1.9 um on the surface of the silicon wafer, wherein the second semiconductor layer is an N + type semiconductor layer, a PN junction with the junction depth of 28-32 um is formed between the first semiconductor layer 110 and the second semiconductor layer 120, the high-temperature diffusion time is 90-110 min, the flow of introduced oxygen is 5.0SLM/min, and the flow of introduced hydrogen is 7.0SLM/min.
In step S17, a mesa structure 140 connected to the diffusion region 130 is formed on a side of the second semiconductor layer 120 away from the first semiconductor layer 110.
In this step, the silicon wafer 101 is etched by using a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, and a groove connected with the diffusion region 130 is etched on the side of the second semiconductor layer 120 away from the first semiconductor layer 101; filling glass powder into the groove; the mesa structure 140 is obtained by sintering glass frit.
In step S18, a first electrode layer 150 is formed on the second semiconductor layer 120 away from the first semiconductor layer 110.
A metal layer with a thickness of 5.5um to 6.5um is fabricated on one side of the second semiconductor layer 120 away from the first semiconductor layer 110 as the first electrode layer 150.
In step S19, a second electrode layer 160 is formed on the first semiconductor layer 110 away from the second semiconductor layer 120.
A Ti metal layer, a Ni metal layer and an Ag metal layer are sequentially deposited on the first semiconductor layer 110 away from the second semiconductor layer 120 to form a second electrode layer 160, wherein the Ti metal layer has a thickness of
The thickness of the Ni metal layer is
The thickness of the Ag metal layer is
In this embodiment, a plurality of high voltage diodes 10 can be fabricated on one silicon wafer 101, the adjacent high voltage diodes 10 share the same mesa structure 140, and a plurality of individual high voltage diodes 10 can be obtained by cutting from the mesa structure 140 along the direction perpendicular to the mesa structure 140. Meanwhile, the adjacent high-voltage diodes 10 share the same mesa structure 140, so that the terminal area of the high-voltage diodes can be reduced, the area of the high-voltage diodes is saved, and the production cost is reduced.
In summary, in the high voltage diode and the method for manufacturing the high voltage diode provided in the embodiments of the present application, the diffusion regions penetrating through the first semiconductor layer and the second semiconductor layer are formed at two opposite ends of the first semiconductor layer and the second semiconductor layer, so that the high voltage diode can bear a large high voltage (for example, a voltage of 1800V or more), and meanwhile, the terminal of the high voltage diode is reduced, the size of the product is reduced, and the manufacturing cost can be saved; the size reduction of the high-voltage diode can reduce power consumption and is convenient to package.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A high voltage diode, comprising:
the semiconductor device comprises a first semiconductor layer, a silicon wafer and a second semiconductor layer which are arranged in a stacked mode;
the diffusion regions are positioned at two opposite ends of the first semiconductor layer, the silicon wafer and the second semiconductor layer and penetrate through the first semiconductor layer, the silicon wafer and the second semiconductor layer;
the mesa structure is positioned on one side of the second semiconductor layer, which is far away from the first semiconductor layer, and is in contact with the diffusion region;
a first electrode layer located on the second semiconductor layer and far away from the first semiconductor layer;
and the second electrode layer is positioned on the first semiconductor layer and is far away from the second semiconductor layer.
2. The high voltage diode of claim 1, wherein:
the first semiconductor layer is a P + type semiconductor layer;
the second semiconductor layer is an N + type semiconductor layer;
the silicon wafer is an N-type semiconductor layer;
the diffusion region is a P-type region;
the first electrode layer is an anode layer;
the second electrode layer is a cathode layer.
3. A method for manufacturing a high-voltage diode is characterized by comprising the following steps:
providing a silicon wafer, and polishing the silicon wafer;
performing diffusion treatment on the polished silicon wafer, and growing an oxide layer on the surface of the silicon wafer;
etching the oxide layers on two opposite sides of the silicon wafer to form an isolation region;
forming aluminum metal layers on two opposite sides of the silicon wafer;
corroding the aluminum metal layer, determining a region needing to be penetrated on the silicon wafer, and forming a diffusion region penetrating through the silicon wafer through diffusion treatment;
forming a first semiconductor layer and a second semiconductor layer on two opposite sides of the silicon wafer through diffusion treatment;
manufacturing a mesa structure connected with the diffusion region on one side of the second semiconductor layer far away from the first semiconductor layer;
manufacturing a first electrode layer on one side of the second semiconductor layer far away from the first semiconductor layer;
and manufacturing a second electrode layer on one side of the first semiconductor layer far away from the second semiconductor layer.
4. The method of claim 3, wherein the step of providing a silicon wafer and polishing the silicon wafer comprises:
providing an N-type silicon wafer with any crystal orientation;
and carrying out double-sided polishing treatment on the silicon wafer.
5. The method for manufacturing a high-voltage diode according to claim 4, wherein the step of performing diffusion treatment on the polished silicon wafer and growing an oxide layer on the surface of the silicon wafer comprises the steps of:
putting the silicon wafer into a diffusion furnace with the furnace temperature of 1145-1155 ℃, and carrying out wet oxygen oxidation treatment for 300-320 min to grow an oxide layer with the thickness of 1.2-2.2 um on the surface of the silicon wafer, wherein the flow of oxygen introduced into the diffusion furnace in the wet oxygen oxidation treatment process is 5.0SLM/min, and the flow of hydrogen introduced into the diffusion furnace is 7.0SLM/min.
6. The method for manufacturing a high-voltage diode according to claim 5, wherein the step of etching the oxide layers on the two opposite sides of the silicon wafer to form the isolation region comprises the steps of:
coating photoresist layers on two opposite sides of the silicon wafer;
obtaining an isolation region pattern by developing and exposing the photoresist layer;
placing the silicon wafer into a mixed solution of HF and BOE for etching to form the isolation region;
the step of forming aluminum metal layers on opposite sides of the silicon wafer comprises:
and respectively evaporating aluminum metal layers with the thickness of 0.5-1.5 um on two opposite sides of the silicon wafer.
7. The method of claim 6, wherein the etching the aluminum metal layer to define the area to be punched through the silicon wafer and the diffusion through the silicon wafer by diffusion comprises:
photoetching the aluminum metal layer, and preparing a region corresponding to the diffusion region on the silicon wafer;
putting the silicon wafer into corrosive liquid to corrode the aluminum metal layer to form a region needing to be penetrated;
and putting the silicon wafer into a diffusion furnace with the furnace temperature of 1283-1293 ℃ for punch-through diffusion to form the diffusion area, wherein the diffusion time is 4 hours, the flow of introduced nitrogen is 1.7SLM/min, the flow of introduced oxygen is 1.7SLM/min, and the minimum width of the diffusion area is 90-110 um.
8. The method of claim 7, wherein the step of forming the first semiconductor layer and the second semiconductor layer on opposite sides of the silicon wafer by diffusion processing comprises:
placing the silicon wafer into a diffusion furnace with the furnace temperature of 1250-1260 ℃ for high-temperature diffusion to form a first semiconductor layer on one side of the silicon wafer, and generating an oxide layer with the thickness of 0.5-1.5 um on the surface of the silicon wafer, wherein the first semiconductor layer is a P + type semiconductor layer, the high-temperature diffusion time is 30 hours, the flow of introduced nitrogen is 5.0SLM/min, and the flow of introduced oxygen is 5.0SLM/min;
manufacturing a photoresist protective layer on one side of the silicon wafer where the first semiconductor layer is formed;
the silicon wafer is placed into a diffusion furnace with the furnace temperature of 1250-1260 ℃ to perform high-temperature diffusion, the second semiconductor layer is formed on the other side of the silicon wafer, an oxide layer with the thickness of 0.9-1.9 um is formed on the surface of the silicon wafer, the second semiconductor layer is an N + type semiconductor layer, a PN junction with the junction depth of 28-32 um is formed between the first semiconductor layer and the second semiconductor layer, the high-temperature diffusion time is 90-110 min, the flow of introduced oxygen is 5.0SLM/min, and the flow of introduced hydrogen is 7.0SLM/min.
9. The method of claim 8, wherein the step of forming a mesa structure in the second semiconductor layer on a side thereof remote from the first semiconductor layer, the mesa structure being connected to the diffusion region comprises:
corroding the silicon wafer by using a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, and corroding a groove connected with the diffusion region on one side of the second semiconductor layer, which is far away from the first semiconductor layer;
filling glass powder into the groove;
and sintering the glass powder to obtain the mesa structure.
10. The method of claim 9, wherein the step of forming the high voltage diode further comprises the step of forming a second diode,
the step of manufacturing the first electrode layer on the side of the second semiconductor layer far away from the first semiconductor layer comprises the following steps:
manufacturing a metal layer with the thickness of 5.5-6.5 um on one side of the second semiconductor layer, which is far away from the first semiconductor layer, as the first electrode layer;
the step of manufacturing a second electrode layer on the side of the first semiconductor layer far away from the second semiconductor layer includes:
a Ti metal layer, a Ni metal layer and an Ag metal layer are sequentially evaporated on one side of the first semiconductor layer far away from the second semiconductor layer to serve as the second electrode layer, wherein the thickness of the Ti metal layer is
The thickness of the Ni metal layer is
The thickness of the Ag metal layer is
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