CN116435179A - Manufacturing method of semiconductor mesa diode chip - Google Patents
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- CN116435179A CN116435179A CN202310449354.3A CN202310449354A CN116435179A CN 116435179 A CN116435179 A CN 116435179A CN 202310449354 A CN202310449354 A CN 202310449354A CN 116435179 A CN116435179 A CN 116435179A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a manufacturing method of a semiconductor mesa diode chip, and relates to the technical field of semiconductors. The manufacturing method comprises the steps of original sheet cleaning, cathode diffusion, sand blowing, cleaning, oxidation, primary photoetching, field limiting ring diffusion, oxidation, secondary photoetching, anode diffusion, tertiary photoetching, step corrosion, cleaning, passivation, quaternary photoetching, metallization, electrical test and scribing, and is characterized in that the P+ field limiting ring has higher impurity concentration, and in order to avoid the leakage current in a device body from being influenced by the P+ field limiting ring, the P+ field limiting ring is not connected with an anode P+ anode layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor mesa diode chip.
Background
With the progress and development of semiconductor process technology, the performance requirements of semiconductor devices are higher and higher, the most basic unit of the semiconductor devices is that PN junctions are indistinct, and the research on the performance of the PN junctions has important significance for researching other complex devices such as triodes and ICs. The diode is a PN junction, and the mesa diode is the most used in terms of its structure, high power and convenience in manufacturing a rectifier bridge.
The mesa diode, as the name implies, is a diode with a step structure, wherein a diffused wafer is subjected to steps by an etching method, a PN junction is exposed, and then the exposed PN junction is protected by cleaning, passivation and the like, so that the reliability of the device is improved.
One of the parameters of the diode is called reverse breakdown voltage VB, generally, after diffusion is finished, the reverse breakdown voltage of the PN junction is fixed, but after the steps of etching, passivation and other processes of the later process, the electric field on the surface of the PN junction can be changed, so that the breakdown voltage on the surface of the PN junction is lower than the breakdown voltage in the body, and when the diode is used, the PN junction is often broken down firstly, and the reliability, the stability and the service life of the device are reduced. Therefore, the PN junction surface electric field is reduced, and the surface breakdown voltage is improved.
Disclosure of Invention
The invention aims to solve the problems, and provides a manufacturing method of a semiconductor mesa diode chip.
A manufacturing method of a semiconductor mesa diode chip comprises the following steps:
s1, cleaning a raw sheet: cleaning the surface of the silicon wafer substrate by using an acid washing or alkali washing mode;
s2, cathode diffusion: manufacturing an N+ cathode layer on a silicon wafer substrate;
s3, blowing sand: removing the oxide layer and impurities on the surface of the diffused silicon wafer substrate by using silicon carbide;
s4, cleaning: cleaning silicon carbide and impurities on the surface of the silicon wafer substrate by using an acid washing or alkali washing mode;
s5, oxidizing: introducing oxygen at high temperature, and growing an oxide layer on the surface of silicon;
s6, primary photoetching: manufacturing a pattern of a P+ field limiting ring, coating a layer of photoresist on the silicon surface, exposing, developing, fixing and hardening, and transferring the design pattern on the mask plate to the silicon surface;
s7, field limiting ring diffusion: a circle of P+ layer is diffused around the diode, and a P+ field limiting circle is manufactured;
s8, oxidizing: growing an oxide layer on the surface of silicon for selective diffusion masking;
s9, secondary photoetching: manufacturing a P+ anode layer region pattern, coating a layer of photoresist on the silicon surface, and transferring the design pattern on the mask plate to the silicon surface through exposure, development, fixation and hardening;
s10, anode diffusion: manufacturing a P+ anode layer on a silicon wafer substrate, and pushing a P+ field limiting ring;
s11, three times of photoetching: manufacturing a device step, coating a layer of photoresist on the surface of silicon, and transferring a design pattern on a mask plate to the surface of the silicon through exposure, development, fixation and hardening;
s12, step corrosion: etching the part uncovered by the photoresist into a groove by using mixed acid, wherein the depth of the step is generally 5-200 mu m, the width is 1-10mil, and the depth and the width disconnect the P+ anode layer and the P+ field limiting ring;
s13, cleaning: cleaning the surface of the silicon wafer by using the combination of acid washing and alkali washing;
s14, passivating: melting and forming the glass powder coated on the surface of the groove in a high-temperature furnace tube to form a stable, compact and sealed passivation layer;
s15, four times of photoetching: manufacturing an electrode, coating a layer of photoresist on the surface of a silicon wafer, and transferring a designed metallized window pattern to the surface of the silicon wafer through exposure, development, fixation and hardening;
s16, metallization: forming ohmic contact, plating a layer of nickel on the surface of the device, sintering under the protection of inert gas in a furnace tube to form ohmic contact, removing a nickel oxide layer in nitric acid with the temperature of more than 70 ℃, and then plating a layer of nickel and gold, wherein a secondary nickel/gold composite layer is a metal electrode;
s17, electrical property test: marking the chip with electrical failure according to the electrical design requirement;
s18, scribing: dividing a chip manufactured on a silicon wafer into individual semiconductor devices according to design dimensions;
s19, finishing the manufacturing of the diode chip.
Preferably, in step S3, the thickness is removed to 5-50 μm.
Preferably, in step S7, the P+ field limit circle has a width of 5-100 μm and a depth of 5-150 μm.
Preferably, in step S10, the depth of the boron P+ anode layer is 5-150 μm, and the depth of the P+ field limit ring after pushing is 5-250 μm.
Preferably, in step S16, sintering is performed under the protection of inert gas in a furnace tube at 500-700 ℃, wherein the inert gas is nitrogen.
The invention has the beneficial effects that:
a circle of P+ type diffusion layer is added on the basis of the traditional mesa diode structure, namely a field limiting circle is adopted, so that the electric field intensity of the PN junction surface is effectively reduced, the PN junction surface breakdown voltage is improved, and the chip breakdown can be ensured to occur in a body in the use process; the P+ type diffusion layer and the N type substrate form a PN junction, the width of a PN junction terminal space charge region can be widened, the concentration of the P+ layer is higher, the widening of the PN junction space charge region formed by the field limiting ring and the substrate is smaller, the device size is smaller, the cost is lower, the core characteristics of the invention are that the impurity concentration of the P+ field limiting ring is higher (the concentration is generally not lower than 1018), in order to avoid the influence of the leakage current in the device body by the P+ field limiting ring, the P+ field limiting ring is not connected with the anode P+ anode layer, the invention has the advantages of high breakdown voltage, small leakage current, strong voltage endurance, high reliability and the like.
Drawings
FIG. 1 is a schematic diagram of a diode chip according to the present invention;
fig. 2 is a flow chart of the fabrication of the diode chip of the present invention.
In the figure: (1) a silicon wafer substrate, (2) an N+ cathode layer, (3) a P+ anode layer, (4) a P+ field limiting ring, (5) a passivation layer, and (6) a metal electrode.
Detailed Description
The technical scheme of the present invention will be described in further detail with reference to the accompanying drawings in the embodiments of the present invention, but the present invention is not limited to the following embodiments. All other embodiments, which are derived from the embodiments of the invention without creative efforts of a person skilled in the art, belong to the protection scope of the present invention.
A manufacturing method of a semiconductor mesa diode chip comprises the following steps:
s1, cleaning a raw sheet: in order to ensure that no other harmful impurities enter the silicon wafer body in the subsequent diffusion process to cause the deterioration of the performance of the device, cleaning the surface of the silicon wafer by using an acid washing or alkali washing mode; cleaning the surface of the silicon wafer by using an acid washing (mixed acid) or alkali washing (alkaline electronic cleaning agent) mode to ensure that other harmful impurities do not enter the silicon wafer body in the subsequent diffusion process, thereby deteriorating the performance of devices;
s2, cathode diffusion: manufacturing an N+ cathode layer 2 on a silicon wafer substrate 1; diffusing the five-group element impurity atoms into the silicon wafer by utilizing a high-temperature physical diffusion principle to form an N+ cathode layer 2;
s3, blowing sand: the purpose is to remove the oxide layer and impurities on the surface of the diffused silicon wafer substrate 1 by using silicon carbide (the thickness is generally 5-50 μm), so as to ensure that the silicon wafer is convenient to clean later;
s4, cleaning: the silicon carbide and other impurities on the surface of the silicon wafer substrate (1) are cleaned in a pickling (mixed acid) or alkaline cleaning (alkaline electronic cleaning agent) mode, so that the subsequent photoresist can be adhered more firmly;
s5, oxidizing: an oxide layer grows on the surface of the silicon in a high-temperature oxygen-introducing mode and is used for selectively masking impurity diffusion during subsequent diffusion;
s6, primary photoetching: the purpose is to make the pattern of the P+ field limiting ring 4; coating a layer of photoresist on the surface of silicon, and transferring the design pattern on the mask plate to the surface of silicon through exposure, development, fixation and hardening;
s7, field limiting ring diffusion: a circle of P+ layer is diffused around the diode to manufacture a P+ field limiting ring 4, and the width of the P+ field limiting ring 4 is 5-100 mu m, and the depth is 5-150 mu m; the method aims at manufacturing a field limiting ring, and utilizes a high-temperature physical diffusion principle to diffuse III-group element impurity atoms into a silicon wafer to form a P+ field limiting ring 4;
s8, oxidizing: the method aims to grow an oxide layer on the surface of a silicon wafer and is used for selectively masking impurity diffusion during subsequent diffusion;
s9, secondary photoetching: the purpose is to make the region graph of the P+ anode layer 3; coating a layer of photoresist on the surface of silicon, and transferring the design pattern on the mask plate to the surface of silicon through exposure, development, fixation and hardening;
s10, anode diffusion: the method aims at manufacturing a diode anode, diffusing III-group element impurity atoms into a silicon wafer by using a high-temperature physical diffusion principle to form a P+ anode layer 3, and pushing a P+ field limiting ring 4; manufacturing a P+ anode layer 3 on a silicon wafer substrate 1, and pushing a P+ field limiting ring 4, wherein the depth of the boron P+ anode layer 3 is generally 5-150 mu m, and the depth of the P+ field limiting ring 4 after being pushed is 5-250 mu m;
s11, three times of photoetching: the purpose is to make device steps; coating a layer of photoresist on the surface of silicon, and transferring the design pattern on the mask plate to the surface of silicon through exposure, development, fixation and hardening;
s12, step corrosion: the method comprises the steps of manufacturing a device table, corroding a part uncovered by photoresist into a groove by using mixed acid, and exposing a PN junction on the surface of the groove; etching the part uncovered by the photoresist into a groove by using mixed acid, wherein the depth of the step is generally 5-200 mu m and the width is 1-10mil; (the depth and width need to disconnect the p+ anode layer 3 and the p+ field limiter 4);
s13, cleaning: in order to avoid the pollution of the silicon chip by harmful impurities, the performance of the device is deteriorated; the silicon wafer surface is cleaned by combining acid washing (No. 2 liquid=hydrochloric acid: hydrogen peroxide: deionized water=1:1-2:5-7 volume ratio) and alkali washing (No. 1 liquid=ammonia water: hydrogen peroxide: deionized water=1:1-2:5-7 volume ratio), so that the silicon wafer is prevented from being polluted by harmful impurities, and the performance of the device is prevented from being deteriorated;
s14, passivating: glass powder coated on the surface of the groove is melted and molded in a high-temperature furnace tube to form a stable, compact and sealed passivation layer 5;
s15, four times of photoetching: the purpose is to make the electrode for windowing; coating a layer of photoresist on the surface of a silicon wafer, and transferring a designed metallized window pattern to the surface of the silicon wafer through exposure, development, fixation and hardening so as to facilitate the subsequent windowing to manufacture an electrode;
s16, metallization: the purpose is to form ohmic contacts for soldering during packaging; the surface of the device is plated with a layer of nickel, sintered in a furnace tube at 500-700 ℃ under the protection of inert gas (usually nitrogen), to form ohmic contact, then the nickel oxide layer is removed in nitric acid at 70 ℃ or above, and then a layer of nickel and gold are plated, wherein the secondary nickel/gold composite layer is the metal electrode 6;
s17, electrical property test: the aim is to pick out defective products; marking the chip with electrical failure according to the electrical design requirement so as to pick out defective products later;
s18, scribing: dividing a chip manufactured on a silicon wafer into individual semiconductor devices according to design dimensions;
s19, finishing the manufacturing of the diode chip.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (5)
1. The manufacturing method of the semiconductor mesa diode chip is characterized by comprising the following steps of:
s1, cleaning a raw sheet: cleaning the surface of the silicon wafer substrate (1) by using an acid washing or alkali washing mode;
s2, cathode diffusion: manufacturing an N+ cathode layer (2) on a silicon wafer substrate (1);
s3, blowing sand: removing an oxide layer and impurities on the surface of the diffused silicon wafer substrate (1) by using silicon carbide;
s4, cleaning: cleaning silicon carbide and impurities on the surface of the silicon wafer substrate (1) by using an acid washing or alkali washing mode;
s5, oxidizing: introducing oxygen at high temperature, and growing an oxide layer on the surface of silicon;
s6, primary photoetching: manufacturing a pattern of a P+ field limiting ring (4), coating a layer of photoresist on the silicon surface, exposing, developing, fixing and hardening, and transferring a design pattern on a mask plate to the silicon surface;
s7, field limiting ring diffusion: a circle of P+ layer is diffused around the diode, and a P+ field limiting ring (4) is manufactured;
s8, oxidizing: growing an oxide layer on the surface of silicon for selective diffusion masking;
s9, secondary photoetching: manufacturing a P+ anode layer (3) region pattern, coating a layer of photoresist on the silicon surface, and transferring the design pattern on the mask plate to the silicon surface through exposure, development, fixation and hardening;
s10, anode diffusion: manufacturing a P+ anode layer (3) on a silicon wafer substrate (1), and pushing a P+ field limiting ring (4) at the same time;
s11, three times of photoetching: manufacturing a device step, coating a layer of photoresist on the surface of silicon, and transferring a design pattern on a mask plate to the surface of the silicon through exposure, development, fixation and hardening;
s12, step corrosion: etching the part uncovered by the photoresist to form a groove by using mixed acid, wherein the depth of the step is generally 5-200 mu m, the width is 1-10mil, and the depth and the width disconnect the P+ anode layer (3) and the P+ field limiting ring (4);
s13, cleaning: cleaning the surface of the silicon wafer by using the combination of acid washing and alkali washing;
s14, passivating: glass powder coated on the surface of the groove is melted and molded in a high-temperature furnace tube to form a stable, compact and sealed passivation layer (5);
s15, four times of photoetching: manufacturing an electrode, coating a layer of photoresist on the surface of a silicon wafer, and transferring a designed metallized window pattern to the surface of the silicon wafer through exposure, development, fixation and hardening;
s16, metallization: forming ohmic contact, plating a layer of nickel on the surface of the device, sintering under the protection of inert gas in a furnace tube to form ohmic contact, removing a nickel oxide layer in nitric acid with the temperature of more than 70 ℃, and then plating a layer of nickel and gold, wherein a secondary nickel/gold composite layer is a metal electrode (6);
s17, electrical property test: marking the chip with electrical failure according to the electrical design requirement;
s18, scribing: dividing a chip manufactured on a silicon wafer into individual semiconductor devices according to design dimensions;
s19, finishing the manufacturing of the diode chip.
2. The method for preparing a fermented extract of taro having a milk flavor according to claim 1, wherein the thickness is removed in the step S3 to be 5-50 μm.
3. The method for preparing a fermented extract of taro having a milk flavor according to claim 1, wherein the p+ field limit loop (4) has a width of 5 to 100 μm and a depth of 5 to 150 μm in step S7.
4. The method for preparing fermented taro extract with milk flavor according to claim 1, wherein in step S10, the depth of the boron p+ anode layer (3) is 5-150 μm and the depth of the p+ field limiter (4) after pushing is 5-250 μm.
5. The method for preparing fermented taro extract with milk flavor according to claim 1, wherein in step S16, the fermented taro extract is sintered under the protection of inert gas in a furnace tube at 500-700 ℃, and the inert gas is nitrogen.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310449354.3A CN116435179A (en) | 2023-04-25 | 2023-04-25 | Manufacturing method of semiconductor mesa diode chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310449354.3A CN116435179A (en) | 2023-04-25 | 2023-04-25 | Manufacturing method of semiconductor mesa diode chip |
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| CN116435179A true CN116435179A (en) | 2023-07-14 |
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