CN115223874A - Semiconductor structure and method of making the same - Google Patents

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method includes providing a substrate, and forming an isolation structure and an active region in the substrate; the steps of forming the isolation structure include: forming a groove in the substrate; forming A first insulating layer, the first insulating layer is located on the bottom and sidewalls of the groove; a second insulating layer is formed, and the second insulating layer is located on the surface of the first insulating layer, wherein part of the second insulating layer is removed, so that the second insulating layer is The top surface is lower than the top surface of the first insulating layer; a third insulating layer is formed, the third insulating layer partially covers the second insulating layer, and the first insulating layer, the second insulating layer and the third insulating layer fill the groove; forming a dielectric layer , the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer, as well as the active region, and fills the recess formed by removing part of the second insulating layer. The preparation method can avoid the formation of residues at the recess formed between the isolation structure and the active region, thereby affecting the performance of the semiconductor structure.

Description

Semiconductor structure and method of making the same

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background technique

During the preparation process of the semiconductor structure of the related art, an isolation region is formed between the active regions. Due to the different materials of the insulating layer, the etching efficiency of the isolation region is different. During the subsequent etching process, the insulation on the surface of the active region is The layer is etched to easily form a groove between the active region and the adjacent insulating layer. When the gate structure is formed by subsequent deposition, residues that are difficult to remove are easily formed in the groove and affect device performance.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for preparing a semiconductor structure, which can avoid forming a recess between the isolation structure and the active region, thereby preventing residues from being formed in the recess and affecting the performance of the semiconductor structure.

A method for fabricating a semiconductor structure according to an embodiment of the present invention includes: providing a substrate, and forming an isolation structure and an active region in the substrate; the step of forming the isolation structure includes: forming a groove in the substrate; forming a first an insulating layer, the first insulating layer is located on the bottom and sidewalls of the groove; a second insulating layer is formed, the second insulating layer is located on the surface of the first insulating layer, wherein a part of the second insulating layer is removed insulating layer, so that the top surface of the second insulating layer is lower than the top surface of the first insulating layer; forming a third insulating layer, the third insulating layer partially covers the second insulating layer, the first insulating layer The insulating layer, the second insulating layer and the third insulating layer fill the groove; a dielectric layer is formed, and the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and all the The active region is filled with the recess formed by removing part of the second insulating layer.

According to some embodiments of the present invention, the step of removing the part of the second insulating layer includes: forming a mask layer on the surface of the substrate exposing the second insulating layer, etching and removing part of the first insulating layer and the second insulating layer.

According to some embodiments of the present invention, in the step of removing part of the first insulating layer and the second insulating layer, the first insulating layer and the second insulating layer are simultaneously etched, and the first insulating layer and the second insulating layer are etched simultaneously. The etching rates of an insulating layer and the second insulating layer are different.

According to some embodiments of the present invention, in the step of removing part of the first insulating layer and the second insulating layer, the etching rate of the second insulating layer is greater than the etching rate of the first insulating layer.

According to some embodiments of the present invention, the etching depth of the second insulating layer is 18-20 nm.

According to some embodiments of the present invention, the thickness of the mask layer is 350nm-500nm, and the overlay accuracy is 0-8nm.

According to some embodiments of the present invention, the first insulating layer is formed by a thermal oxidation process, and the first insulating layer is silicon oxide.

According to some embodiments of the present invention, the second insulating layer is formed by a deposition process, and the second insulating layer is silicon nitride.

According to some embodiments of the present invention, after the dielectric layer is formed, the dielectric layer is thinned to expose the surface of the active region.

According to some embodiments of the present invention, the distance difference between the top surface of the second insulating layer and the top surface of the first insulating layer is 5 nm-10 nm.

According to some embodiments of the present invention, the thickness of the second insulating layer is 20 nm-100 nm.

According to some embodiments of the present invention, the thickness of the second insulating layer is 20 nm-50 nm.

The present invention also provides a semiconductor structure.

A semiconductor structure according to an embodiment of the present invention may include: a substrate in which an isolation structure, a groove, and an active region are formed; the isolation structure includes a first insulating layer, a second insulating layer, and a third insulating layer, and a dielectric layer, the insulating layer is located on the bottom and sidewalls of the groove, the second insulating layer is located on the surface of the first insulating layer, wherein the top surface of the second insulating layer is lower than the first insulating layer the top surface of the layer, the third insulating layer is located on the surface of the second insulating layer, the first insulating layer, the second insulating layer and the third insulating layer fill the groove, the dielectric layer covering the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and the active region.

According to some embodiments of the present invention, the height difference from the upper surface of the second insulating layer to the upper surface of the active region is 18-20 nm.

According to some embodiments of the present invention, the semiconductor structure further includes a gate structure formed on the active region.

According to some embodiments of the present invention, the third insulating layer does not cover the top surface of the second insulating layer.

According to the semiconductor structure and the manufacturing method thereof according to the embodiments of the present invention, by removing part of the second insulating layer, the top surface of the second insulating layer is lower than the top surface of the first insulating layer, and a dielectric layer is formed to fill the second insulating layer and the second insulating layer is removed. After part of the recess, in the subsequent etching, even if the dielectric layer is over-etched, because the height of the top surface of the second insulating layer is lower than that of the first insulating layer, it can avoid over-etching and cause damage to the second insulating layer. A recess is formed between the layer and the active region, which affects the performance of the semiconductor structure, and in the prior art, since the first insulating layer is over-etched, there is a recess between the second insulating layer and the active region. , the recess will cause the first insulating layer between the second insulating layer and the active region to be further over-etched, so by preventing the formation of the recess between the second insulating layer and the active region, the subsequent process can also be further reduced The middle isolation structure, especially the etching of the first insulating layer.

Description of drawings

1-10 are cross-sectional views of steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

Reference number:

100: semiconductor structure;

1: substrate, 11: active region, 12: mask layer;

2: isolation structure, 21: first insulating layer, 22: second insulating layer, 23: third insulating layer, 24: dielectric layer, 25: recess;

3: gate structure, 31: polysilicon layer, 32: metal gate, 33: metal material layer, 34: metal nitride layer;

4: gate mask layer, 41: silicon nitride layer, 42: spin coating mask layer, 43: oxynitride layer;

5: photoresist pattern;

61: the sidewall silicon nitride layer on the side of the gate structure, 62: the sidewall silicon oxide layer.

Detailed ways

A semiconductor structure 100 and a manufacturing method thereof proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

The semiconductor structure 100 and a method for fabricating the same according to embodiments of the present invention are described below with reference to the accompanying drawings.

As shown in FIG. 1 to FIG. 10 , a method for fabricating a semiconductor structure 100 according to an embodiment of the present invention may include: providing a substrate 1 , forming an isolation structure 2 and an active region 11 in the substrate 1 ; forming the isolation The steps of the structure 2 include: forming a groove in the substrate 1; forming a first insulating layer 21, the first insulating layer 21 is located on the bottom and sidewalls of the groove; forming a second insulating layer 22, the first insulating layer 21 Two insulating layers 22 are located on the surface of the first insulating layer 21, wherein part of the second insulating layer 22 is removed, so that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21; A third insulating layer 23 is formed, the third insulating layer 23 partially covers the second insulating layer 22, and the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 fill the groove; forming a dielectric layer 4, the dielectric layer 4 covers the surface of the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 and the active region 11 and fills up and removes part of the second insulating layer 23. The recess 25 formed by the insulating layer 22 .

Specifically, in the step of providing the substrate 1, the substrate 1 may be, but not limited to, a silicon substrate, and this specific embodiment is described by taking the substrate 1 as a silicon substrate as an example. In other examples, the substrate 1 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 1 is used to support the device structure above it. The top surface of the substrate 1 refers to the surface of the substrate 1 facing the device structure.

1-7, the isolation structure 2 and the active region 11 are formed in the substrate 1. Specifically, the active region 11 can be formed by etching the substrate 1 by etching the substrate 1. A plurality of active regions 11 can be formed, and the plurality of active regions 11 are distributed in an array. The active regions 11 can be used to form device structures, and the isolation structure 2 surrounds the active regions 11 .

1-7, the step of forming the isolation structure 2 may include the following steps:

Forming grooves in the substrate 1, specifically, the substrate 1 can be photolithographically formed by a photolithography process to form the grooves, and the substrate 1 can be divided into a plurality of active regions 11 through the grooves, and the isolation structure 2 can be are formed in the grooves to form isolation between the active regions 11 .

As shown in FIG. 1 , a first insulating layer 21 is formed, and the first insulating layer 21 is located at the bottom and sidewalls of the groove. Specifically, at least one of a chemical vapor deposition method, a physical vapor deposition method and an atomic layer deposition method can be used. A first insulating layer 21 is formed by deposition, and the first insulating layer 21 covers the inner wall surface of the groove. An insulating material is deposited on the surface of the region 11 , and then the insulating material located on the surface of the active region 11 is removed, and only the insulating material located in the groove is left to form the first insulating layer 21 . Optionally, a chemical mechanical polishing process may be used to remove the insulating material on the active surface, and the top surface of the first insulating layer 21 may be flush with the top surface of the active region 11 .

A second insulating layer 22 is formed on the surface of the first insulating layer 21. The material of the second insulating layer 22 is different from that of the first insulating layer 21, that is, the first insulating layer 21 and the second insulating layer 22 have a certain selective etching ratio. Under the same etching conditions, the etching rates of the first insulating layer 21 and the second insulating layer 22 are different.

The third insulating layer 23 is formed, the third insulating layer 23 is located on the surface of the second insulating layer 22, the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 can fill the groove, wherein the third insulating layer 23 covers the first insulating layer 23. The bottom and sidewalls of the two insulating layers 22 . The third insulating layer 23, the first insulating layer 21 and the second insulating layer 22 together fill the grooves, and it is understood that the isolation structure 2 can also be formed as a stacked structure including more insulating layers, (for example, an ONO stacked structure , that is, the structure in which the oxide layer and the nitride layer are alternated (such as oxide layer-nitride layer-oxide layer), the present invention may not be particularly limited, in the embodiment of the present invention, the first insulating layer 21, the second insulating layer 22 and the third insulating layer are used. The insulating layer 23 fills the groove as an example for description. Optionally, the material of the third insulating layer 23 may be the same as that of the first insulating layer 21 , for example, both the first insulating layer 21 and the third insulating layer 23 may be silicon oxide layers.

As shown in FIG. 2-FIG. 4, part of the second insulating layer 22 is removed, so that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21, so that the first insulating layer 21 can be prevented from being over-etched. A recess is formed between the active region 11 and the second insulating layer 22 . In this step, wet etching or dry etching can be used to etch the second insulating layer 22 to remove part of the second insulating layer 22. Further, the height of the removed second insulating layer 22 is not lower than that of the subsequent The height at which the first insulating layer 21 is over-etched in the etching process.

As shown in FIG. 5 , a dielectric layer 4 is formed, the dielectric layer 4 covers the surfaces of the first insulating layer 21 , the second insulating layer 22 and the third insulating layer 23 and the active region 11 and fills up the removed part. The recess 25 formed by the second insulating layer 22 is described. In other words, the dielectric layer 4 covers the first insulating layer 21 , the second insulating layer 22 , the third insulating layer 23 and the top surface of the active region 11 , and fills and removes part of the second insulating layer 22 before filling the third insulating layer 23 The recess 25 formed between the first insulating layer 21 and the first insulating layer 21 forms the isolation structure 2. In this way, during the subsequent etching, even if the dielectric layer 4 is over-etched, the height of the top surface of the second insulating layer 22 is lower than that of the first insulating layer 22. a top surface of the insulating layer 21, so as to avoid over-etching resulting in the formation of recesses 25 between the second insulating layer 22 and the active region 11 and affecting the performance of the semiconductor structure 100, and in the prior art, due to the first insulating layer 21 is over-etched, resulting in a recess between the second insulating layer 22 and the active region 11. Due to the etching characteristics, the recess will cause the first insulating layer 21 between the second insulating layer 22 and the active region 11 to be further Over-etching, therefore, by preventing the formation of recesses between the second insulating layer 22 and the active region 11, the etching of the isolation structure 2, especially the first insulating layer 21 in the subsequent process can also be further reduced.

In some embodiments of the present invention, as shown in FIG. 2 , the step of removing part of the second insulating layer 22 may include: forming a mask layer 12 exposing the second insulating layer 22 on the surface of the substrate 1 , and removing it by etching Part of the second insulating layer 22, wherein the mask layer 12 can cover the surface of the active region 11 and part of the surface of the isolation structure 2, and only the surface of the second insulating layer 22 can be exposed, so as to facilitate the etching of the second insulating layer 22 . Optionally, in this step, part of the first insulating layer 21 may be removed by etching at the same time, and specifically, the mask layer 12 may expose the second insulating layer 22 and a part of the first insulating layer 21 adjacent to the second insulating layer 22 , when the second insulating layer 22 is etched, a part of the first insulating layer 21 adjacent to the second insulating layer 22 can be etched and removed at the same time, so that the second insulating layer 22 can be etched cleanly, avoiding the first insulating layer 22 The upper sidewall of the insulating layer 21 has a portion of the second insulating layer 22 remaining. Moreover, the thickness of the second insulating layer 22 is relatively small, and the formation of the mask layer 12 and the lithography registration are also facilitated by etching a part of the first insulating layer 21 and the second insulating layer 22 at the same time. The mask layer 12 may be removed after removing part of the second insulating layer 22 .

In some embodiments of the present invention, the first insulating layer 21 , the third insulating layer 23 and the dielectric layer 4 may be of the same material, for example, the first insulating layer 21 , the third insulating layer 23 and the dielectric layer 4 may all be silicon oxide In the step of removing part of the second insulating layer 22, the mask layer 12 may cover the active region 11, and at the same time, part of the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 are etched and removed, wherein the The etching depth of the second insulating layer 22 is greater than the etching depth of the first insulating layer 21 and the third insulating layer 23 , so that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21 and the third insulating layer 23 On the top surface, the dielectric layer 4 is then formed. The dielectric layer 4 can fill the recesses 25 formed by the removed part of the second insulating layer 22, while the dielectric layer 4 covers the first insulating layer 21 and the third insulating layer 23. The materials of the first insulating layer 21 and the third insulating layer 23 are the same, so in the step of etching the second insulating layer 22, the mask layer 12 can only cover the active region 11, and the subsequent formation of the dielectric layer 4 can fill the second insulating layer 22. An insulating layer 21 and a third insulating etched portion.

In some examples of the present invention, the mask layer 12 may be a photoresist layer, that is, a photoresist layer exposing the second insulating layer 22 is directly formed on the surface of the substrate 1, and a photolithography process is performed to remove part of the second insulating layer 22. The second insulating layer 22 has simple process and precise etching.

In some embodiments of the present invention, the thickness of the mask layer 12 may be 350nm-500nm, for example, the thickness of the mask layer 12 may be 350nm, 400nm, 450nm or 500nm, and the overlay accuracy may be 0-8nm, and further Ground, the overlay accuracy can be 0-4nm.

In some embodiments of the present invention, in the process of removing part of the first insulating layer 21 and the second insulating layer 22, the first insulating layer 21 and the second insulating layer 22 may be etched at the same time, and the first insulating layer 21 The etching rate is different from that of the second insulating layer 22, that is, the etching rates of the first insulating layer 21 and the second insulating layer 22 are different under the same etching conditions. For example, the first insulating layer 21 and the second insulating layer 22 may have high Select the etch ratio. Optionally, the etching rate of the second insulating layer 22 is greater than the etching rate of the first insulating layer 21, so that during the etching process, it can be ensured that the top surface of the second insulating layer 22 after etching is lower than The top surface of the first insulating layer 21 and the top surface of the second insulating layer 22 are lower than the top surface of the active region 11 , so as to avoid forming depressions on the upper side of the active region 11 and affecting the execution of other subsequent processes.

In some embodiments of the present invention, the first insulating layer 21 may be silicon oxide, and the second insulating layer 22 may be silicon nitride or silicon oxynitride. Optionally, the first insulating layer 21 may be formed by a thermal oxidation process. For example, a thermal oxidation process may be performed on the sidewalls and bottom of the active region 11 to form the first insulating layer 21. Of course, it should be understood that a deposition process may be directly used to form the first insulating layer on the sidewalls and bottom of the active region 11. twenty one. In some specific examples, the second insulating layer 22 may be silicon nitride, and the second insulating layer 22 may be formed by a deposition process. For example, the second insulating layer 22 may be formed by chemical vapor deposition, physical vapor deposition, and atomic layer deposition. A process in the deposition method is formed by deposition.

In some embodiments of the present invention, the etching depth of the second insulating layer 22 is 18-20 nm, that is, the height of the removed part of the second insulating layer 22 is 18-20 nm, so as to prevent the second insulating layer The layer 22 is etched too much to affect the insulating effect, which can also reduce the increase in the difficulty of etching due to over-etching, and further can prevent the etching depth from being too small, resulting in the subsequent excessive etching depth of the first insulating layer 21 It is greater than the etching depth of the second insulating layer 22 to form a recess between the second insulating layer 22 and the active region 11. It should be noted that the depth and height here refer to the depth and height along the thickness direction of the substrate 1, That is, the height and depth in the up-down direction of FIG. 3 . Further, the depth of the second insulating layer 22 may be 18 nm, 18.5 nm, 19 nm, 19.5 or 20 nm.

In some embodiments of the present invention, as shown in FIGS. 5-6 , after the dielectric layer 4 is formed, the dielectric layer 4 may be thinned, and the surface of the active region 11 may be exposed to have a In order to facilitate the formation of the gate structure 3, specifically, in order to enable the dielectric layer 4 formed by deposition to fill the recess formed after the second insulating layer 22 is partially removed, the dielectric layer 4 needs to be deposited to a sufficient thickness to fill the recess 25, so that As a result, the thickness of the deposited dielectric layer 4 on the substrate 1 is relatively large, which needs to be thinned to ensure the performance of the formed semiconductor structure 100 .

In some specific examples of the present invention, the deposition thickness of the dielectric layer 4 may be 90 nm-110 nm, for example, the deposition thickness of the dielectric layer 4 may be 100 nm, and the thinning of the dielectric layer 4 may be performed multiple times. In order to facilitate the control of the thinning thickness of the dielectric layer 4 . In some examples, as shown in FIG. 5 , a chemical mechanical polishing process may be used to thin the dielectric layer 4 to thin the dielectric layer 4 to a thickness of 10 nm-20 nm on the top surface of the active region 11 , and then as shown in FIG. As shown in 6, chemical vapor etching can be used to thin the dielectric layer 4 to a thickness of 0-2 nm on the top surface of the active region 11. In this step, hydrofluoric acid can be used as an etchant and the dielectric layer can be controlled by etching. Layer 4 is thinned down to a thickness of 0-2 nm remaining on the top surface of active region 11 .

When the second insulating layer 22 is etched, part of the first insulating layer 21 is etched at the same time, so that the top surface of the first insulating layer 21 is lowered, and the top surface of the second insulating layer 22 is connected to the first insulating layer 21. There is a distance difference between the top surface of an insulating layer 21. In some embodiments of the present invention, the distance difference between the top surface of the second insulating layer 22 and the top surface of the first insulating layer 21 is 5 nm-10 nm. The distance difference between the top surface of the insulating layer 22 and the top surface of the first insulating layer 21 can be 5 nm, 7 nm, 9 nm and 10 nm, so that even if the first insulating layer 21 is over-etched by the subsequent etching process, the The second insulating layer 22 is flush with the first insulating layer 21 or has a small height difference, resulting in the formation of a recess between the second insulating layer 22 and the active region 11 .

In some embodiments of the present invention, the thickness of the second insulating layer 22 may be 20 nm-100 nm. Optionally, the thickness of the second insulating layer 22 may be 20 nm-50 nm, and further, the thickness of the second insulating layer 22 may be 20 nm, 30 nm, 40 nm or 50 nm, so that the active region 11 in the semiconductor structure 100 can be improved. insulating effect between.

In some embodiments of the present invention, the method for forming the semiconductor structure 100 shown in FIG. 7 to FIG. 10 may further include: forming the gate structure 3 on the active region 11 , specifically, as shown in FIG. 7 , A polysilicon layer 31 and a metal gate 32 are sequentially formed on the surface of the dielectric layer 4. Optionally, the metal gate 32 may be at least one of a metal material and a metal nitride material. For example, the metal gate 32 may be is a metal material layer such as a metal tungsten layer, or the metal gate 32 may be a metal nitride layer such as a titanium nitride layer. In the example shown in FIG. 7 , the metal gate 32 may include a metal material layer 33 and a metal The nitride layer 34 is, for example, a titanium nitride layer 34 formed on the surface of the polysilicon layer 31 and a metal tungsten layer 33 formed on the surface of the titanium nitride layer 34 .

As shown in FIG. 7-FIG. 8, a gate mask layer 4 is formed on the surface of the metal gate 32 for forming a mask to etch the metal gate 32, the polysilicon layer 31 and the dielectric layer 4, as shown in FIG. 8 , a photoresist pattern 5 is formed on the surface of the gate mask layer 4 to define the area where the gate structure 3 is formed, and then a photolithography process is performed on the polysilicon layer 31 and the metal gate 32 and the dielectric layer on the surface of the substrate 1 4. Etching is performed to form gate structure 3. Optionally, the gate mask layer 4 may be formed as a combined mask layer 12. In the example shown in FIG. 8, the gate mask layer 4 may include a silicon nitride layer 41, a spin-on mask A film layer 42 and a silicon oxynitride layer 43, wherein the silicon nitride layer 41 is located on the surface of the metal gate 32, the spin coating mask layer 42 is located on the surface of the silicon nitride layer 43, and the silicon oxynitride layer 43 on the surface of the spin coating mask layer 42 .

As shown in FIG. 10 , an insulating layer is then formed on the surface of the gate structure 3 and the sidewalls of the part of the dielectric layer 4 located under the gate structure 3 . Specifically, an insulating layer may be formed on the surface of the gate structure 3 and on the sidewall of the gate structure 3 A silicon nitride layer 61 is deposited on the sidewalls of the part of the dielectric layer 4 below 3 , and then a sidewall silicon oxide layer 62 is formed on the sidewalls of the silicon nitride layer 61 . In the step of forming the gate structure 3, part of the gate mask layer 4 on the surface of the gate structure 3 can be reserved, for example, part of the silicon nitride layer 41 on the surface of the gate structure 3 can be reserved for subsequent insulating formation layer, and then deposit the sidewall silicon nitride layer 61 on the sidewall of the gate structure 3, the sidewall of a part of the dielectric layer 4 under the gate structure 3, and the sidewall of the remaining silicon nitride layer to form a spacer silicon nitride layer 61, and then deposit on the sidewall of the sidewall spacer 4. A spacer silicon oxide layer 62 is formed on the surface of the silicon nitride layer.

Since the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21 in the previous process, and the dielectric layer 4 is formed subsequently, the second insulating layer can be prevented from forming during the step of forming the gate structure 3 A recess is formed between the active region 22 and the active region 11 to affect subsequent processes and the performance of the semiconductor structure 100 .

The present invention also provides a semiconductor structure 100 .

A semiconductor according to an embodiment of the present invention may include a substrate 1 in which an isolation structure 2, a groove and an active region 11 are formed; the isolation structure 2 includes a first insulating layer 21, a second insulating layer 22 and The third insulating layer 23 and the dielectric layer 4 are located on the bottom and sidewalls of the groove, and the second insulating layer 22 is located on the surface of the first insulating layer 21 , wherein a part of the second insulating layer is removed. insulating layer 22, so that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21, the third insulating layer 23 is located on the surface of the second insulating layer 22, and the first insulating layer Layer 21 , the second insulating layer 22 and the third insulating layer 23 fill the grooves, and the dielectric layer 4 covers the surfaces of the first insulating layer 21 , the second insulating layer 22 and the third insulating layer 23 and the active region 11 and fill up the recess 25 formed by removing part of the second insulating layer 22 .

Therefore, when other structures such as the gate structure 3 are subsequently formed on the semiconductor structure 100, for example, when the semiconductor structure 100 is subsequently etched, even if the dielectric layer 4 is over-etched, the second insulating layer 22 The height of the top surface is reduced, so as to avoid over-etching resulting in the formation of recesses between the second insulating layer 22 and the active region 11 to affect the performance of the semiconductor structure 100, and compared with the prior art, since the first insulating layer 21 is Excessive etching, resulting in a recess between the second insulating layer 22 and the active region 11, due to the characteristics of the etching, the recess will cause the first insulating layer 21 between the second insulating layer 22 and the active region 11 to be further overetched Therefore, the semiconductor structure 100 of the embodiment of the present invention can further reduce the etching of the isolation structure 2, especially the first insulating layer 21 in the subsequent process by preventing the formation of a recess between the second insulating layer 22 and the active region 11. eclipse.

According to some embodiments of the present invention, the third insulating layer 23 does not cover the top surface of the second insulating layer 22 .

In some embodiments of the present invention, the height difference between the upper surface of the second insulating layer 22 and the upper surface of the active region 11 is 18-20 nm.

In some embodiments of the present invention, the semiconductor structure 100 may further include a gate structure 3 formed on the active region 11 .

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as the present invention. the scope of protection of the invention.

Claims (16)

1. a preparation method of a semiconductor structure, is characterized in that, comprises: A substrate is provided, and an isolation structure and an active region are formed in the substrate; the step of forming the isolation structure includes: forming grooves in the substrate; forming a first insulating layer, the first insulating layer is located on the bottom and sidewalls of the groove; forming a second insulating layer, the second insulating layer is located on the surface of the first insulating layer, wherein part of the second insulating layer is removed so that the top surface of the second insulating layer is lower than the first insulating layer the top surface; forming a third insulating layer, the third insulating layer partially covering the second insulating layer, the first insulating layer, the second insulating layer and the third insulating layer filling the groove; A dielectric layer is formed, the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and the active region and fills the recess formed by removing part of the second insulating layer. 2 . The method for fabricating a semiconductor structure according to claim 1 , wherein the step of removing the part of the second insulating layer comprises: forming a mask layer on the surface of the substrate to expose the second insulating layer, 2 . Part of the first insulating layer and the second insulating layer are removed by etching. 3 . The method for fabricating a semiconductor structure according to claim 2 , wherein in the step of removing part of the first insulating layer and the second insulating layer, the first insulating layer and the second insulating layer are removed simultaneously. 4 . The second insulating layer is etched, and the etching rates of the first insulating layer and the second insulating layer are different. 4 . The method for fabricating a semiconductor structure according to claim 3 , wherein in the step of removing part of the first insulating layer and the second insulating layer, the etching rate of the second insulating layer is greater than The etch rate of the first insulating layer. 5 . The method for preparing a semiconductor structure according to claim 4 , wherein the etching depth of the second insulating layer is 18-20 nm. 6 . 6 . The method for preparing a semiconductor structure according to claim 2 , wherein the thickness of the mask layer is 350 nm-500 nm, and the overetching precision is 0-8 nm. 7 . 7 . The method for fabricating a semiconductor structure according to claim 1 , wherein the first insulating layer is formed by a thermal oxidation process, and the first insulating layer is silicon oxide. 8 . 8 . The method for fabricating a semiconductor structure according to claim 7 , wherein the second insulating layer is formed by a deposition process, and the second insulating layer is silicon nitride. 9 . 9 . The method for fabricating a semiconductor structure according to claim 1 , wherein after the dielectric layer is formed, the dielectric layer is thinned to expose the surface of the active region. 10 . 10 . The method of claim 1 , wherein the distance difference between the top surface of the second insulating layer and the top surface of the first insulating layer is 5 nm-10 nm. 11 . 11 . The method for fabricating a semiconductor structure according to claim 1 , wherein the thickness of the second insulating layer is 20 nm-100 nm. 12 . 12 . The method for fabricating a semiconductor structure according to claim 11 , wherein the thickness of the second insulating layer is 20 nm-50 nm. 13 . 13. A semiconductor structure, characterized in that it comprises: a substrate, in which an isolation structure, a groove and an active region are formed; The isolation structure includes a first insulating layer, a second insulating layer, a third insulating layer and a dielectric layer, the insulating layer is located on the bottom and sidewalls of the groove, and the second insulating layer is located on the first insulating layer layer surface, wherein the top surface of the second insulating layer is lower than the top surface of the first insulating layer, the third insulating layer partially covers the second insulating layer, the first insulating layer, the The second insulating layer and the third insulating layer fill the groove, and the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and the active region. 14 . The semiconductor structure of claim 13 , wherein a height difference between the upper surface of the second insulating layer and the upper surface of the active region is 18-20 nm. 15 . 15. The semiconductor structure of claim 13, wherein the third insulating layer does not cover the top surface of the second insulating layer. 16. The semiconductor structure of claim 13, further comprising a gate structure formed on the active region.

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