CN115223874A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN115223874A
CN115223874A CN202210866551.0A CN202210866551A CN115223874A CN 115223874 A CN115223874 A CN 115223874A CN 202210866551 A CN202210866551 A CN 202210866551A CN 115223874 A CN115223874 A CN 115223874A
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China
Prior art keywords
insulating layer
layer
forming
active region
top surface
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Chinese (zh)
Inventor
林超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210866551.0A priority Critical patent/CN115223874A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the steps of providing a substrate, and forming an isolation structure and an active region in the substrate; the step of forming the isolation structure comprises: forming a groove in the substrate; forming a first insulating layer, wherein the first insulating layer is positioned at the bottom and the side wall of the groove; forming a second insulating layer on the surface of the first insulating layer, wherein part of the second insulating layer is removed so that the top surface of the second insulating layer is lower than that of the first insulating layer; forming a third insulating layer, wherein the third insulating layer partially covers the second insulating layer, and the first insulating layer, the second insulating layer and the third insulating layer fill the groove; and forming a dielectric layer, wherein the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and the active region and is filled in the recess formed by removing part of the second insulating layer. The preparation method can avoid the influence of residues formed at the position of a recess formed between the isolation structure and the active region on the performance of the semiconductor structure.

Description

Semiconductor structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
In the preparation process of the semiconductor structure in the related art, an isolation region is formed between active regions, the isolation region has different etching efficiency due to different insulating layer materials, when an etching process is performed subsequently, an insulating layer on the surface of the active region is etched, so that a groove is easily formed between the active region and an adjacent insulating layer, and when a gate structure is formed by subsequent deposition, residues which are difficult to remove are easily formed in the groove, so that the performance of a device is affected.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor structure, which can avoid forming a recess between an isolation structure and an active region, and further prevent residues from being formed at the recess to influence the performance of the semiconductor structure.
The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and forming an isolation structure and an active region in the substrate; the step of forming the isolation structure comprises: forming a groove in the substrate; forming a first insulating layer, wherein the first insulating layer is positioned at the bottom and the side wall of the groove; forming a second insulating layer on the surface of the first insulating layer, wherein part of the second insulating layer is removed so that the top surface of the second insulating layer is lower than the top surface of the first insulating layer; forming a third insulating layer partially covering the second insulating layer, wherein the first insulating layer, the second insulating layer and the third insulating layer fill the groove; and forming a dielectric layer, wherein the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer and the active region and is filled with the recess formed by removing part of the second insulating layer.
According to some embodiments of the invention, the step of removing the portion of the second insulating layer comprises: and forming a mask layer exposing the second insulating layer on the surface of the substrate, and etching to remove part of the first insulating layer and the second insulating layer.
According to some embodiments of the present invention, in the step of removing a portion of the first insulating layer and the second insulating layer, the first insulating layer and the second insulating layer are etched at the same time, and the etching rates of the first insulating layer and the second insulating layer are different.
According to some embodiments of the invention, in the step of removing a portion of the first insulating layer and the second insulating layer, an etching rate of the second insulating layer is greater than an etching rate of the first insulating layer.
According to some embodiments of the invention, the second insulating layer is etched to a depth of 18-20nm.
According to some embodiments of the invention, the mask layer has a thickness of 350nm to 500nm and an alignment precision of 0nm to 8nm.
According to some embodiments of the invention, the first insulating layer is formed using a thermal oxidation process, and the first insulating layer is silicon oxide.
According to some embodiments of the invention, the second insulating layer is formed using a deposition process, the second insulating layer being silicon nitride.
According to some embodiments of the invention, after the dielectric layer is formed, the dielectric layer is thinned and the surface of the active region is exposed.
According to some embodiments of the invention, a difference between a top surface of the second insulating layer and a top surface of the first insulating layer is 5nm to 10nm.
According to some embodiments of the invention, the second insulating layer is 20nm to 100nm thick.
According to some embodiments of the invention, the second insulating layer is 20nm to 50nm thick.
The invention also provides a semiconductor structure.
The semiconductor structure according to an embodiment of the present invention may include: the semiconductor device comprises a substrate, wherein an isolation structure, a groove and an active region are formed in the substrate; the isolation structure comprises a first insulation layer, a second insulation layer, a third insulation layer and a dielectric layer, wherein the insulation layers are located at the bottom and the side wall of the groove, the second insulation layer is located on the surface of the first insulation layer, the top surface of the second insulation layer is lower than that of the first insulation layer, the third insulation layer is located on the surface of the second insulation layer, the groove is filled with the first insulation layer, the second insulation layer and the third insulation layer, and the dielectric layer covers the surfaces of the first insulation layer, the second insulation layer and the third insulation layer and the active region.
According to some embodiments of the invention, a height difference from an upper surface of the second insulating layer to an upper surface of the active region is 18-20nm.
According to some embodiments of the invention, the semiconductor structure further comprises a gate structure formed on the active region.
According to some embodiments of the invention, the third insulating layer does not cover a top surface of the second insulating layer.
According to the semiconductor structure and the preparation method thereof provided by the embodiment of the invention, the top surface of the second insulating layer is lower than the top surface of the first insulating layer by removing part of the second insulating layer, and the dielectric layer is formed to fill the recess of the second insulating layer after the part of the second insulating layer is removed, so that even if the dielectric layer is over-etched in the subsequent etching process, the top surface of the second insulating layer is lower than the top surface of the first insulating layer, thereby avoiding the recess formed between the second insulating layer and the active region due to the over-etching to influence on the performance of the semiconductor structure.
Drawings
Fig. 1-10 are cross-sectional views of steps of a method of fabricating a semiconductor structure according to an embodiment of the present invention.
Reference numerals are as follows:
100: a semiconductor structure;
1: substrate, 11: active region, 12: a mask layer;
2: isolation structure, 21: first insulating layer, 22: second insulating layer, 23: third insulating layer, 24: dielectric layer, 25: recessing;
3: gate structure, 31: polysilicon layer, 32: metal gate, 33: metallic material layer, 34: a metal nitride layer;
4: gate mask layer, 41: silicon nitride layer, 42: spin-on mask layer, 43: a nitrogen oxide layer;
5: a photoresist pattern;
61: sidewall silicon nitride layer of gate structure lateral part, 62: and a silicon oxide layer is arranged on the side wall.
Detailed Description
A semiconductor structure 100 and a method for fabricating the same according to the present invention are further described in detail with reference to the drawings and the detailed description below.
A semiconductor structure 100 and a method of fabricating the same according to an embodiment of the present invention are described below with reference to the accompanying drawings.
As shown in fig. 1-10, a method of fabricating a semiconductor structure 100 according to an embodiment of the present invention may include: providing a substrate 1, and forming an isolation structure 2 and an active region 11 in the substrate 1; the step of forming the isolation structure 2 comprises: forming a groove in the substrate 1; forming a first insulating layer 21, wherein the first insulating layer 21 is positioned at the bottom and the side wall of the groove; forming a second insulating layer 22, wherein the second insulating layer 22 is located on the surface of the first insulating layer 21, and wherein a portion of the second insulating layer 22 is removed such that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21; forming a third insulating layer 23, wherein the third insulating layer 23 partially covers the second insulating layer 22, and the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 fill the groove; and forming a dielectric layer 4, wherein the dielectric layer 4 covers the surfaces of the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 and the active region 11 and fills a recess 25 formed by removing part of the second insulating layer 22.
Specifically, in the step of providing the substrate 1, the substrate 1 may be, but is not limited to, a silicon substrate, and the substrate 1 is taken as a silicon substrate in the present embodiment as an example for description. In other examples, the substrate 1 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 1 is used to support the device structure above it. The top surface of the substrate 1 refers to the surface of the substrate 1 facing the device structure.
Referring to fig. 1 to 7, an isolation structure 2 and an active region 11 are formed in the substrate 1, specifically, the active region 11 may be formed by etching the substrate 1, a plurality of active regions 11 may be formed by etching the substrate 1, the plurality of active regions 11 are distributed in an array, the active regions 11 may be used to form a device structure, and the isolation structure 2 surrounds the active regions 11.
As shown in connection with fig. 1-7, the step of forming the isolation structure 2 may include the steps of:
a groove is formed in the substrate 1, and specifically, the substrate 1 may be subjected to photolithography through a photolithography process to form a groove, the substrate 1 may be divided into a plurality of active regions 11 through the groove, and the isolation structure 2 may be formed in the groove to form a structure for isolating between the active regions 11.
As shown in fig. 1, a first insulating layer 21 is formed, where the first insulating layer 21 is located at the bottom and the side wall of the groove, and specifically, at least one of a chemical vapor deposition method, a physical vapor deposition method, and an atomic layer deposition method may be used to form the first insulating layer 21, where the first insulating layer 21 covers the inner wall surface of the groove, and specifically, after the groove is formed, an insulating material may be deposited on the inner wall surface of the groove (i.e., the bottom and the side wall of the groove) and the surface of the active region 11, and then the insulating material located on the surface of the active region 11 is removed, and only the insulating material located in the groove is remained to form the first insulating layer 21. Alternatively, the insulating material on the active surface may be removed by a chemical mechanical polishing process, and the top surface of the first insulating layer 21 may be flush with the top surface of the active region 11.
Forming a second insulating layer 22 on the surface of the first insulating layer 21, wherein the material of the second insulating layer 22 is different from that of the first insulating layer 21, that is, the first insulating layer 21 and the second insulating layer 22 have a certain selective etching ratio, and under the same etching conditions, the etching rates of the first insulating layer 21 and the second insulating layer 22 are different.
And forming a third insulating layer 23, wherein the third insulating layer 23 is located on the surface of the second insulating layer 22, and the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 can fill the groove, wherein the third insulating layer 23 covers the bottom and the side wall of the second insulating layer 22. The third insulating layer 23, the first insulating layer 21 and the second insulating layer 22 fill the groove together, it is understood that the isolation structure 2 may also be formed as a stacked structure including more insulating layers (for example, an ONO stacked structure, i.e., a structure in which an oxide layer and a nitride layer are alternated, such as an oxide layer-nitride layer-oxide layer), the present invention is not particularly limited, and the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23 fill the groove in the embodiment of the present invention as an example. Alternatively, the material of the third insulating layer 23 may be the same as the first insulating layer 21, for example, both the first insulating layer 21 and the third insulating layer 23 may be silicon oxide layers.
As shown in fig. 2 to 4, a portion of the second insulating layer 22 is removed such that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21, so that the first insulating layer 21 can be prevented from being excessively etched to form a recess between the active region 11 and the second insulating layer 22. In this step, the second insulating layer 22 may be etched by wet etching or dry etching to remove a portion of the second insulating layer 22, and further, the height of the removed second insulating layer 22 is not lower than the height of the first insulating layer 21 excessively etched in the subsequent etching process.
As shown in fig. 5, a dielectric layer 4 is formed, and the dielectric layer 4 covers the surfaces of the first insulating layer 21, the second insulating layer 22, the third insulating layer 23 and the active region 11 and fills a recess 25 formed by removing a portion of the second insulating layer 22. In other words, the dielectric layer 4 covers the top surfaces of the first insulating layer 21, the second insulating layer 22, the third insulating layer 23 and the active region 11, and fills the recess 25 formed between the third insulating layer 23 and the first insulating layer 21 after removing a part of the second insulating layer 22, so as to form the isolation structure 2, so that, even if the dielectric layer 4 is over-etched in the subsequent etching process, since the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21, it is possible to avoid that the recess 25 is formed between the second insulating layer 22 and the active region 11 due to the over-etching, which may affect the performance of the semiconductor structure 100, and in the prior art, since the first insulating layer 21 is over-etched, which may cause the recess to be further over-etched between the second insulating layer 22 and the active region 11, the recess may further cause the etching of the first insulating layer 21 between the second insulating layer 22 and the active region 11, which may further reduce the etching of the isolation structure 2, particularly the first insulating layer 21 in the subsequent etching process.
In some embodiments of the present invention, as shown in fig. 2, the step of removing a portion of the second insulating layer 22 may include: forming a mask layer 12 exposing the second insulating layer 22 on the surface of the substrate 1, and etching to remove a part of the second insulating layer 22, wherein the mask layer 12 may cover the surface of the active region 11 and a part of the surface of the isolation structure 2, and only the surface of the second insulating layer 22 may be exposed, so as to etch the second insulating layer 22. Optionally, in this step, a portion of the first insulating layer 21 may be etched and removed at the same time, specifically, the mask layer 12 may expose the second insulating layer 22 and a portion of the first insulating layer 21 adjacent to the second insulating layer 22, and a portion of the first insulating layer 21 adjacent to the second insulating layer 22 may be etched and removed at the same time when the second insulating layer 22 is etched, so that the second insulating layer 22 can be etched clean, and a portion of the second insulating layer 22 remaining on the upper sidewall of the first insulating layer 21 is avoided. And the thickness of the second insulating layer 22 is small, the formation of the mask layer 12 and the photolithography registration are also facilitated by simultaneously etching a portion of the first insulating layer 21 and the second insulating layer 22. Wherein masking layer 12 may be removed after removing portions of the second insulating layer 22.
In some embodiments of the present invention, the first insulating layer 21, the third insulating layer 23 and the dielectric layer 4 may be made of the same material, for example, the first insulating layer 21, the third insulating layer 23 and the dielectric layer 4 may all be made of silicon oxide layers, in the step of removing a portion of the second insulating layer 22, the masking layer 12 may cover the active region 11, and simultaneously etch and remove a portion of the first insulating layer 21, the second insulating layer 22 and the third insulating layer 23, wherein the etching depth of the second insulating layer 22 is greater than that of the first insulating layer 21 and the third insulating layer 23, so that the top surface of the second insulating layer 22 is lower than that of the first insulating layer 21 and that of the third insulating layer 23, and then form the dielectric layer 4, the dielectric layer 4 may fill the recess 25 formed by the removed portion of the second insulating layer 22, and simultaneously cover the first insulating layer 21 and the third insulating layer 23, and the dielectric layer 4 is made of the same material as the first insulating layer 21 and the third insulating layer 23, so that in the step of etching the second insulating layer 22, the masking layer 12 may only cover the active region 11, and then form a portion of the dielectric layer 4 that is etched by filling the first insulating layer 21 and the third insulating layer 4.
In some examples of the present invention, the mask layer 12 may be a photoresist layer, that is, a photoresist layer exposing the second insulating layer 22 may be directly formed on the surface of the substrate 1, and a photolithography process is performed to remove a portion of the second insulating layer 22, which is simple and accurate in etching.
In some embodiments of the present invention, the thickness of the mask layer 12 may be 350nm to 500nm, for example, the thickness of the mask layer 12 is 350nm, 400nm, 450nm or 500nm, the alignment precision may be 0 to 8nm, and further, the alignment precision may be 0 to 4nm.
In some embodiments of the present invention, in the process of removing a portion of the first insulating layer 21 and the second insulating layer 22, the first insulating layer 21 and the second insulating layer 22 may be etched at the same time, and the etching rates of the first insulating layer 21 and the second insulating layer 22 are different, that is, the etching rates of the first insulating layer 21 and the second insulating layer 22 are different under the same etching condition, for example, the first insulating layer 21 and the second insulating layer 22 may have a high selective etching ratio. Optionally, the etching rate of the second insulating layer 22 is greater than that of the first insulating layer 21, so that during the etching process, the top surface of the etched second insulating layer 22 is lower than that of the first insulating layer 21, and the top surface of the second insulating layer 22 is lower than that of the active region 11, so that the formation of a recess on the side of the upper portion of the active region 11 can be avoided to affect the performance of other subsequent processes.
In some embodiments of the present invention, the first insulating layer 21 may be silicon oxide, the second insulating layer 22 may be silicon nitride or silicon oxynitride, and optionally, the first insulating layer 21 may be formed by a thermal oxidation process, for example, a thermal oxidation process may be performed on the sidewall and the bottom of the active region 11 to form the first insulating layer 21, although it is understood that the first insulating layer 21 may be formed on the sidewall and the bottom of the active region 11 by directly using a deposition process. In some specific examples, the second insulating layer 22 may be silicon nitride, and the second insulating layer 22 may be formed by a deposition process, for example, the second insulating layer 22 may be formed by deposition by one of a chemical vapor deposition method, a physical vapor deposition method, and an atomic layer deposition method.
In some embodiments of the present invention, the etching depth of the second insulating layer 22 is 18-20nm, that is, the height of the removed portion of the second insulating layer 22 is 18-20nm, so as to prevent the second insulating layer 22 from being excessively etched to affect the insulating effect, reduce the increase of the etching difficulty due to the over-etching, and further avoid the over-etching depth from being excessively small, so that the subsequent first insulating layer 21 is excessively etched to a depth greater than the etching depth of the second insulating layer 22 to form a recess between the second insulating layer 22 and the active region 11, where it should be noted that the depth and the height refer to the depth and the height along the thickness direction of the substrate 1, that is, the height and the depth in the vertical direction of fig. 3. Further, the depth of the second insulating layer 22 may be 18nm, 18.5nm, 19nm, 19.5 or 20nm.
In some embodiments of the present invention, as shown in fig. 5 to fig. 6, after the dielectric layer 4 is formed, the dielectric layer 4 may be thinned and the surface of the active region 11 may be exposed to facilitate the formation of the gate structure 3, and specifically, in order to enable the deposited dielectric layer 4 to fill the recess formed after the second insulating layer 22 is partially removed, the dielectric layer 4 needs to be deposited with a sufficient thickness to fill the recess 25, which results in a large thickness of the deposited dielectric layer 4 on the substrate 1, and needs to be thinned to ensure the performance of the formed semiconductor structure 100.
In some specific examples of the present invention, the deposition thickness of the dielectric layer 4 may be 90nm to 110nm, for example, the deposition thickness of the dielectric layer 4 may be 100nm, and the dielectric layer 4 may be thinned for multiple times to facilitate the control of the thinned thickness of the dielectric layer 4. In some examples, as shown in fig. 5, the dielectric layer 4 may be thinned using a chemical mechanical polishing process to thin the dielectric layer 4 to a thickness of 10nm to 20nm at the top surface of the active region 11, and then as shown in fig. 6, the dielectric layer 4 may be thinned to a thickness of 0 to 2nm at the top surface of the active region 11 using a chemical vapor etching, where hydrofluoric acid may be used as an etchant and the thinning of the dielectric layer 4 to a thickness of 0 to 2nm remaining at the top surface of the active region 11 is stopped by etching control.
When the second insulating layer 22 is etched, a portion of the first insulating layer 21 is etched at the same time, so that the top surface of the first insulating layer 21 is lowered, and there is a distance difference between the top surface of the second insulating layer 22 and the top surface of the first insulating layer 21, in some embodiments of the present invention, the distance difference between the top surface of the second insulating layer 22 and the top surface of the first insulating layer 21 is 5nm to 10nm, and the distance difference between the top surface of the second insulating layer 22 and the top surface of the first insulating layer 21 may be 5nm, 7nm, 9nm, and 10nm, thereby preventing a recess from being formed between the second insulating layer 22 and the active region 11 due to the fact that the second insulating layer 22 is flush with the first insulating layer 21 or the height difference is small even though the first insulating layer 21 is excessively etched by a subsequent etching process.
In some embodiments of the present invention, the second insulating layer 22 may have a thickness of 20nm to 100nm. Alternatively, the thickness of the second insulating layer 22 may be 20nm to 50nm, and further, the thickness of the second insulating layer 22 may be 20nm, 30nm, 40nm, or 50nm, so that the insulating effect between the active regions 11 in the semiconductor structure 100 can be improved.
In some embodiments of the present invention, the method for forming the semiconductor structure 100 described in conjunction with fig. 7-10 may further include: forming a gate structure 3 on the active region 11, specifically, as shown in fig. 7, sequentially forming a polysilicon layer 31 and a metal gate 32 on the surface of the dielectric layer 4, optionally, the metal gate 32 may be at least one of a metal material and a metal nitride material, for example, the metal gate 32 may be a metal material layer such as a metal tungsten layer, or the metal gate 32 may be a metal nitride layer such as a titanium nitride layer, and in the example shown in fig. 7, the metal gate 32 may include a metal material layer 33 and a metal nitride layer 34, for example, a titanium nitride layer 34 formed on the surface of the polysilicon layer 31 and a metal tungsten layer 33 formed on the surface of the titanium nitride layer 34.
As shown in fig. 7-8, a gate mask layer 4 is formed on the surface of the metal gate 32 to form a mask for etching the metal gate 32, the polysilicon layer 31 and the dielectric layer 4, as shown in fig. 8, a photoresist pattern 5 is formed on the surface of the gate mask layer 4 to define a region for forming the gate structure 3, and then a photolithography process is performed to etch the polysilicon layer 31, the metal gate 32 and the dielectric layer 4 on the surface of the substrate 1 to form the gate structure 3. Alternatively, the gate mask layer 4 may be formed as a combined mask layer 12, and in the example shown in fig. 8, the gate mask layer 4 may include a silicon nitride layer 41, a spin-on mask layer 42, and a silicon oxynitride layer 43, where the silicon nitride layer 41 is located on the surface of the metal gate 32, the spin-on mask layer 42 is located on the surface of the silicon nitride layer 43, and the silicon oxynitride layer 43 is located on the surface of the spin-on mask layer 42.
As shown in fig. 10, an insulating layer is then formed on the surface of the gate structure 3 and on the sidewall of a portion of the dielectric layer 4 located below the gate structure 3, specifically, a silicon nitride layer 61 may be deposited on the surface of the gate structure 3 and on the sidewall of a portion of the dielectric layer 4 located below the gate structure 3, and then a sidewall silicon oxide layer 62 is formed on the sidewall of the silicon nitride layer 61. In the step of forming the gate structure 3, a part of the gate mask layer 4 on the surface of the gate structure 3 may be reserved, for example, a part of the silicon nitride layer 41 on the surface of the gate structure 3 may be reserved for forming an insulating layer in the following step, then a sidewall silicon nitride layer 61 is formed on the sidewall of the gate structure 3, the sidewall of a part of the dielectric layer 4 under the gate structure 3, and the sidewall of the reserved silicon nitride layer by deposition, and then a sidewall silicon oxide layer 62 is formed on the surface of the sidewall silicon nitride layer.
Since the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21 in the previous process and the dielectric layer 4 is formed subsequently, the formation of a recess between the second insulating layer 22 and the active region 11 in the step of forming the gate structure 3 can be prevented from affecting the performance of the subsequent process and the semiconductor structure 100.
The invention also provides a semiconductor structure 100.
The semiconductor according to the embodiment of the invention can comprise a substrate 1, wherein an isolation structure 2, a groove and an active region 11 are formed in the substrate 1; the isolation structure 2 includes a first insulating layer 21, a second insulating layer 22, a third insulating layer 23, and a dielectric layer 4, where the insulating layers are located at the bottom and the side wall of the groove, the second insulating layer 22 is located on the surface of the first insulating layer 21, wherein a portion of the second insulating layer 22 is removed, so that the top surface of the second insulating layer 22 is lower than the top surface of the first insulating layer 21, the third insulating layer 23 is located on the surface of the second insulating layer 22, the groove is filled with the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23, and the dielectric layer 4 covers the surfaces of the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23, the active region 11, and fills the recess 25 formed by removing a portion of the second insulating layer 22.
Therefore, when other structures such as the gate structure 3 are formed on the semiconductor structure 100 in the subsequent process, for example, when the semiconductor structure 100 is etched in the subsequent process, even if the dielectric layer 4 is over-etched, the top surface of the second insulating layer 22 is lowered, so that it is possible to avoid that the performance of the semiconductor structure 100 is affected by the recess formed between the second insulating layer 22 and the active region 11 due to over-etching of the dielectric layer 4, and compared with the prior art, because the recess is formed between the second insulating layer 22 and the active region 11 due to over-etching of the first insulating layer 21, and the recess is further over-etched due to etching characteristics, the semiconductor structure 100 according to the embodiment of the present invention can further reduce the etching of the isolation structure 2, particularly the first insulating layer 21, in the subsequent process by preventing the recess from being formed between the second insulating layer 22 and the active region 11.
According to some embodiments of the present invention, the third insulating layer 23 does not cover the top surface of the second insulating layer 22.
In some embodiments of the present invention, the height difference from the upper surface of the second insulating layer 22 to the upper surface of the active region 11 is 18-20nm.
In some embodiments of the present invention, the semiconductor structure 100 may further include a gate structure 3, and the gate structure 3 is formed on the active region 11.
The above is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and embellishments can be made without departing from the principle of the present invention, and these modifications and embellishments should also be regarded as the protection scope of the present invention.

Claims (16)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming an isolation structure and an active region in the substrate; the step of forming the isolation structure comprises:
forming a groove in the substrate;
forming a first insulating layer, wherein the first insulating layer is positioned at the bottom and the side wall of the groove;
forming a second insulating layer on the surface of the first insulating layer, wherein part of the second insulating layer is removed so that the top surface of the second insulating layer is lower than the top surface of the first insulating layer;
forming a third insulating layer partially covering the second insulating layer, wherein the first insulating layer, the second insulating layer and the third insulating layer fill the groove;
and forming a dielectric layer, wherein the dielectric layer covers the surfaces of the first insulating layer, the second insulating layer and the third insulating layer, the active area and the recess formed by removing part of the second insulating layer.
2. The method of claim 1, wherein the step of removing the portion of the second insulating layer comprises: and forming a mask layer exposing the second insulating layer on the surface of the substrate, and etching to remove part of the first insulating layer and the second insulating layer.
3. The method according to claim 2, wherein in the step of removing part of the first insulating layer and the second insulating layer, the first insulating layer and the second insulating layer are etched at the same time, and the etching rates of the first insulating layer and the second insulating layer are different.
4. The method of claim 3, wherein in the step of removing portions of the first insulating layer and the second insulating layer, an etching rate of the second insulating layer is greater than an etching rate of the first insulating layer.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein the second insulating layer is etched to a depth of 18-20nm.
6. The method of claim 2, wherein the mask layer has a thickness of 350nm to 500nm and an alignment precision of 0nm to 8nm.
7. The method of claim 1, wherein a thermal oxidation process is used to form the first insulating layer, and the first insulating layer is silicon oxide.
8. The method of claim 7, wherein the second insulating layer is formed by a deposition process, and the second insulating layer is silicon nitride.
9. The method of claim 1, wherein after the dielectric layer is formed, the dielectric layer is thinned and the surface of the active region is exposed.
10. The method of claim 1, wherein a distance between a top surface of the second insulating layer and a top surface of the first insulating layer is between 5nm and 10nm.
11. The method of claim 1, wherein the second insulating layer has a thickness of 20nm to 100nm.
12. The method of claim 11, wherein the second insulating layer has a thickness of 20nm to 50nm.
13. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, wherein an isolation structure, a groove and an active region are formed in the substrate;
the isolation structure comprises a first insulation layer, a second insulation layer, a third insulation layer and a dielectric layer, wherein the insulation layers are located at the bottom and the side wall of the groove, the second insulation layer is located on the surface of the first insulation layer, the top surface of the second insulation layer is lower than the top surface of the first insulation layer, the third insulation layer partially covers the second insulation layer, the groove is filled with the first insulation layer, the second insulation layer and the third insulation layer, and the dielectric layer covers the surfaces of the first insulation layer, the second insulation layer and the third insulation layer and the active region.
14. The semiconductor structure of claim 13, wherein a height difference from an upper surface of the second insulating layer to an upper surface of the active region is 18-20nm.
15. The semiconductor structure of claim 13, wherein the third insulating layer does not cover a top surface of the second insulating layer.
16. The semiconductor structure of claim 13, further comprising a gate structure formed over the active region.
CN202210866551.0A 2022-07-22 2022-07-22 Semiconductor structure and preparation method thereof Pending CN115223874A (en)

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