CN115188832B - High-voltage JFET device and preparation method thereof - Google Patents
High-voltage JFET device and preparation method thereof Download PDFInfo
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- CN115188832B CN115188832B CN202210808565.7A CN202210808565A CN115188832B CN 115188832 B CN115188832 B CN 115188832B CN 202210808565 A CN202210808565 A CN 202210808565A CN 115188832 B CN115188832 B CN 115188832B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 36
- 239000007924 injection Substances 0.000 claims abstract description 36
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- 210000000746 body region Anatomy 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 26
- 238000001259 photo etching Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000007943 implant Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 9
- 230000006872 improvement Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
Abstract
The invention discloses a high-voltage JFET device which comprises a first well region, a second well region and a third well region which are formed on a substrate, wherein a first voltage division ring, a second voltage division ring and a third voltage division ring are formed in the second well region and the third well region, a field oxide layer comprises a first part, a second part and a third part, the first part is connected with the first voltage division ring, the second part and the third part are connected with the second voltage division ring, the third part is connected with the third voltage division ring, polycrystalline field plates which correspond to the third voltage division ring in a one-to-one mode are formed in the third part, a body region is formed in a first injection region, a source electrode is formed in a second injection region, a grid electrode which is arranged on the third injection region and connected with the polycrystalline field plates, and a drain electrode which is far away from the grid electrode and is connected with the third part and the second well region. The polycrystalline field plate can eliminate the peak electric field on the surface of the third part corresponding to the third voltage division ring, the voltage resistance of the device is enhanced, the preparation cost is not additionally increased, and the working reliability of the high-voltage starting device is improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit design and manufacture, in particular to a high-voltage JFET device and a preparation method thereof.
Background
In the AC/DC switching power supply application field, the controller chip needs a starting circuit to provide the voltage required for starting. In the traditional application, a starting circuit is that a large resistor is connected in series from the output end of a rectifier bridge to the power supply end of a controller chip, the output end of the rectifier bridge charges a bypass capacitor of the controller chip through the large resistor, when the capacitor voltage reaches the starting voltage of the controller chip, the controller chip starts to work, a switching pulse signal is output to a switching tube, a power tube of a switch starts to switch, the output voltage or current is fed back to the port of the controller chip, the purpose of stabilizing the output voltage or current is achieved by adjusting and controlling the switching time, and after the starting is completed, energy required by the power supply end of the controller chip is mainly provided by an auxiliary winding. After the circuit of the traditional controller chip is started, the resistance of the starting circuit outside the controller still continuously consumes certain energy, so that the overall efficiency of the power management system is influenced to a certain extent.
The first method is to increase the resistance of the starting resistor and reduce the starting current of the control chip, thereby reducing the loss of the starting circuit. By adopting the first method, after the resistance value of the starting resistor is increased, the charging time of the starting capacitor is increased, so that the starting time of the system is prolonged. The second method is to add a high-voltage starting circuit by integrating a high-voltage JFET or a depletion type high-voltage MOS, and turn off the high-voltage JFET or the depletion type MOS through a control circuit after the starting is finished, so that the energy loss caused by continuous leakage of a starting resistor during normal work is prevented. The high-voltage JFET device has to be integrated in a single chip in a normal middle and low voltage control chip, and the manufacturing process of the high-voltage device is far more complicated than that of the middle and low voltage device, so that the manufacturing cost is increased.
Disclosure of Invention
In view of this, the technical problem to be solved by the present invention is how to integrate a high voltage JFET device with a withstand voltage of more than 500V in a low and medium voltage control circuit chip at the lowest cost, and the pinch-off voltage Vp of the device can be flexibly adjusted to meet the requirements of various power management start-up circuits, and the present invention is specifically implemented by the following technical solutions.
In a first aspect, the present invention provides a high voltage JFET device comprising:
a substrate of a first conductivity type;
the semiconductor device comprises a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of a second conductivity type, wherein the first well region is formed on a substrate, the second well region is formed on the substrate at intervals, and the third well region is located between the second well regions;
the first voltage division ring is formed on the upper surface of the first well region, the second voltage division ring is formed on the upper surface of the second well region, and the third voltage division ring is formed on the upper surface of the third well region;
the field oxide layers are formed in the first well region, the second well region and the third well region at intervals, each field oxide layer comprises a first portion connected with the first voltage dividing ring, a second portion connected with the second voltage dividing ring and a third portion connected with the second voltage dividing ring and the third voltage dividing ring, and polycrystalline field plates are formed on the third portions at intervals and are arranged in one-to-one correspondence with the third voltage dividing rings;
a first injection region of the first conductivity type formed over the first well region, the first voltage divider ring and connected to the first portion, a second injection region of the second conductivity type formed over the second well region and located between the first portion and the second portion, and a third injection region of the first conductivity type located between the second portion and the third portion and connected to the second well region;
a body region formed at an upper surface of the first implant region, a source electrode formed at an upper surface of the second implant region, a gate electrode formed at an upper surface of the third implant region and connected to the polycrystalline field plate, and a drain electrode remote from the gate electrode and connected to the third portion and the second well region.
As a further improvement of the above technical solution, the high-voltage JFET device further includes:
a dielectric layer formed on the first portion, the second portion, the third portion and covering the polycrystalline field plate;
and the contact holes penetrate through the dielectric layer and are respectively connected with the first injection region, the second injection region, the third injection region and the second well region.
As a further improvement of the above technical solution, the doping concentration of the first well region is greater than the doping concentration of the third well region, and the junction depths of the third voltage dividing ring, the first voltage dividing ring, and the second voltage dividing ring are sequentially increased.
In a second aspect, the invention further provides a preparation method of the high-voltage JFET device, which comprises the following specific steps:
providing a substrate of a first conductivity type;
forming first well regions of a first conductivity type on the substrate, forming second well regions of a second conductivity type on the substrate at intervals, and forming third well regions of the second conductivity type between the second well regions;
forming a first voltage division ring on the upper surface of the first well region, a second voltage division ring on the upper surface of the second well region, and a third voltage division ring on the upper surface of the third well region;
preparing field oxide layers arranged at intervals on the first well region, the second well region and the third well region, wherein the field oxide layers comprise a first part connected with the first voltage dividing ring, a second part connected with the second voltage dividing ring and a third part connected with the second voltage dividing ring and the third voltage dividing ring, and polycrystalline field plates are arranged on the third part and correspond to the third voltage dividing ring one by one;
forming a first injection region of the first conductivity type connected to the first portion over the first well region and the first voltage divider ring, a second injection region of the second conductivity type formed over the second well region and between the first portion and the second portion, and a third injection region of the first conductivity type between the second portion and the third portion and connected to the second well region;
forming a body region at an upper surface of the first implant region, a source electrode at an upper surface of the second implant region, a gate electrode at an upper surface of the third implant region connected to the poly field plate, and a drain electrode remote from the gate electrode and connected to the third portion and the second well region.
As a further improvement of the above technical solution, after the first well region is formed, the method includes:
coating photoresist on the upper surface of the first well region and coating photoresist on the substrate at intervals;
and etching and injecting second conductive type ions on the substrate by adopting a dry etching technology, removing the photoresist and performing high-temperature propulsion to form the second well region and the third well region.
As a further improvement of the above technical solution, after forming the second well region and the third well region, the method includes:
firstly, coating photoresist on the first well region, the second well region and the third well region to carry out photoetching etching on the active region, then carrying out ion injection on the voltage dividing ring, and finally forming the first voltage dividing ring, the second voltage dividing ring and the third voltage dividing ring;
and removing the photoresist to perform field oxidation to form a first portion, a second portion and a third portion.
As a further improvement of the technical scheme, the implanted impurity is BF2, the implantation dosage is between 5E13 and 2E14, the first conduction type is P type, and the second conduction type is N type.
As a further improvement of the above technical scheme, the doping concentration of the third well region is less than that of the second well region, the junction depth of the second well region is 2~4 micrometers, and the junction depth of the third well region is 1.5 to 2.8 micrometers.
As a further improvement of the technical scheme, the polycrystalline silicon is deposited on the third part and is subjected to photoetching, so that polycrystalline field plates which correspond to the third voltage dividing rings one by one are formed, and the junction depth of each polycrystalline field plate is 3~5 micrometers.
As a further improvement of the above technical solution, before forming the body region on the upper surface of the first implantation region, the method includes:
and growing the dielectric layer, performing photoetching of the contact hole, growing metal in the contact hole and on the dielectric layer, and performing photoetching on the metal to form a body region, a source electrode, a grid electrode and a drain electrode.
Compared with the prior art, the invention provides a high-voltage JFET device and a preparation method thereof, and the high-voltage JFET device has the following beneficial effects:
the first well region, the second well region and the third well region are formed on the substrate, the first well region and the second well region are different in conduction type, the second well region and the third well region are the same in conduction type, the doping concentration of the second well region is larger than that of the third well region, so that a drift region corresponding to the third well region is exhausted more easily, and the voltage resistance of the high-voltage JFET device is improved. And a first voltage division ring, a second voltage division ring and a third voltage division ring are formed in the second well region and the third well region, the field oxide layer comprises a first part, a second part and a third part, the first part is connected with the first voltage division ring, the second part and the third part are connected with the second voltage division ring, the third part is connected with the third voltage division ring, polycrystalline field plates in one-to-one correspondence with the third voltage division ring are formed in the third part, the polycrystalline field plates can eliminate peak electric fields on the surfaces of the third parts corresponding to the third voltage division ring, and meanwhile, the voltage resistance of the high-voltage JFET device is enhanced. When the voltage of the grid electrode is zero or no voltage is applied, a channel exists in a second voltage division ring below the grid electrode, and when the bias voltage exists in the drain electrode, current can be generated between the source electrode and the drain electrode. And when negative voltage is applied to the grid electrode, the PN junction formed by the second voltage division ring and the second well region is reversely biased, and the channel below the grid electrode is exhausted, so that the effective channel of the high-voltage JFET device is narrowed, and the current is reduced. When the applied voltage reaches or exceeds the pinch-off voltage Vp of the high-voltage JFET device, the channel is completely pinched off, the high-voltage JFET device is turned off, the preparation cost is not additionally increased, and the working reliability of the high-voltage starting device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a high-voltage JFET device according to an embodiment of the invention;
fig. 2 to 8 are process diagrams of a method for manufacturing a high-voltage JFET device according to an embodiment of the invention;
fig. 9 is a flow chart of a method for fabricating a high-voltage JFET device according to an embodiment of the invention;
fig. 10 is a schematic diagram of a pinch-off voltage adjustment for a high-voltage JFET device according to a first embodiment of the invention;
fig. 11 is a schematic diagram of pinch-off voltage adjustment for a high-voltage JFET device according to a second embodiment of the invention;
fig. 12 is a schematic diagram of pinch-off voltage adjustment of a high-voltage JFET device according to a third embodiment of the invention.
The main component symbols are as follows:
1-a substrate; 2-a first well region; 3-a second well region; 4-a third well region; 5-a first voltage division ring; 6-a second voltage division ring; 7-a third voltage dividing ring; 8-field oxide layer; 9-the first part; 10-a second part; 11-a third portion; 12-a polycrystalline field plate; 13-a first implanted region; 14-a second implanted region; 15-a third implanted region; 16-a body region; 17-a source electrode; 18-a gate; 19-a drain electrode; 20-a dielectric layer; 21-contact hole.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
Referring to fig. 1 and 8, fig. 8 is a cross-sectional view of fig. 1, the present invention provides a high voltage JFET device comprising:
a substrate 1 of a first conductivity type;
a first well region 2 of a first conductivity type formed on the substrate 1, a second well region 3 of a second conductivity type formed on the substrate 1 at intervals, and a third well region 4 of the second conductivity type located between the second well regions 3;
a first voltage dividing ring 5 formed on the upper surface of the first well region 2, a second voltage dividing ring 6 formed on the upper surface of the second well region 3, and a third voltage dividing ring 7 formed on the upper surface of the third well region 4;
the field oxide layers 8 are formed in the first well region 2, the second well region 3 and the third well region 4 at intervals, each field oxide layer 8 comprises a first portion 9 connected with the first voltage dividing ring 6, a second portion 10 connected with the second voltage dividing ring 6, a third portion 11 connected with the second voltage dividing ring 6 and the third voltage dividing ring 7, and polycrystalline field plates 12 are formed on the third portion 11 at intervals and are arranged in one-to-one correspondence with the third voltage dividing rings 7;
a first injection region 13 of the first conductivity type formed on said first well region 2, on said first voltage divider ring 5 and connected to said first portion 9, a second injection region 14 of the second conductivity type formed on said second well region 3 and located between said first portion 9 and said second portion 10, and a third injection region 15 of the first conductivity type located between said second portion 10 and said third portion 11 and connected to said second well region 3;
a body region 16 formed at the upper surface of the first implant region 13, a source region 17 formed at the upper surface of the second implant region 14, a gate 18 formed at the upper surface of the third implant region 15 and connected to the polycrystalline field plate 12, and a drain 19 remote from the gate 18 and connected to the third portion 11 and the second well region 3.
In this embodiment, the high-voltage JFET device further includes a dielectric layer 20 and a contact hole 21, the dielectric layer 20 is formed on the first portion 9, the second portion 10, and the third portion 11 and covers the polycrystalline field plate 12; the contact holes 21 penetrate through the dielectric layer 20 and are respectively connected with the first injection region 13, the second injection region 14, the third injection region 15 and the second well region 3. The doping concentration of the first well region 2 is greater than that of the third well region 4, and the junction depths of the third voltage division ring 7, the first voltage division ring 5 and the second voltage division ring 6 are sequentially increased. The first conductivity type is P type, the second conductivity type is N type, the substrate is lightly doped P type, the resistivity of the substrate is between 50-200ohm cm, the first well region 2 can be marked as heavily doped PW, the second well region 3 and the third well region 4 can be marked as lightly doped NW, the second well region 3 is a lightly doped drift region and used for guaranteeing the voltage withstanding performance of the high-voltage JFET device, the pinch-off voltage of the high-voltage JFET device is determined by the NW concentration and junction depth of the channel region, and the NW concentration of the channel region on the left side is flexibly adjusted through variable doping of a photoetching plate. The field oxide layer 8 is provided with a first voltage division ring 5, a second voltage division ring 6 and a third voltage division ring 7 which are used for improving the voltage resistance, a polycrystalline field plate 8 which is in one-to-one correspondence with the third voltage division ring 7 is arranged above the third part 11 of the field oxide layer 8, and the voltage resistance of the high-voltage JFET device can be further improved.
The second well region 3 connected to the first well region 2 is a channel region NW, the second well region 4 far from the first well region 2 is a drain terminal NW, and the third well region 4 is a drift region NW. The grid 18 is composed of a second voltage division ring 6, namely PF, and a third injection region 15, namely P +, when negative pressure is applied to the PF, a reverse-biased PN junction can be formed between the grid and the lower channel region NW, the high-voltage JFET device can be turned off under certain bias, a P + low-resistance contact region is arranged above the PF, the maximum size of the contact region is smaller than 1.5 micrometers, the device can be failed due to overlarge contact region, and the contact hole of the grid region is located in the grid contact region. The pinch-off voltage is the voltage applied between the gate and the source when the mos transistor starts to change from off to on, and the voltage applied between the gate and the source when the mos transistor changes from on to off (the conduction channel narrows).
It should be understood that a high-voltage JFET device with voltage resistance of more than 500V is integrated in a low-voltage controller chip, the pinch-off voltage Vp of the high-voltage JFET device can be flexibly adjusted, the requirements of various power management starting circuits are met, when the grid voltage is zero or no voltage is applied, a JFET channel exists below a grid PF, and when a drain electrode has bias voltage, current can be generated between the source electrode and the drain electrode. When negative voltage is applied to the grid electrode, the PF/NW junction is reversely biased, the channel is depleted, so that the effective channel of the JFET is narrowed, the current is reduced, when the applied voltage reaches and exceeds the JFET pinch-off voltage Vp, the channel is completely pinched off, the JFET is turned off, the pinch-off voltage Vp can be flexibly adjusted from 5 to 20V preferably, the requirement of the AC-DC starting circuit is met,
so as to improve the working stability of the high-voltage JFET device.
Referring to fig. 2 to 8 and 9, the invention further provides a method for manufacturing a high-voltage JFET device, which comprises the following specific steps:
s1: providing a substrate of a first conductivity type;
s2: forming first well regions of a first conductivity type on the substrate, forming second well regions of a second conductivity type on the substrate at intervals, and forming third well regions of the second conductivity type between the second well regions;
s3: forming a first voltage division ring on the upper surface of the first well region, a second voltage division ring on the upper surface of the second well region, and a third voltage division ring on the upper surface of the third well region;
s4: preparing field oxide layers arranged at intervals on the first well region, the second well region and the third well region, wherein the field oxide layers comprise a first part connected with the first voltage dividing ring, a second part connected with the second voltage dividing ring and a third part connected with the second voltage dividing ring and polycrystalline field plates arranged on the third part and in one-to-one correspondence with the third voltage dividing ring;
s5: forming a first injection region of the first conductivity type connected to the first portion over the first well region and the first voltage divider ring, a second injection region of the second conductivity type formed over the second well region and between the first portion and the second portion, and a third injection region of the first conductivity type between the second portion and the third portion and connected to the second well region;
s7: and a body region is formed on the upper surface of the first injection region, a source electrode is formed on the upper surface of the second injection region, a grid electrode connected with the polycrystalline field plate is formed on the upper surface of the third injection region, and a drain electrode which is far away from the grid electrode and is connected to the third part and the second well region.
Optionally, after the forming the first well region in step S2, the method includes:
s21: coating photoresist on the upper surface of the first well region and coating photoresist on the substrate at intervals;
s22: and etching and injecting second conductive type ions on the substrate by adopting a dry etching technology, removing the photoresist and performing high-temperature propulsion to form the second well region and the third well region.
Optionally, after forming the second well region and the third well region in step S2, the method includes:
firstly, coating photoresist on the first well region, the second well region and the third well region to carry out photoetching and etching of an active region, then carrying out ion implantation of the voltage divider ring, and finally forming a first voltage divider ring, a second voltage divider ring and a third voltage divider ring;
and removing the photoresist to perform field oxidation to form a first part, a second part and a third part.
Optionally, in step S4, depositing polysilicon on the third portion and performing photolithography etching on the polysilicon to form a polysilicon field plate corresponding to the third voltage divider ring one to one, where a junction depth of the polysilicon field plate is 3~5 micrometers.
Optionally, before the step S7, the method further includes:
s6: and growing a dielectric layer, performing photoetching and etching on the contact hole, growing metal in the contact hole and on the dielectric layer, and performing photoetching and etching on the metal to form a body region, a source electrode, a grid electrode and a drain electrode.
In this embodiment, the first conductive type is P-type, and the second conductive type is N-type. First, as shown in FIG. 2, FIG. 3 and FIG. 4, a P-type substrate is providedAnd photoetching injection of the first well region marked as PW is carried out, the doping concentration of the P-type substrate is slightly lower than that of the original process, and the resistivity of the P-type substrate is 50-100ohm cm, so that a wider depletion region can be obtained, and higher withstand voltage of the JFET device can be obtained. Then, carrying out NW photoetching implantation on the surface of the substrate, wherein the NW dose and energy are consistent with those of a traditional medium-low voltage device, and the implantation ion dose is 3E12-1E 13/cm 2 In the NW doping design, the NW in the middle part is the pattern of the third well region, the junction depth of the NW window is between 0.5 to 1.0 micron, and the area percentage of the open window is about 30%, so that the actual dosage of the NW impurity in the area can be controlled to be about 30% of the standard NW dosage. And then removing the photoresist, advancing the well region at a high temperature, wherein the advancing temperature and the advancing time are consistent with those of a traditional medium-low pressure process, the junction depth of the conventional NW is 1~4 micrometers after the advancing is finished, and the actual junction depth of the middle variable-doping low-resistance drift region is about 1.5 to 2.8 micrometers because the impurity concentration is lower, so that the drift region is more easily consumed, and the voltage resistance of the device can be improved.
And thirdly, as shown in fig. 5 and fig. 6, performing photolithography etching on the active region, wherein the junction depth of the gate contact region is 0.8 to 1.5 micrometers, which is too small, so that the gate contact region is eroded during subsequent field oxidation, and finally, the surface oxide layer is too thick, and subsequent P + impurities cannot be injected, so that effective gate contact cannot be formed. If the size is too large, the PF lateral diffusion on both sides of the PF is not connected, and the withstand voltage of the device is greatly reduced. And then performing PF field implantation, wherein the implantation dosage is slightly higher than that of the conventional PF field implantation, preferably between 5E13 and 2E14, and BF2 is implanted as an impurity, and the implantation dosage can influence the junction depth of PF to a certain extent and the pinch-off voltage Vp of the JFET device. It should be noted that the PF injection region mainly includes a first voltage divider ring, a second voltage divider ring, and a third voltage divider ring, and the first voltage divider ring is a PW region that is the same as the conventional low-voltage process, and can prevent electric leakage and parasitic effect between devices; the second voltage division ring is PF on two sides of the grid of the channel region, and the grid is finally formed; the third voltage division ring is a PF field ring above the drift region NW, the withstand voltage of the JFET device can be improved, the optimal size of the field ring is 3-5um, the distance between the field rings is 5-10um, and the withstand voltage of the device can be optimal due to reasonable field ring arrangement.
Finally, as shown in fig. 7 and 8, the photoresist is removed, the field region is oxidized, the PF impurities are simultaneously activated and diffused after oxidation, wherein the PF impurities on both sides of the gate contact region are diffused and then connected together to form a whole, if the size of the gate contact region is too large, the PF on both sides cannot be folded, and the withstand voltage of the device is directly negatively affected. And then, manufacturing gate oxide and growing polycrystal by the conventional process, photoetching and etching the polysilicon, forming a gate field plate by the polycrystal above the right of the gate PF and short-circuiting the gate, wherein the polysilicon above the right of the PF field ring is a floating field ring which is in one-to-one correspondence with the PF ring, and the optimal junction depth is 3~5 microns. The subsequent process is the same as the traditional process, the dielectric layer is grown and the contact hole is etched by photoetching, the metal is grown again and the metal is etched by photoetching, and the integrated high-voltage JFET device is manufactured. The photoetching layer and the process flow adopted by the invention are completely the same as those of the existing middle-low voltage control chip, so that compared with the conventional flow, only the adjustment of the photoetching plate design is carried out, and the process cost is not increased at all. The high-voltage JFET device integrated by the high-voltage JFET device has withstand voltage of over 500V, and the pinch-off voltage Vp of the high-voltage JFET device can be flexibly adjusted from 5V to 20V, so that the requirement of an AC-DC starting circuit is met.
In another embodiment, as shown in fig. 10, different NW lithographic areas determine the actual impurity dose in the channel region, as shown in fig. 11, different impurity doses affect the junction depth and concentration of the channel region NW, and as shown in fig. 12, the effective channel width and concentration directly determine the magnitude of Vp after the gate fabrication is completed. In the HVCMOS process, a variable channel and a voltage division ring for reducing a surface electric field are provided for the JFET device by the special design of NW variable doping and PF photomask, the withstand voltage of the JFET device can be 300-700V, namely, the PF layer in the original CMOS process is used as the voltage division ring, the surface electric field of a drift region of the JFET device is reduced, and any photomask is not added, so that the requirement of an AC-DC starting circuit can be met. The JFET device is convenient to understand, the concentration of a drift region of the JFET device is reduced by adopting an NW variable doping mode, the withstand voltage of the JFET device is improved, and meanwhile, the junction depth and the concentration of a JFET channel region are adjusted by adopting the NW variable doping mode, so that the pinch-off voltage of the JFET device is adjusted. Compared with the traditional medium and low voltage CMOS process, the ultra-high voltage JFET device is manufactured on the premise of not adding any photomask layer or increasing the process cost, and the high voltage starting requirement of the AC-DC current is met.
The invention provides a high-voltage JFET device and a preparation method thereof.A first well region, a second well region and a third well region are formed on a substrate, the first well region and the second well region have different conduction types, the second well region and the third well region have the same conduction type, and the doping concentration of the second well region is greater than that of the third well region, so that a drift region corresponding to the third well region is more easily exhausted, and the voltage resistance of the high-voltage JFET device is improved. Form first divider ring, second divider ring and third divider ring in second well region, third well region, the field oxide layer includes the first portion, the second portion and third portion, first divider ring is connected to the first portion, the second divider ring is connected to the second portion and third portion, the third divider ring is connected to the third portion, form the polycrystal field plate with third divider ring one-to-one in the third portion, the peak electric field on the surface of the third portion that third divider ring corresponds can be eliminated to the polycrystal field plate, the withstand voltage ability of high-voltage JFET device has been strengthened simultaneously. When the voltage of the grid electrode is zero or no voltage is applied, a channel exists in a second voltage division ring below the grid electrode, and when the bias voltage exists in the drain electrode, current can be generated between the source electrode and the drain electrode. And when negative voltage is applied to the grid electrode, the PN junction formed by the second voltage division ring and the second well region is reversely biased, and the channel below the grid electrode is exhausted, so that the effective channel of the high-voltage JFET device is narrowed, and the current is reduced. When the applied voltage reaches or exceeds the pinch-off voltage Vp of the high-voltage JFET device, the channel is completely pinched off, the high-voltage JFET device is turned off, the preparation cost is not additionally increased, and the working reliability of the high-voltage starting device is improved.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (2)
1. A high-voltage JFET device, comprising:
a substrate of a first conductivity type;
the semiconductor device comprises a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of a second conductivity type, wherein the first well region is formed on a substrate, the second well region is formed on the substrate at intervals, and the third well region is located between the second well regions;
the first voltage division ring is formed on the upper surface of the first well region, the second voltage division ring is formed on the upper surface of the second well region, and the third voltage division ring is formed on the upper surface of the third well region;
the field oxide layers are formed on the first well region, the second well region and the third well region at intervals, each field oxide layer comprises a first portion connected with the first voltage dividing ring, a second portion connected with the second voltage dividing ring and a third portion connected with the second voltage dividing ring and the third voltage dividing ring, and the field oxide layers are formed on the third portions at intervals and are polycrystalline field plates arranged in one-to-one correspondence with the third voltage dividing rings;
a first injection region of the first conductivity type formed over the first well region and the first voltage divider ring and connected to the first portion, a second injection region of the second conductivity type formed over the second well region and located between the first portion and the second portion, and a third injection region of the first conductivity type located between the second portion and the third portion and connected to the second well region;
a body region formed at an upper surface of the first implant region, a source region formed at an upper surface of the second implant region, a gate formed at an upper surface of the third implant region and connected to the poly field plate, and a drain remote from the gate and connected to the third portion and the second well region;
a dielectric layer formed on the first portion, the second portion, the third portion and covering the polycrystalline field plate;
the contact hole penetrates through the dielectric layer and is respectively connected with the first injection region, the second injection region, the third injection region and the second well region;
the doping concentration of the first well region is greater than that of the third well region, the junction depths of the third voltage division ring, the first voltage division ring and the second voltage division ring are sequentially increased, and the polycrystalline field plate is made of polycrystalline silicon;
the doping concentration of the third well region is smaller than that of the second well region, the junction depth of the second well region is 2-4 micrometers, the junction depth of the third well region is 1.5-2.8 micrometers, and the first voltage division ring, the second voltage division ring and the third voltage division ring are injection regions of a first conduction type.
2. A preparation method of a high-voltage JFET device, wherein the preparation method is used for preparing the high-voltage JFET device according to claim 1, and the preparation method comprises the following specific steps:
providing a substrate of a first conductivity type;
forming first well regions of a first conductivity type on the substrate, forming second well regions of a second conductivity type on the substrate at intervals, and forming third well regions of the second conductivity type between the second well regions;
a first voltage division ring is formed on the upper surface of the first well region, a second voltage division ring is formed on the upper surface of the second well region, and a third voltage division ring is formed on the upper surface of the third well region;
preparing field oxide layers arranged at intervals on the first well region, the second well region and the third well region, wherein the field oxide layers comprise a first part connected with the first voltage dividing ring, a second part connected with the second voltage dividing ring and a third part connected with the second voltage dividing ring and polycrystalline field plates arranged on the third part and in one-to-one correspondence with the third voltage dividing ring;
forming a first implanted region of the first conductivity type connected to the first portion over the first well region and the first voltage divider ring, a second implanted region of the second conductivity type formed over the second well region and between the first portion and the second portion, and a third implanted region of the first conductivity type formed between the second portion and the third portion and connected to the second well region;
forming a body region at an upper surface of the first implant region, a source electrode at an upper surface of the second implant region, a gate electrode at an upper surface of the third implant region connected to the polycrystalline field plate, and a drain electrode remote from the gate electrode and connected to the third portion and the second well region;
wherein, after forming the first well region, include:
coating photoresist on the upper surface of the first well region and coating photoresist on the substrate at intervals;
etching and injecting second conductive type ions on the substrate by adopting a dry etching technology, removing photoresist and performing high-temperature propulsion to form the second well region and the third well region;
wherein, after forming the second well region and the third well region, include:
firstly, coating photoresist on the first well region, the second well region and the third well region to carry out photoetching etching on the active region, then carrying out ion injection on the voltage dividing ring, and finally forming the first voltage dividing ring, the second voltage dividing ring and the third voltage dividing ring;
removing the photoresist and carrying out field oxidation to form a first part, a second part and a third part;
depositing polycrystalline silicon on the third part, and performing photoetching of the polycrystalline silicon to form polycrystalline field plates corresponding to the third voltage dividing rings one by one, wherein the junction depth of each polycrystalline field plate is 3-5 micrometers;
wherein, before forming the body region on the upper surface of the first implantation region, the method comprises:
and growing the dielectric layer, performing photoetching of the contact hole, growing metal in the contact hole and on the dielectric layer, and performing photoetching on the metal to form a body region, a source electrode, a grid electrode and a drain electrode.
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| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
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| CN104518034B (en) * | 2014-06-17 | 2020-11-24 | 上海华虹宏力半导体制造有限公司 | JFET device and manufacturing method thereof |
| US9460926B2 (en) * | 2014-06-30 | 2016-10-04 | Alpha And Omega Semiconductor Incorporated | Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions |
| CN108305903B (en) * | 2018-02-27 | 2020-11-24 | 上海华虹宏力半导体制造有限公司 | JFET and manufacturing method thereof |
| CN109860277A (en) * | 2019-01-08 | 2019-06-07 | 福州臻美网络科技有限公司 | A kind of JFET device and preparation method thereof |
| CN112151620B (en) * | 2020-10-27 | 2022-07-19 | 杰华特微电子股份有限公司 | Junction field effect transistor with ESD protection structure |
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| CN102867843A (en) * | 2008-02-27 | 2013-01-09 | 先进模拟科技公司 | Isolated transistors and diodes and isolation and termination structures for semiconductor die |
| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
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