CN103137622A - Semiconductor device for high-voltage integrated circuit and preparation method thereof - Google Patents

Semiconductor device for high-voltage integrated circuit and preparation method thereof Download PDF

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CN103137622A
CN103137622A CN2011103843424A CN201110384342A CN103137622A CN 103137622 A CN103137622 A CN 103137622A CN 2011103843424 A CN2011103843424 A CN 2011103843424A CN 201110384342 A CN201110384342 A CN 201110384342A CN 103137622 A CN103137622 A CN 103137622A
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CN103137622B (en
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潘光燃
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Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Abstract

本发明实施例涉及半导体技术领域，特别涉及一种用于高压集成电路的半导体器件，包括：位于衬底内的P阱区，P阱区包括低压P阱区和高压P阱区；位于P阱区上表面的局部厚氧化层；位于P阱区内的P型掺杂区，P型掺杂区是通过一次掩膜曝光，向低压P阱区及高压P阱区的场区上表面内进行P场注入，以及向低压P阱区的有源区再进行防穿通注入形成；位于P阱区有源区上的栅氧化层；位于所述栅氧化层上表面的多晶硅栅；位于所述有源区和多晶硅层上的介质层和接触孔；位于所述介质层上表面和接触孔内的金属层。本发明实施例提供的半导体器件及其制造方法，降低了制造成本及传统工艺的复杂操作，并且也达到了保证器件和集成电路的性能的效果。

Figure 201110384342

Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device for high-voltage integrated circuits, including: a P well region located in a substrate, and the P well region includes a low-voltage P well region and a high-voltage P well region; The local thick oxide layer on the upper surface of the region; the P-type doped region located in the P-well region. The P-type doped region is exposed through a mask to the upper surface of the field region of the low-voltage P-well region and the high-voltage P-well region. P field implantation, and anti-puncture implantation to the active region of the low-voltage P well region; the gate oxide layer on the active region of the P well region; the polysilicon gate on the upper surface of the gate oxide layer; A dielectric layer and a contact hole on the source region and the polysilicon layer; a metal layer located on the upper surface of the dielectric layer and in the contact hole. The semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention reduce the manufacturing cost and the complex operation of the traditional process, and also achieve the effect of ensuring the performance of the device and the integrated circuit.

Figure 201110384342

Description

A kind of semiconductor device and manufacture method thereof for high voltage integrated circuit
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly a kind of semiconductor device and manufacture method thereof for high voltage integrated circuit.
Background technology
At present, in micron order and submicron order integrated circuit fabrication process, generally all adopt selective oxidation (LOCOS) isolation technology, due to the solid solubility of boron ion in silicon less than it solid solubility in silicon dioxide, therefore (these thick oxide layers generally all are referred to as field oxide to generate thick oxide layer in selective oxidation, be Fox) process in, the fractional condensation in the thick oxide layer (being silicon dioxide) of the boron ion of silicon face causes the boron ion concentration of silicon face to reduce.
N trap and P trap are to make the essential structure of CMOS integrated circuit, and dopant wherein is respectively phosphonium ion and boron ion.When the oxide layer of location oxidation of silicon process fabricating yard, the boron ion concentration on surface, P trap place can reduce, and this causes the isolation effect variation of P trap place, the performance of integrated circuit so step-down.In order to improve the isolation effect of P trap place, common way is before the growth field oxide or a photoetching (being referred to as P field photoetching) is carried out in growth after field oxide and the boron Implantation (is referred to as P field injection, being called for short PF injects), thus the boron ion concentration on surface, P trap place increased.
For preventing the break-through electric leakage that low pressure NMOS pipe short-channel effect causes or puncturing, need to carry out the boron Implantation one time at P trap active area, usually be referred to as anti-break-through and inject (being called for short APT injects); The channel length of high pressure NMOS pipe is larger, does not generally need APT to inject at its active area.
As shown in Fig. 1 a～Fig. 1 c, the mask layout profile of prior art high voltage integrated circuit P field photoetching, as shown in Figure 1, generate P well region, grow thick oxide layer on the P well region on substrate 1, zone with thick oxide layer is place 4, comprise high pressure P well region 2 and low pressure P well region 3, after exposing, develop by mask plate, be retained in the photoresist 5 of high pressure P well region 2, low pressure P well region 3 is carried out P field injection 6 and APT injection 7, then remove photoresist 5; As shown in Fig. 1 b, then by a mask plates, carry out single exposure, development, and be retained in the photoresist 5 of low pressure P well region 3, high pressure P well region 2 is carried out P field injection for the second time 6, then remove photoresist as shown in Fig. 1 c.
All inject the PF doping below the P type field doped structure that adopts that above-mentioned conventional method forms, the thick oxide layer of all P traps, reached the insulation request of P trap place; The P trap active area of low pressure NMOS has injected the APT doping, and the P trap active area of high pressure NMOS does not inject the APT doping, has satisfied simultaneously the requirement on devices of low pressure NMOS and high pressure NMOS.
This classical production process, needing Twi-lithography (low pressure P field photoetching, high pressure P field photoetching) and three secondary ions to inject comprises: low pressure PF injects, APT injects, high pressure P F injects, just can complete the P field doping in high voltage integrated circuit, the technique more complicated, manufacturing cost is higher.
Summary of the invention
A kind of semiconductor device and manufacture method thereof for high voltage integrated circuit that the embodiment of the present invention provides have reduced the complex operations of manufacturing cost and traditional handicraft, and have also reached the effect that guarantees the performance of device and integrated circuit.
The embodiment of the present invention provides a kind of semiconductor device for high voltage integrated circuit, comprising:
Be positioned at the P well region of substrate, described P well region comprises low pressure P well region and high pressure P well region;
Be positioned at the local thick oxide layer of described P well region upper surface;
Be positioned at the P type doped region of P well region, described P type doped region is by a mask exposure, carries out P field injection in the place upper surface of low pressure P well region and described high pressure P well region, and prevents that to the active area of described low pressure P well region the break-through injection forms again;
Be positioned at the gate oxide on described P well region active area;
Be positioned at the polysilicon gate of described gate oxide upper surface;
Be positioned at dielectric layer and contact hole on described active area and polysilicon layer;
Be positioned at the metal level of described dielectric layer upper surface and contact hole.
A kind of manufacturing method of semiconductor device for high voltage integrated circuit also is provided, comprises:
Implanted dopant forms the P well region in the substrate, and described P well region comprises low pressure P well region and high pressure P well region;
Local growth thick oxide layer at described P well region upper surface;
Make P type doped region in the P well region, described P type doped region is by a mask exposure, carries out P field injection in the place upper surface of low pressure P well region and described high pressure P well region, and prevents that at the active area of described low pressure P well region the break-through injection forms again;
The gate oxide of growing on described P well region active area;
At described gate oxide upper surface growing polycrystalline silicon layer, form polysilicon gate by mask exposure, an etching;
Described active area and and polysilicon layer on the somatomedin layer, form contact hole by mask exposure, etching;
Growing metal layer in described dielectric layer upper surface and contact hole forms metal connecting line by mask exposure, an etching.
The present invention has the following advantages with comparing of prior art:
The invention provides a kind ofly for the semiconductor device of high voltage integrated circuit and the embodiment of manufacture method, implanted dopant in the substrate forms the P well region, and described P well region comprises low pressure P well region and high pressure P well region; Different according to demand, for preventing low pressure metal-oxide-semiconductor short-channel effect, active area at low pressure P well region carries out the APT injection, but can not carry out APT at the high pressure P well region injects, otherwise the threshold voltage of high-voltage MOS pipe can become greatly, the combination property of energising ability and device is descended, therefore, the present invention has reduced the complex operations of manufacturing cost and traditional handicraft, and has also reached the effect that guarantees the performance of device and integrated circuit.
Description of drawings
Fig. 1 a～Fig. 1 c is the mask layout profile of prior art high voltage integrated circuit P field photoetching;
Fig. 2 is the manufacture method schematic flow sheet of semiconductor device in the embodiment of the present invention;
Fig. 3 a-Fig. 3 j is the manufacture method schematic flow sheet of semiconductor device in the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description, the embodiment of the present invention is described in further detail.
The embodiment of the present invention provides a kind of semiconductor device for high voltage integrated circuit, comprising:
Be positioned at the P well region of substrate, described P well region comprises low pressure P well region and high pressure P well region;
Be positioned at the local thick oxide layer of described P well region upper surface;
Be positioned at the P type doped region of P well region, described P type doped region is by a mask exposure, carries out P field injection in the place upper surface of low pressure P well region and described high pressure P well region, and prevents that at the active area of described low pressure P well region the break-through injection forms again;
Be positioned at the gate oxide on described P well region active area;
Be positioned at the polysilicon gate of described gate oxide upper surface;
Be positioned at dielectric layer and contact hole on described active area and polysilicon layer;
Be positioned at the metal level of described dielectric layer upper surface and contact hole.
The described P type doped region that forms does not comprise: at the on-site of described high pressure P well region, and the active area boundary length of the described high pressure P well region place of distance and described high pressure P well region is the fringe region of 0.5～2.0 micron.
The impurity that described P field is injected is the boron ion, and its Implantation Energy is 150～250 kiloelectron-volts, and its implantation dosage is 6E12～12E12 atom/square centimeter.
The impurity that described anti-break-through is injected is the boron ion, and its Implantation Energy is 50～100 kiloelectron-volts, and its implantation dosage is 2E12～4E12 atom/square centimeter.
The embodiment of the present invention also provides a kind of manufacturing method of semiconductor device for high voltage integrated circuit, comprising:
Implanted dopant forms the P well region in the substrate, and described P well region comprises low pressure P well region and high pressure P well region;
Local growth thick oxide layer at described P well region upper surface;
Make P type doped region in the P well region, described P type doped region is by a mask exposure, carries out P field injection in the place upper surface of low pressure P well region and described high pressure P well region, and prevents that at the active area of described low pressure P well region the break-through injection forms again;
The gate oxide of growing on described P well region active area;
At described gate oxide upper surface growing polycrystalline silicon layer, form polysilicon gate by mask exposure, an etching;
Described active area and and polysilicon layer on the somatomedin layer, form contact hole by mask exposure, etching;
Growing metal layer in described dielectric layer upper surface and contact hole forms metal connecting line by mask exposure, an etching.
The described P type doped region of making in the P well region specifically also comprises:
At the on-site of described high pressure P well region, and the active area of distance described high pressure P well region place and described high pressure P well region is not carry out the P field in the fringe region of 0.5～2.0 micron inject and prevent the break-through injection apart from the length on border.
At the described P type doped region of making in the P well region, specifically also comprise:
The photoetching of P field is specially: scribble photoresist on P well region upper surface, the mask plate of use moulding after overexposure, developing, carries out a P field injection in active area and the zone described fringe region except the high pressure P well region.
Describedly also comprise after a P field injects carrying out except the active area of high pressure P well region and the zone described fringe region:
The break-through injection is once prevented in zone described active area except the high pressure P well region and described fringe region, then removes photoresist, forms P type doped region.
The impurity that described P field is injected is the boron ion, and its Implantation Energy is 150～250 kiloelectron-volts, and its implantation dosage is 6E12～12E12 atom/square centimeter.
The impurity that described anti-break-through is injected is the boron ion, and its Implantation Energy is 50～100 kiloelectron-volts, and its implantation dosage is 2E12～4E12 atom/square centimeter.
Describe below by the manufacture method of specific embodiment to semiconductor device provided by the invention, as shown in Figure 2, comprise the following steps:
Step 201: implanted dopant forms the P well region in the substrate, and described P well region comprises low pressure P well region and high pressure P well region;
Step 202: at the local growth thick oxide layer of described P well region upper surface;
Step 203: the P type doped region of making in the P well region, described P type doped region is by a mask exposure, carry out P field injection in the place upper surface of low pressure P well region and described high pressure P well region, and prevent again that at the active area of described low pressure P well region the break-through injection forms;
Step 204: the gate oxide of growing on described P well region active area;
Step 205: at described gate oxide upper surface growing polycrystalline silicon layer, form polysilicon gate by mask exposure, an etching;
Step 206: described active area and and polysilicon layer on the somatomedin layer, form contact hole by mask exposure, etching;
Step 207: growing metal layer in described dielectric layer upper surface and contact hole forms metal connecting line by mask exposure, an etching.
Referring to Fig. 3 a-Fig. 3 j, the method that the embodiment of the present invention is provided is described in detail, and as shown in Fig. 3 a and Fig. 3 b, makes the P well region on substrate 1, includes low pressure P well region 3 and high pressure P well region 2, carries out an oxidation on the surface of P well region, generates field oxide 4.Be the place to be active area less than what be capped by what field oxide covered; When the oxide layer 4 of location oxidation of silicon process fabricating yard, the boron ion concentration on surface, P trap place can reduce, and this causes the isolation effect variation of P trap place, and then makes performance so the step-down of integrated circuit.In order to improve the isolation effect of P trap place, common way is to carry out a photoetching before the growth field oxide or after the growth field oxide, be P field photoetching, and the boron Implantation is that (being called for short PF injects) injected in the P field, thereby increases the boron ion concentration on surface, P trap place.
As shown in Fig. 3 c～Fig. 3 f, the flow chart that injects for carry out P field injection and APT by the mask plate photoetching, as shown in Fig. 3 c, after gluing, exposure, development, only keep active area 21 and the active area of high pressure P well region and the photoresist of place boundary line fringe region 22 of high pressure P well region; Fringe region 22 is the zone of 0.5～2.0 micron for the length of the place boundary line of the active area of the on-site distance high-voltage P well region of high pressure P well region and high pressure P well region, as shown in Fig. 3 d, carry out a P field injection 6 in the place (removing fringe region 22) of low pressure P well region and high pressure P well region, described P field implanted dopant is the boron ion, its Implantation Energy is 150～250 kiloelectron-volts, and its implantation dosage is 6E12～12E12 atom/square centimeter; As shown in Fig. 3 e, then carry out an APT and inject 7 formation P type doped regions, described anti-break-through implanted dopant is the boron ion, and its Implantation Energy is 50～100 kiloelectron-volts, and its implantation dosage is 2E12～4E12 atom/square centimeter; Employing sulfuric acid etc. is removed the photoresist 5 of above-mentioned coating, as shown in Fig. 3 f.
As shown in Fig. 3 g, after removing photoresist 5, at the active area upper surface growth gate oxide 8 of P well region.
As shown in Fig. 3 h, growing polycrystalline silicon layer 9 on gate oxide 8.Utilize the polysilicon reticle, produce the polysilicon strip by steps such as gluing, exposure, development, etchings regional.Wherein, can utilize chlorine atom and silicon generation chemical reaction in chlorine to generate volatilizable compound during etching, then adopt dry method to add wet method and remove above-mentioned photoresist.
As shown in Fig. 3 i, described active area and and polysilicon layer on somatomedin layer 10, utilize the contact hole reticle, produce contact hole 11 by steps such as gluing, exposure, development, etchings, then adopt dry method to add wet method and remove above-mentioned photoresist.
As shown in Fig. 3 j, growing metal layer in dielectric layer 10 upper surfaces and contact hole utilizes the metal level reticle, produces metal connecting line 12 by steps such as gluing, exposure, development, etchings, then adopts dry method to add wet method and remove above-mentioned photoresist.
Except above processing step, the making in source, drain region, the processing steps such as passivation layer can carry out according to the known standard technology in this area, and are no longer burdensome at this.
As shown in above-mentioned Fig. 3 c～Fig. 3 f, also can carry out mask lithography after P well region 1 grow thick oxide layer 4, the B Implanted ion also can carry out before grow thick oxide layer 4, and its technique is same as described above.
By above-mentioned description as can be known, semiconductor device that is used for high voltage integrated circuit that the use embodiment of the present invention provides and preparation method thereof, overcome that cost in the prior art is high, the shortcoming of complex process, utilize a P field photoetching to expose in the place of low pressure P well region and high pressure P well region, and carry out twice injection, be respectively that P field injection and APT inject, reached and both saved cost, satisfied again performance and the device parameters beneficial effect of circuit.
Although described the preferred embodiments of the present invention, in a single day those skilled in the art get the basic creative concept of cicada, can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.

Claims (10)

1.一种用于高压集成电路的半导体器件，其特征在于，包括：1. A semiconductor device for high-voltage integrated circuits, characterized in that, comprising: 位于衬底内的P阱区，所述P阱区包括低压P阱区和高压P阱区；A P-well region located in the substrate, the P-well region includes a low-voltage P-well region and a high-voltage P-well region; 位于所述P阱区上表面的局部厚氧化层；A local thick oxide layer located on the upper surface of the P well region; 位于P阱区内的P型掺杂区，所述P型掺杂区是通过一次掩膜曝光，向低压P阱区及所述高压P阱区的场区上表面内进行P场注入，以及向所述低压P阱区的有源区再进行防穿通注入形成；The P-type doped region located in the P-well region, the P-type doped region is exposed through a mask, and the P-field implantation is performed into the upper surface of the field region of the low-voltage P-well region and the high-voltage P-well region, and Perform anti-puncture implantation to the active region of the low-voltage P-well region; 位于所述P阱区有源区上的栅氧化层；a gate oxide layer located on the active region of the P well region; 位于所述栅氧化层上表面的多晶硅栅；a polysilicon gate located on the upper surface of the gate oxide layer; 位于所述有源区和多晶硅层上的介质层和接触孔；a dielectric layer and a contact hole located on the active region and the polysilicon layer; 位于所述介质层上表面和接触孔内的金属层。The metal layer located on the upper surface of the dielectric layer and in the contact hole. 2.如权利要求1所述用于高压集成电路的半导体器件，其特征在于，形成的所述P型掺杂区不包括：在所述高压P阱区的场区内，并且距离所述高压P阱区场区与所述高压P阱区的有源区边界长度为0.5～2.0微米的边缘区域。2. The semiconductor device used for high-voltage integrated circuits as claimed in claim 1, wherein the P-type doped region formed does not include: in the field region of the high-voltage P well region, and at a distance from the high-voltage The boundary between the field region of the P-well region and the active region of the high-voltage P-well region is an edge region with a length of 0.5-2.0 microns. 3.如权利要求2所述用于高压集成电路的半导体器件，其特征在于，所述P场注入的杂质为硼离子，其注入能量为150～250千电子伏，其注入剂量为6E12～12E12原子/平方厘米。3. The semiconductor device used for high-voltage integrated circuits as claimed in claim 2, wherein the impurities implanted in the P field are boron ions, the implantation energy is 150-250 keV, and the implantation dose is 6E12-12E12 atoms/square centimeter. 4.如权利要求3所述用于高压集成电路的半导体器件，其特征在于，所述防穿通注入的杂质为硼离子，其注入能量为50～100千电子伏，其注入剂量为2E12～4E12原子/平方厘米。4. The semiconductor device for high-voltage integrated circuits as claimed in claim 3, wherein the impurity for preventing punch-through implantation is boron ions, the implantation energy is 50-100 keV, and the implantation dose is 2E12-4E12 atoms/square centimeter. 5.一种用于高压集成电路的半导体器件制作方法，其特征在于，包括：5. A semiconductor device manufacturing method for high-voltage integrated circuits, characterized in that, comprising: 向衬底内注入杂质形成P阱区，所述P阱区包括低压P阱区和高压P阱区；Implanting impurities into the substrate to form a P-well region, the P-well region including a low-voltage P-well region and a high-voltage P-well region; 在所述P阱区上表面的局部生长厚氧化层；locally growing a thick oxide layer on the upper surface of the P-well region; 在P阱区内制作P型掺杂区，所述P型掺杂区是通过一次掩膜曝光，在低压P阱区及所述高压P阱区的场区上表面内进行P场注入，以及在所述低压P阱区的有源区再进行防穿通注入形成；Making a P-type doped region in the P-well region, the P-type doped region is exposed through a mask, and performing P field implantation in the low-voltage P-well region and the upper surface of the field region of the high-voltage P-well region, and performing anti-puncture implantation in the active region of the low-voltage P-well region; 在所述P阱区有源区上生长栅氧化层；growing a gate oxide layer on the active region of the P well region; 在所述栅氧化层上表面生长多晶硅层，通过一次掩膜曝光、刻蚀形成多晶硅栅；growing a polysilicon layer on the surface of the gate oxide layer, and forming a polysilicon gate through one mask exposure and etching; 在所述有源区和和多晶硅层上生长介质层，通过一次掩膜曝光、刻蚀形成接触孔；growing a dielectric layer on the active region and the polysilicon layer, and forming a contact hole through mask exposure and etching; 在所述介质层上表面和接触孔内生长金属层，通过一次掩膜曝光、刻蚀形成金属连线。A metal layer is grown on the upper surface of the dielectric layer and in the contact hole, and a metal connection is formed through exposure and etching of a mask. 6.如权利要求5所述的制作方法，其特征在于，所述在P阱区内制作P型掺杂区，具体还包括：6. The manufacturing method according to claim 5, wherein said manufacturing a P-type doped region in the P well region specifically further comprises: 在所述高压P阱区的场区内，并且距离所述高压P阱区场区与所述高压P阱区的有源区距离边界的长度为0.5～2.0微米的边缘区域内不进行P场注入和防穿通注入。In the field region of the high-voltage P well region, and the distance from the field region of the high-voltage P well region and the active region of the high-voltage P well region is 0.5 to 2.0 microns in the edge region. Injection and anti-puncture injection. 7.如权利要求6所述的制作方法，其特征在于，所述在P阱区内制作P型掺杂区，具体还包括：7. The manufacturing method according to claim 6, wherein said manufacturing a P-type doped region in the P well region specifically further comprises: P场光刻，具体为：在P阱区上表面上涂有光刻胶，使用制作成型的掩膜版，经过曝光、显影后，在除高压P阱区的有源区及所述边缘区域之外的区域进行一次P场注入。P-field lithography, specifically: coating photoresist on the upper surface of the P-well region, using a fabricated mask, after exposure and development, except for the active region of the high-voltage P-well region and the edge region A P-field implantation is performed in the region. 8.如权利要求7所述的制作方法，其特征在于，所述在除高压P阱区的有源区及所述边缘区域之外的区域进行一次P场注入之后，还包括：8. The manufacturing method according to claim 7, characterized in that, after performing a P field implantation in regions other than the active region of the high-voltage P well region and the edge region, further comprising: 在所述除高压P阱区的有源区及所述边缘区域之外的区域进行一次防穿通注入，再除去光刻胶，形成出P型掺杂区。An anti-piercing injection is performed in the region except the active region of the high-voltage P well region and the edge region, and then the photoresist is removed to form a P-type doped region. 9.如权利要求7所述的制作方法，其特征在于，所述P场注入杂质为硼离子，其注入能量为150～250千电子伏，其注入剂量为6E12～12E12原子/平方厘米。9. The manufacturing method according to claim 7, wherein the impurity implanted in the P field is boron ions, the implantation energy is 150-250 keV, and the implantation dose is 6E12-12E12 atoms/cm2. 10.如权利要求8所述的制作方法，其特征在于，所述防穿通注入杂质为硼离子，其注入能量为50～100千电子伏，其注入剂量为2E12～4E12原子/平方厘米。10 . The manufacturing method according to claim 8 , wherein the anti-puncture implantation impurity is boron ions, the implantation energy is 50-100 keV, and the implantation dose is 2E12-4E12 atoms/cm2.
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