CN110021561B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN110021561B CN110021561B CN201811617682.5A CN201811617682A CN110021561B CN 110021561 B CN110021561 B CN 110021561B CN 201811617682 A CN201811617682 A CN 201811617682A CN 110021561 B CN110021561 B CN 110021561B
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for forming a semiconductor device. First, a substrate is provided, and a first well and a second well with opposite conductive types are formed in a high potential predetermined region of the substrate. Then, forming a high-potential region oxide layer on the substrate of the high-potential predetermined region, then forming a third well and a fourth well with opposite conductivity types in the low-potential predetermined region of the substrate, and then forming a low-potential region oxide layer on the substrate of the low-potential predetermined region.
Description
Technical Field
The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a well of a high potential region and a well of a low potential region of a semiconductor device.
Background
In the fabrication of semiconductor devices, it is sometimes necessary to integrate the processing of high voltage integrated circuit devices into the processing of low voltage integrated circuit devices so that the high voltage integrated circuit devices and the low voltage integrated circuit devices can be integrated into the semiconductor device at the same time.
However, when the process of the high voltage integrated circuit device is integrated into the process of the low voltage integrated circuit device, the formed low voltage integrated circuit device may be affected by the process of the high voltage integrated circuit device to reduce the reliability thereof.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor device. The method for forming the semiconductor device comprises the step of providing a substrate. The substrate includes a low potential predetermined region and a high potential predetermined region. The method also includes forming a first well and a second well in the substrate in the high-potential predefined region. The first well and the second well have opposite conductivity types. The method also includes forming a high-potential region oxide layer on the substrate in the high-potential predetermined region, and forming a third well and a fourth well in the substrate in the low-potential predetermined region after forming the high-potential region oxide layer. The third well and the fourth well have opposite conductivity types. The method also includes forming a low-potential region oxide layer on the substrate in the low-potential predetermined region.
The embodiment of the invention also provides a semiconductor device. The semiconductor device includes a substrate. The substrate includes a low potential region and a high potential region. The semiconductor device also includes a first well and a second well. The first well and the second well are located in the substrate of the high potential region, and the first well and the second well have opposite conductivity types. The semiconductor device also includes a high-potential region oxide layer on the substrate in the high-potential region, and a third well and a fourth well in the substrate in the low-potential region. The third well and the fourth well have opposite conductivity types. The semiconductor device also includes a low potential region oxide layer on the substrate in the low potential region. The thickness of the oxide layer in the high potential region is greater than that of the oxide layer in the low potential region.
Drawings
The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be exaggerated or minimized to clearly illustrate the technical features of the embodiments of the present invention.
Fig. 1 to 12 are a series of cross-sectional views for illustrating a method of forming a semiconductor device according to an embodiment of the present invention.
Reference numerals:
10-a first metal oxide semiconductor field effect transistor;
20-a second metal oxide semiconductor field effect transistor;
12 to a first source/drain region;
22 to a second source/drain region;
14-a first gate electrode;
24 to a second gate electrode;
100 to a substrate;
100L-low potential preset area;
100H-high potential predetermined area;
102-sacrifice of an oxide layer;
200. 300, 700, 800-implantation mask;
202-first trap;
302 to a second well;
400. 900-mask layer;
602-high potential area oxide layer;
604-a first oxide layer;
702 to a third well;
802 to a fourth well;
1102-low potential region oxide layer;
1104 to a second oxide layer;
t1, T2, T3 and T4.
Detailed Description
The following summary provides many different embodiments or examples for implementing different features of the disclosure. The following summary describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if embodiments of the present invention describe a first feature formed over or on a second feature, this indicates that embodiments may include the first feature in direct contact with the second feature, and embodiments may include additional features formed between the first and second features such that the first and second features may not be in direct contact.
It should be understood that additional operational steps may be performed before, during, or after the method, and that in other embodiments of the method, some of the operational steps may be replaced or omitted.
Furthermore, spatially relative terms, such as "under" …, "under," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature(s) of the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
In order to avoid the process of the high-voltage integrated circuit element from influencing the reliability of the low-voltage integrated circuit element, the well of the low-potential predetermined area is manufactured after the oxide layer of the high-potential area is formed. Therefore, the well of the low potential predetermined region is not affected by the formation step of the high potential region oxide layer, and the reliability of the low voltage integrated circuit device can be improved.
Fig. 1 is a partial cross-sectional view illustrating an initial step of a method of forming a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, a substrate 100 is provided, which may have at least one low predetermined region 100L and at least one high predetermined region 100H. In some embodiments, the low predetermined area 100L is used for providing a low voltage integrated circuit device (e.g., an operating voltage of 1.2 to 3.3 volts) formed thereon and/or therein, and the high predetermined area 100H is used for providing a high voltage integrated circuit device (e.g., an operating voltage of 5 to 40 volts) formed thereon and/or therein. For example, the high voltage integrated circuit device and the low voltage integrated circuit device may each include a field effect transistor, a bipolar transistor, a diode, other suitable integrated circuit devices, or a combination thereof.
In the embodiment, the substrate 100 is a silicon substrate, but the invention is not limited thereto. For example, in some other embodiments, the substrate 100 may comprise some other elemental semiconductor substrate (e.g., germanium). The substrate 100 may also include a compound semiconductor substrate (e.g., silicon carbide, gallium arsenide, indium arsenide, or indium phosphide). The substrate 100 may also comprise an alloy semiconductor substrate (e.g., a silicon germanium carbide (SiGe), gallium arsenide phosphide (GaAs), or indium gallium phosphide (InGaP)). In some embodiments, the substrate 100 may include a Semiconductor On Insulator (SOI) substrate (e.g., a Silicon On Insulator (SOI) substrate or a germanium on insulator (ge) substrate) that may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In some embodiments, the substrate 100 may include a single crystal substrate, a multi-layer substrate (multi-layer substrate), a gradient substrate (gradient substrate), other suitable substrate, or a combination thereof.
For example, the substrate 100 may have the first conductivity type (e.g., the substrate 100 is a p-type semiconductor substrate or an n-type semiconductor substrate). In some embodiments where the substrate 100 is a p-type substrate, the substrate 100 may include dopants such as boron, aluminum, gallium, indium, and thallium, and may have a doping concentration (e.g., average doping concentration) of 1014To 1016cm-3. In some embodiments where the substrate 100 is an n-type substrate, the substrate 100 may include dopants such as nitrogen, phosphorus, arsenic, antimony, bismuth, and may have a doping concentration (e.g., average doping concentration) of 1014To 1016cm-3. For convenience of understanding, the first conductivity type will be described as p-type (i.e., the substrate 100 is a p-type substrate) in this embodiment, but may be n-type in other embodiments.
In some embodiments, the substrate 100 may include a semiconductor epitaxial layer (not shown). For example, the semiconductor epitaxial layer may include a silicon epitaxial layer, a germanium epitaxial layer, a silicon carbide epitaxial layer, a gallium nitride epitaxial layer, other suitable semiconductor epitaxial layers, or a combination thereof. For example, the semiconductor epitaxial layer may be formed using Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), molecular-beam epitaxy (MBE), metal chemical vapor deposition (MOCVD), other suitable methods, or a combination thereof.
In some embodiments, the substrate 100 may include isolation features (not shown) formed therein. For example, the isolation features may be used to define active regions and provide electrical isolation required for various device devices formed in and/or on the substrate 100 in the active regions. In some embodiments, the isolation feature may include a Shallow Trench Isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.
With continued reference to fig. 1, in some embodiments, a sacrificial oxide layer 102 may be formed onOn a substrate 100. For example, the sacrificial oxide layer 102 may serve as a screen oxide layer (screen oxide) in a subsequent ion implantation process to reduce the influence of a channeling effect. In the present embodiment, the substrate 100 is a silicon substrate, and thus the sacrificial oxide layer 102 may include silicon oxide formed by a thermal oxidation process, for example, but the invention is not limited thereto. For example, in some other embodiments, the sacrificial oxide layer 102 of any suitable oxide may be formed on the substrate 100 by Chemical Vapor Deposition (CVD), spin-on coating (spin-on coating), or any other suitable method. For example, the thickness of the sacrificial oxide layer 102 may be 50 a to 50 a
However, the invention is not limited thereto.
Next, as shown in fig. 2, a first well 202 is formed in the substrate 100 of the high potential predetermined region 100H. In some embodiments, an implantation mask 200 having an opening corresponding to the first well 202 may be formed on the sacrificial oxide layer 102, and then an ion implantation process may be performed to implant appropriate dopants into the substrate 100 to form the first well 202. For example, the implantation mask 200 may be formed of photoresist, and the implantation mask 200 having an opening corresponding to the first well 202 may be formed using a photolithography process, such as photoresist coating (e.g., spin coating), soft baking (soft baking), mask alignment (mask alignment), exposure (exposure), post-exposure baking (post-exposure), photoresist development (developing), rinsing (rising), and drying (e.g., hard baking). In some embodiments, after forming the first well 202, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the implantation mask 200. In some other embodiments, the implantation mask 200 may also be a hard mask, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
In some embodiments, the first well 202 is a p-type well, which may include dopants such as boron, aluminum, gallium, indium, and thallium, and may have a doping concentration (e.g., average doping concentration) of 1016To 1018cm-3. For example, boron ions, indium ions, or boron difluoride ions (BF) can be implanted using an ion implantation process2(+) is injected into the substrate 100 of the high potential predetermined region 100H to form the p-type first well 202. In some other embodiments, the first well 202 is an n-type well, which may include dopants such as nitrogen, phosphorus, arsenic, antimony, bismuth, and which may have a doping concentration (e.g., average doping concentration) of 1016To 1018cm-3. For example, phosphorus ions or arsenic ions may be implanted into the substrate 100 of the high-potential predetermined region 100H using an ion implantation process to form the n-type first well 202.
Next, as shown in fig. 3, a second well 302 is formed in the substrate 100 of the high potential predetermined region 100H. In some embodiments, an implantation mask 300 having an opening corresponding to second well 302 may be formed on sacrificial oxide layer 102, followed by an ion implantation process to implant appropriate dopants into substrate 100 to form second well 302. For example, the implantation mask 300 may be formed of photoresist, and a photolithography process may be used to form the implantation mask 300 having an opening corresponding to the second well 302. In some embodiments, after forming the second well 302, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the implantation mask 300. In some other embodiments, the implantation mask 300 may also be a hard mask, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
In some embodiments, as shown in fig. 3, the low potential predetermined region 100L of the substrate 100 may be located between the first well 202 and the second well 302, and thus a well subsequently formed in the low potential predetermined region 100L may also be located between the first well 202 and the second well 302.
In some embodiments, the first well 202 and the second well 302 have opposite conductivity types. For example, when the first well 202 is a p-type well, the second well 302 is an n-type well and may include dopants such as nitrogen, phosphorus, arsenic, antimony, bismuth, and the second well 302 may have a doping concentration (e.g., average doping concentration) of 1016To 1018cm-3. For example, when the first well 202 is an n-well, the second well 302 isIs a p-type well and may include dopants such as boron, aluminum, gallium, indium, thallium, and the second well 302 may have a doping concentration (e.g., average doping concentration) of 1016To 1018cm-3. For example, the same or similar ion implantation processes as described above may be performed to implant appropriate dopants into the semiconductor substrate 100 to form the second well 302.
It should be understood that although the first well 202 is formed first and then the second well 302 is formed in the present embodiment, the invention is not limited thereto. In some other embodiments, the second well 302 may be formed first and then the first well 202 may be formed.
Next, as shown in fig. 4, in some embodiments, a mask layer 400 is formed on the sacrificial oxide layer 102. As shown in fig. 4, the mask layer 400 may cover the sacrificial oxide layer 102 in the low predetermined potential region 100L, but expose the sacrificial oxide layer 102 in the high predetermined potential region 100H. For example, the mask layer 400 may serve as an etching mask in a subsequent etching step for removing the sacrificial oxide layer 102 in the high-potential predetermined region 100H to prevent the sacrificial oxide layer 102 in the low-potential predetermined region 100L therebelow from being etched, which will be described in further detail later. In some embodiments, the mask layer 400 may be formed of photoresist, and the mask layer 400 may be formed using a photolithography process to cover the sacrificial oxide layer 102 of the low potential predetermined region 100L but expose the sacrificial oxide layer 102 of the high potential predetermined region 100H. In some other embodiments, the mask layer 400 may also be a hard mask layer, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
Next, as shown in fig. 5, in some embodiments, the sacrificial oxide layer 102 of the high-potential predetermined region 100H is removed. In some embodiments, an etching process may be performed using the mask layer 400 as an etching mask to remove the sacrificial oxide layer 102 of the high-potential predetermined region 100H, but leave the sacrificial oxide layer 102 of the low-potential predetermined region 100L. For example, the etching process may be a wet etching process, a dry etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etchant used in the wet etching process may include hydrofluoric acid and a chemical buffer (e.g., fluorine) added theretoAmmonium chloride). In some embodiments, the etching gas used in the dry etching process may include trifluoromethane (CHF)3) Boron trifluoride (BF)3) Other suitable etching gases, or combinations thereof. For example, after removing the sacrificial oxide layer 102 in the high-potential predetermined region 100H, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the mask layer 400.
Next, as shown in fig. 6, a high potential region oxide layer 602 is formed on the substrate 100 in the high potential scheduled region 100H. In detail, in some embodiments, the high potential region oxide layer 602 may be formed on the first well 202 and the second well 302 in the substrate 100 of the high potential predetermined region 100H.
In some embodiments, the high potential region oxide layer 602 may serve as a portion of a high voltage integrated circuit device to be subsequently formed on and/or in the substrate 100 of the high potential predetermined region 100H, and the thickness T1 (e.g., 90-90 a) of the high potential region oxide layer 602 may be adjusted according to the desired properties of the high voltage integrated circuit device
). For example, in some embodiments, the high voltage integrated circuit device is a field effect transistor (e.g., a high voltage metal oxide semiconductor field effect transistor (HVMOS)) having an operating voltage of 5 to 40 volts, and the high potential region oxide layer 602 may serve as a gate dielectric layer of the field effect transistor and may have a thickness T1 of 100 to 40 volts
For example, the high potential region oxide layer 602 may be formed using a thermal oxidation process, a chemical vapor deposition process, or any other suitable process. In the present embodiment, the substrate 100 is a silicon substrate, and thus the high potential region oxide layer 602 may include silicon oxide formed by a thermal oxidation process, for example. For example, the thermal oxidation process may include a dry thermal oxidation process (e.g., Si + O)2→SiO2) A wet thermal oxidation process (e.g., Si + 2H)2O→SiO2+2H2) Or a combination of the foregoing.
In some embodiments, as shown in fig. 6, the step of forming the high potential region oxide layer 602 may also form the first oxide layer 604 on the sacrificial oxide layer 102 in the low potential predetermined region 100L. For example, the first oxide layer 604 may also be silicon oxide formed by a thermal oxidation process, for example.
As shown in fig. 6, the total thickness of the first oxide layer 604 and the sacrificial oxide layer 102 in the low potential predetermined region 100L is T2. In some embodiments, the first oxide layer 604 and the sacrificial oxide layer 102 of the low predetermined area 100L may collectively act as a shielding oxide layer to reduce the channeling effect during a subsequent ion implantation process for forming a well in the substrate 100 of the low predetermined area 100L. In some embodiments, the total thickness T2 of the first oxide layer 604 and the sacrificial oxide layer 102 of the low predetermined area 100L is less than
And may not provide sufficient masking functionality to be compatible with standard logic processes. In some other embodiments, the total thickness T2 of the first oxide layer 604 and the sacrificial oxide layer 102 in the low predetermined area 100L is greater than
And it may not be easy to form implantation conditions matching with the standard logic process well implantation, and then it is not easy to form a low potential well conforming to the standard logic process. Therefore, in the present embodiment, the total thickness T2 of the first oxide layer 604 and the sacrificial oxide layer 102 in the low potential predetermined region 100L is 100 to 100
(e.g., 150 to
) Therefore, the above-mentioned problem caused by the total thickness T2 of the first oxide layer 604 and the sacrificial oxide layer 102 in the low predetermined area 100L being too large or too small can be avoided.
Next, as shown in fig. 7, a third well 702 is formed in the substrate 100 of the low potential predetermined region 100L. In some embodiments, an implantation mask 700 having an opening corresponding to the third well 702 may be formed on the high potential region oxide layer 602, the sacrificial oxide layer 102 and the first oxide layer 604, and then an ion implantation process may be performed to implant appropriate dopants into the substrate 100 to form the third well 702. For example, the implantation mask 700 may be formed of photoresist, and a photolithography process may be used to form the implantation mask 700 having an opening corresponding to the third well 702. In some embodiments, after forming the third well 702, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the implantation mask 700. In some other embodiments, the implantation mask 700 may also be a hard mask, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
In some embodiments, the third well 702 is a p-type well, which may include dopants such as boron, aluminum, gallium, indium, and thallium, and may have a doping concentration (e.g., average doping concentration) of 1017To 5x1018cm-3. In some other embodiments, the third well 702 is an n-type well, which may include dopants such as nitrogen, phosphorus, arsenic, antimony, bismuth, and which may have a doping concentration (e.g., average doping concentration) of 1017To 5x1018cm-3. For example, the third well 702 may be formed by implanting an appropriate dopant into the semiconductor substrate 100 using the same or similar ion implantation process as described above.
Next, as shown in fig. 8, a fourth well 802 is formed in the substrate 100 of the low potential predetermined region 100L. In some embodiments, an implantation mask 800 having an opening corresponding to the fourth well 802 may be formed on the high potential region oxide layer 602, the sacrificial oxide layer 102 and the first oxide layer 604, and then an ion implantation process may be performed to implant appropriate dopants into the substrate 100 to form the fourth well 802. For example, the implantation mask 800 may be formed of photoresist, and a photolithography process may be used to form the implantation mask 800 having an opening corresponding to the fourth well 802. In some embodiments, after forming the fourth well 802, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the implantation mask 800. In some other embodiments, the implantation mask 800 may also be a hard mask, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
In some embodiments, as shown in fig. 8, the third and fourth wells 702 and 802 in the low potential predetermined region 100L may be located between the first and second wells 202 and 302. In some embodiments, as shown in fig. 8, the third well 702 and the fourth well 802 may be adjacent to each other or substantially abutting each other.
In some embodiments, the third well 702 and the fourth well 802 have opposite conductivity types. For example, in some embodiments in which the third well 702 is a p-type well, the fourth well 802 may be an n-type well and may include dopants such as nitrogen, phosphorus, arsenic, antimony, bismuth, and the doping concentration (e.g., average doping concentration) of the fourth well 802 may be 1017To 5x1018cm-3. For example, in some embodiments in which the third well 702 is an n-type well, the fourth well 802 may be a p-type well and may include dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration (e.g., the average doping concentration) of the fourth well 802 may be 1017To 5x1018cm-3。
For example, the same or similar ion implantation processes as described above may be performed to implant appropriate dopants into the semiconductor substrate 100 to form the fourth well 802.
It should be understood that although the third well 702 is formed first and then the fourth well 802 is formed in the present embodiment, the invention is not limited thereto. In some other embodiments, the fourth well 802 may be formed first and then the third well 702 may be formed.
It should be noted that the present inventors found that the high-potential region oxide layer is formed after the well is formed in the substrate of the low-potential predetermined region in the conventional process. Therefore, the well formed in the substrate of the low potential predetermined region is affected by the formation step (e.g., thermal oxidation process) of the high potential region oxide layer, thereby degrading the characteristics and reliability of the integrated circuit device formed on/in the well formed in the substrate of the low potential predetermined region. In contrast, in the embodiment of the invention, the wells (e.g., the third well 702 and the fourth well 802) are formed in the substrate 100 of the low potential predetermined region 100L after the formation of the high potential region oxide layer 602, so that the wells formed in the substrate 100 of the low potential predetermined region 100L are not affected by the formation of the high potential region oxide layer 602 (e.g., the thermal oxidation process), thereby improving the characteristics and reliability of the integrated circuit devices formed on/in the wells (e.g., the third well 702 and the fourth well 802) formed in the substrate 100 of the low potential predetermined region 100L.
Next, as shown in fig. 9, in some embodiments, a mask layer 900 is formed on the high potential region oxide layer 602. As shown in fig. 9, the mask layer 900 may cover the high potential region oxide layer 602, but expose the sacrificial oxide layer 102 and the first oxide layer 604 in the low potential predetermined region 100L. For example, the mask layer 900 may serve as an etching mask in a subsequent etching step for removing the sacrificial oxide layer 102 and the first oxide layer 604 in the low potential predetermined region 100L to prevent the high potential region oxide layer 602 thereunder from being etched, which will be described in further detail later. In some embodiments, the mask layer 900 may be formed of a photoresist, and the mask layer 900 may be formed using a photolithography process to cover the high potential region oxide layer 602 but expose the sacrificial oxide layer 102 and the first oxide layer 604 of the low potential predetermined region 100L. In some other embodiments, the mask layer 900 may also be a hard mask layer, and the material thereof may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof.
Next, as shown in fig. 10, in some embodiments, the sacrificial oxide layer 102 and the first oxide layer 604 in the low predetermined area 100L are removed. In some embodiments, an etching process may be performed using the mask layer 900 as an etching mask to remove the sacrificial oxide layer 102 and the first oxide layer 604 in the low potential predetermined region 100L. For example, the etching process may be a wet etching process, a dry etching process, other suitable processes, or a combination thereof. For example, after removing the sacrificial oxide layer 102 and the first oxide layer 604 in the low predetermined area 100L, an appropriate process (e.g., a wet strip process and/or an ashing process) may be performed to remove the mask layer 900.
Next, as shown in fig. 11, a low-potential region oxide layer 1102 is formed on the substrate 100 in the low-potential predetermined region 100L. In detail, in some embodiments, the low potential region oxide layer 1102 may be formed on the third well 702 and the fourth well 802 in the substrate 100 of the low potential predetermined region 100L.
In some embodiments, the low potential region oxide layer 1102 may serve as a portion of a low voltage integrated circuit device to be subsequently formed on and/or in the substrate 100 of the low potential predetermined region 100L, and the thickness T3 (e.g., 20 to 20) of the low potential region oxide layer 1102 may be adjusted according to the desired properties of the low voltage integrated circuit device
). For example, in some embodiments, the low voltage integrated circuit device is a field effect transistor (e.g., a metal oxide semiconductor field effect transistor (MOS)) having an operating voltage of 1.2 to 3.3V, and the low-potential region oxide layer 1102 may serve as a gate dielectric layer of the field effect transistor and may have a thickness T3 of 25 to 3.3V
In some embodiments, as shown in fig. 11, the thickness T1 of the high potential region oxide layer 602 may be greater than the thickness T3 of the low potential region oxide layer 1102. In detail, in some embodiments, the ratio of the thickness T1 of the high potential region oxide layer 602 to the thickness T3 of the low potential region oxide layer 1102 may be 1.5 to 8.
For example, the low potential region oxide layer 1102 may be formed using a thermal oxidation process, an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, or any other suitable process. In the present embodiment, the substrate 100 is a silicon substrate, and thus the low-potential region oxide layer 1102 may include silicon oxide formed by a thermal oxidation process (e.g., a dry thermal oxidation process, a wet thermal oxidation process, or a combination thereof).
In some embodiments, as shown in fig. 11, the step of forming the low region oxide layer 1102 may also form the second oxide layer 1104 on the high region oxide layer 602. For example, the second oxide layer 1104 can also be silicon oxide formed by a thermal oxidation process, for example. In some embodiments, the thickness T4 of the second oxide layer 1104 may be less than the thickness of the low potential region oxide layer 1102Degree T3. For example, the thickness T4 of the second oxide layer 1104 may be 15 to
Then, a low voltage integrated circuit device (e.g., operating voltage of 1.2 to 3.3 volts) can be formed on and/or in the substrate 100 of the low potential predetermined region 100L. In some embodiments, the low voltage integrated circuit devices may include field effect transistors (e.g., metal oxide semiconductor field effect transistors), other suitable integrated circuit devices, or combinations thereof.
For example, in some embodiments, as shown in fig. 12, a first mosfet 10 may be formed in and/or on the third well 702, and a second mosfet 20 may be formed in and/or on the fourth well 802. As shown in fig. 12, the first mosfet 10 may include a first gate electrode 14, a first source/drain region 12 formed in a third well 702 on both sides of the first gate electrode 14, and a low-potential region oxide layer 1102 on the third well 702 may serve as a gate dielectric layer of the first mosfet 10, and the third well 702 under the first gate electrode 14 may serve as a channel region of the first mosfet 10. Similarly, as shown in fig. 12, the second mosfet 20 may include a second gate electrode 24, and second source/drain regions 22 formed in the fourth well 802 on both sides of the second gate electrode 24, and the low-potential-region oxide layer 1102 on the fourth well 802 may serve as a gate dielectric layer of the second mosfet 20, and the fourth well 802 under the second gate electrode 24 may serve as a channel region of the second mosfet 20.
In some embodiments, since the third well 702 and the fourth well 802 have opposite conductivity types, the first mosfet 10 and the second mosfet 20 also have opposite conductivity types. For example, one of the first metal oxide semiconductor field effect transistor 10 and the second metal oxide semiconductor field effect transistor 20 is a p-type metal oxide semiconductor field effect transistor (PMOS) and the other is an n-type metal oxide semiconductor field effect transistor (NMOS). In some embodiments, the first metal oxide semiconductor field effect transistor 10 and the second metal oxide semiconductor field effect transistor 20 having opposite conductivity types may together form a complementary metal oxide semiconductor field effect transistor (CMOS).
In the present embodiment, the first gate electrode 14 and the second gate electrode 24 may each comprise polysilicon, but the invention is not limited thereto. In some other embodiments, each of the first gate electrode 14 and the second gate electrode 24 may comprise a metal (e.g., W, Ti, Al, Cu, Mo, Ni, Pt, similar metallic materials, or combinations thereof), a metal alloy, a metal nitride (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, similar metallic nitrides, or combinations thereof), a metal silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, similar metallic silicides, or combinations thereof), a metal oxide (e.g., ruthenium oxide, indium tin oxide, similar metallic oxides, or combinations thereof), other suitable conductive materials, or combinations thereof. For example, a conductive blanket layer may be formed by a chemical vapor deposition process (e.g., LPVD (low pressure chemical vapor deposition) or a Plasma Enhanced Chemical Vapor Deposition (PECVD)), a physical vapor deposition process (e.g., vacuum evaporation (vacuum evaporation) or sputtering), other suitable processes, or a combination thereof, and then patterned by a suitable patterning process (e.g., photolithography, etching, other suitable processes, or a combination thereof) to form the first and second gate electrodes 14 and 24.
For example, the first source/drain may be formed by performing an ion implantation process after forming the first gate electrode 14 and the second gate electrode 24 to implant appropriate dopants into the third well 702 and the fourth well 802, respectivelyRegion 12 and a second source/drain region 22. In some embodiments, the first source/drain region 12 is an n-type doped region including an n-type dopant (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth, other suitable dopants or combinations thereof), and the second source/drain region 22 is a p-type doped region including a p-type dopant (e.g., boron, aluminum, gallium, indium, thallium, other suitable dopants or combinations thereof), but the invention is not limited thereto, and in other embodiments, the first source/drain region 12 may also be a p-type doped region and the second source/drain region 22 may be an n-type doped region. In some embodiments, the doping concentration of each of the first source/drain region 12 and the second source/drain region 22 may be 5 × 1019To 1021cm-3。
It should be understood that although the foregoing is directed to a mosfet as an example of a low voltage integrated circuit device, the invention is not limited thereto. For example, in some other embodiments, other types of integrated circuit devices (e.g., bipolar transistors, diodes, resistors, capacitors, etc.) may be formed in and/or on the wells (e.g., the third well 702 and the fourth well 802) of the low predetermined voltage region 100L. In addition, although not shown, high voltage integrated circuit devices (e.g., LDMOS, HVMOSFET, bipolar transistor, diode, resistor, capacitor, etc.) having an operating voltage of 5-40V may be formed in and/or on the wells (e.g., the first well 202 and the second well 302) of the high-voltage predefined area 100H to form a semiconductor device including both low voltage integrated circuit devices and high voltage integrated circuit devices.
In addition, it should be understood that the thermal process may be performed at an appropriate time to activate or drive in (drive-in) the dopants of the doped wells according to design requirements. For example, the thermal process may include a rapid thermal annealing (RTP) process, a furnace annealing (furace annealing) process, a Laser Spike Annealing (LSA) process, other suitable thermal processes, or a combination thereof. In some embodiments, the heat treatment temperature of the heat treatment process may be 800 to 1100 ℃, and the corresponding heat treatment time (duration) may be 10 to 60 seconds.
In summary, in the method for forming a semiconductor device according to the embodiment of the invention, the step of forming the well in the substrate in the low potential predetermined region is performed after the step of forming the high potential region oxide layer. Therefore, the well formed in the substrate of the low potential predetermined region is not affected by the formation step of the high potential region oxide layer, and the reliability of the low voltage integrated circuit device formed in and/or on the well of the low potential predetermined region of the substrate can be improved.
The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the present embodiments. It should be appreciated by those skilled in the art that other processes and structures can be readily devised or modified based on the embodiments of the present invention to achieve the same purposes and/or to achieve the same advantages as described herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the embodiments of the invention. Various changes, substitutions, or alterations may be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention.
Furthermore, each claim of the present invention may be an individual embodiment, and the scope of the present invention includes each claim of the present invention and each embodiment in combination with each other.
Claims (6)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a low potential preset area and a high potential preset area;
forming a sacrificial oxide layer on the substrate;
forming a first well and a second well in the substrate of the high potential predetermined region, wherein the first well and the second well have opposite conductivity types;
performing an etching process to remove the sacrificial oxide layer on the substrate in the high-potential predetermined region, but retaining the sacrificial oxide layer on the substrate in the low-potential predetermined region;
forming a high-potential region oxide layer on the substrate of the high-potential predetermined region and a first oxide layer on the sacrificial oxide layer on the substrate of the low-potential predetermined region, wherein the step of forming the high-potential region oxide layer and the first oxide layer comprises a thermal oxidation process, and the sum of the thicknesses of the first oxide layer and the sacrificial oxide layer on the substrate of the low-potential predetermined region is greater than or equal to
After forming the high-potential region oxide layer, wherein the sacrificial oxide layer and the first oxide layer on the substrate of the low-potential predetermined region serve as a shielding oxide layer, forming a third well and a fourth well in the substrate of the low-potential predetermined region, wherein the third well and the fourth well have opposite conductivity types; and
forming a low potential region oxide layer on the substrate in the low potential predetermined region.
2. The method as claimed in claim 1, wherein the sum of the thicknesses of the first oxide layer and the sacrificial oxide layer on the substrate in the low-potential predetermined region is 100 to 100%
3. The method as claimed in claim 1, further comprising, before the step of forming the low-potential region oxide layer on the substrate in the predetermined low-potential region:
an etching process is performed to remove the sacrificial oxide layer and the first oxide layer on the substrate in the low potential predetermined region.
4. The method as claimed in claim 3, wherein the step of performing the etching process to remove the sacrificial oxide layer and the first oxide layer on the substrate in the low-potential predetermined region further comprises:
forming a mask layer on the high-potential region oxide layer, wherein the mask layer covers the high-potential region oxide layer but exposes the sacrificial oxide layer and the first oxide layer on the substrate in the low-potential predetermined region.
5. The method as claimed in claim 1, wherein a thickness of the low potential region oxide layer is formed to be smaller than a thickness of the high potential region oxide layer.
6. The method as claimed in claim 1, wherein the substrate including the third well and the fourth well in the predetermined low-potential region forms a complementary metal oxide semiconductor field effect transistor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
| CN103681861A (en) * | 2012-08-31 | 2014-03-26 | 新唐科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| US9123642B1 (en) * | 2013-07-22 | 2015-09-01 | Cypress Semiconductor Corporation | Method of forming drain extended MOS transistors for high voltage circuits |
| CN105226020A (en) * | 2014-06-26 | 2016-01-06 | 英飞凌科技股份有限公司 | Containing semiconductor device and the manufacture method of power transistor cell and lateral transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9520296B2 (en) * | 2014-06-12 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device having a low divot of alignment between a substrate and an isolation thereof and method of forming the same |
-
2017
- 2017-12-29 TW TW106146496A patent/TWI682502B/en active
-
2018
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
| CN103681861A (en) * | 2012-08-31 | 2014-03-26 | 新唐科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| US9123642B1 (en) * | 2013-07-22 | 2015-09-01 | Cypress Semiconductor Corporation | Method of forming drain extended MOS transistors for high voltage circuits |
| CN105226020A (en) * | 2014-06-26 | 2016-01-06 | 英飞凌科技股份有限公司 | Containing semiconductor device and the manufacture method of power transistor cell and lateral transistor |
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| CN110021561A (en) | 2019-07-16 |
| TW201931525A (en) | 2019-08-01 |
| TWI682502B (en) | 2020-01-11 |
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