CN1964004A - A method to improve isolation characteristic of high pressure NMOS part - Google Patents
A method to improve isolation characteristic of high pressure NMOS part Download PDFInfo
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- CN1964004A CN1964004A CN 200510110231 CN200510110231A CN1964004A CN 1964004 A CN1964004 A CN 1964004A CN 200510110231 CN200510110231 CN 200510110231 CN 200510110231 A CN200510110231 A CN 200510110231A CN 1964004 A CN1964004 A CN 1964004A
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- high pressure
- voltage
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- trap
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Abstract
The disclosed method applies LOCOS technology with field O2 thickness as 330-4500. Wherein, the injection dosage of B for anti-breaking low-voltage P trap is 4e12-B1e13, and the power is 100KeV. This invention can obtain better isolation performance for high-voltage device.
Description
Technical field
The present invention relates to a kind of process of high-pressure MOS component, particularly relate to a kind of chip manufacturing process method of improving the high-pressure MOS component isolation characteristic.
Background technology
Liquid crystal display drive circuit adopts high pressure (more than the 12V) MOS element manufacturing usually.The manufacture craft of high-pressure MOS component is compared with common low voltage CMOS device making technics, because operating voltage much higher relatively (the low-voltage device operating voltage is generally below 3.3V) requires device that good isolation characteristic is arranged during work.Otherwise very easily cause break-through between device, cause leakage current big between device, can cause power consumption increase with device between mutual interference mutually, reduce the reliability of device.
The most frequently used isolation method of high-pressure MOS component is LOCOS (local oxidation of silicon) technology, and promptly the oxide-film of region growing one bed thickness beyond active area also claims field oxide as separator, is called for short an oxygen.Silicon area below the field oxide is the raceway groove block area, can carry out heavy doping usually in this zone and inject, and also injection or raceway groove blocking-up is on the spot injected.Above-mentioned two steps are very big for the good bad influence of isolation performance of device, the thickness of field oxygen, an energy that injects and dosage etc. have determined the height of a pipe cut-in voltage, so select conditions such as a suitable field oxygen thickness and an implantation dosage most important to the isolation of high tension apparatus.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of improving isolation characteristic of high pressure NMOS part, and it can obtain higher field pipe cut-in voltage.
For solving the problems of the technologies described above, the method that the present invention improves isolation characteristic of high pressure NMOS part is achieved by the following technical solution, and adopts LOCOS technology, and wherein, an oxygen thickness is 3300 ~4500 , and the anti-break-through implantation dosage of low pressure P trap is B (boron) 4e
12~B1e
13, energy is 100KeV.
The present invention improves isolation characteristic of high pressure NMOS part by the methods such as concentration that increase an oxygen thickness, the injection of raising low pressure P trap.Increase the gate oxide thickness that an oxygen thickness has been equivalent to increase a pipe, can effectively improve a threshold voltage that pipe is opened, also promptly improved the isolation characteristic between device.The injection of low pressure P trap has improved the break-through threshold value of high pressure NMOS field pipe parasitic channel.To form the required electric field of raceway groove just high more for transoid under high more then the oxygen of low pressure P trap implantation dosage, and therefore the cut-in voltage of a pipe is just high more, promptly obtains good high tension apparatus isolation characteristic.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done explanation in further detail:
Fig. 1 is the schematic diagram of high-pressure MOS polysilicon gate field pipe;
Wherein, the left side is a high pressure NMOS polysilicon gate field pipe (at the high pressure P well area), and the right side is high voltage PMOS field pipe; Field oxygen serves as the effect of grid oxygen at this, and low pressure P trap is infused in the anti-break-through injection that this double as is a high pressure NMOS.
Fig. 2 is the high pressure NMOS polysilicon gate field pipe cut-in voltage curve chart under different oxygen thickness;
Fig. 3 is the high pressure NMOS polysilicon gate field pipe cut-in voltage curve chart under the anti-break-through implantation dosage of different low pressure P traps.
Embodiment
The method that the present invention improves isolation characteristic of high pressure NMOS part adopts LOCOS technology, by increasing an oxygen thickness, improves the methods such as concentration of low pressure P trap injection and improves isolation characteristic of high pressure NMOS part.
For operating voltage is the high tension apparatus of 18V, if the cut-in voltage of a pipe more than 23V, is reliable to isolating then.
Embodiment one, adopts LOCOS technology, and its midfield oxygen thickness is 3400 , and the anti-break-through implantation dosage of low pressure P trap is B (boron) 7e
12, energy is 100KeV.
Embodiment two, adopt LOCOS technology, and its midfield oxygen thickness is 3600 , and the anti-break-through implantation dosage of low pressure P trap is B1e
13, energy is 100KeV.
Embodiment three, as a preferred embodiment of the present invention, adopt LOCOS technology, and its midfield oxygen thickness is 3800 , and the anti-break-through implantation dosage of low pressure P trap is B7e
12, energy is 100KeV.Under this condition, the cut-in voltage of high pressure NMOS polysilicon gate field pipe reaches 28V.
The schematic diagram of high-pressure MOS polysilicon gate field pipe as shown in Figure 1.Increase the gate oxide thickness that an oxygen thickness has been equivalent to increase a pipe, can effectively improve a threshold voltage that pipe is opened, also promptly improved the isolation characteristic between device.But owing to except that high tension apparatus, also have low-voltage device to exist,,, follow reducing of device widths, Vt (threshold voltage) is obviously risen the narrow ditch device of low pressure along with the increase of field oxygen thickness.So,, should pay special attention to the influence of an oxygen thickness to narrow channel device in case will change an oxygen thickness.In addition, along with the increase of field oxygen thickness, to low-voltage device, the deviation that distributes in its Vt face also may increase, so the thickness of increase field oxygen that can not be simply.
The injection of low pressure P trap has improved the break-through threshold value of high pressure NMOS field pipe parasitic channel.To form the required electric field of raceway groove just high more for transoid under high more then the oxygen of low pressure P trap implantation dosage, so the cut-in voltage of field-effect transistor is just high more.
Oxygen thickness to the influence of field cut-in voltage as can be seen from Figure 2.Different the high pressure NMOS polysilicon gate field pipe cut-in voltages under the oxygen thickness have been represented among the figure.Inject energy dose constant (100keV, B7e at low pressure P trap boron as seen from the figure
12) condition under, (3 field oxygen thickness is respectively 3100 shown in the figure with the increase of field oxygen thickness, 3800 and 4500 ), the cut-in voltage of high pressure NMOS polysilicon gate field pipe has risen to about 32 volts from 19 volts, basically the thickness of oxidation film of every increase by 100 , a pipe cut-in voltage improves about nearly 1V.Explanation is thick more at certain scope internal field oxygen, and the cut-in voltage of a pipe is just high more, and the isolation characteristic of device is just good more.
Low pressure P trap boron implantation dosage has represented among the figure that other condition is identical to the influence of field cut-in voltage as can be seen from Figure 3, but the high pressure NMOS polysilicon gate field pipe cut-in voltage under the anti-break-through implantation dosage of different low pressure P traps.As seen from the figure with the increase of boron implantation dosage (from 4e
12To 1e
13), the cut-in voltage of high pressure NMOS polysilicon gate field pipe has risen to about 32 volts from 22 volts.Explanation is in certain scope, and the anti-break-through implantation dosage of low pressure P trap is high more, and the cut-in voltage of a pipe is just high more, and the isolation characteristic of device is just good more.
Claims (4)
1, a kind of method of improving isolation characteristic of high pressure NMOS part adopts LOCOS technology, it is characterized in that: wherein, an oxygen thickness is 3300 ~4500 , and the anti-break-through implantation dosage of low pressure P trap is B 4e
12~B1e
13, energy is 100KeV.
2, the method for improving isolation characteristic of high pressure NMOS part according to claim 1 is characterized in that: described oxygen thickness is 3800 , and the anti-break-through implantation dosage of low pressure P trap is B 7e
12, energy is 100KeV.
3, the method for improving isolation characteristic of high pressure NMOS part according to claim 1 is characterized in that: described oxygen thickness is 3400 , and the anti-break-through implantation dosage of low pressure P trap is B 7e
12, energy is 100KeV.
4, the method for improving isolation characteristic of high pressure NMOS part according to claim 1 is characterized in that: described oxygen thickness is 3600 , and the anti-break-through implantation dosage of low pressure P trap is B 1e
13, energy is 100KeV.
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CN 200510110231 CN1964004A (en) | 2005-11-10 | 2005-11-10 | A method to improve isolation characteristic of high pressure NMOS part |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102262213A (en) * | 2011-04-22 | 2011-11-30 | 上海北京大学微电子研究院 | Method for testing influence of high voltage environment on standard cell library |
CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
CN103606537A (en) * | 2013-12-06 | 2014-02-26 | 中国电子科技集团公司第四十七研究所 | Manufacturing method of bipolar component in BICMOS (bipolar compIementary metal oxide semiconductor) integrated circuit |
-
2005
- 2005-11-10 CN CN 200510110231 patent/CN1964004A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102262213A (en) * | 2011-04-22 | 2011-11-30 | 上海北京大学微电子研究院 | Method for testing influence of high voltage environment on standard cell library |
CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
CN103137622B (en) * | 2011-11-28 | 2016-04-06 | 北大方正集团有限公司 | A kind of semiconductor device for high voltage integrated circuit and manufacture method thereof |
CN103606537A (en) * | 2013-12-06 | 2014-02-26 | 中国电子科技集团公司第四十七研究所 | Manufacturing method of bipolar component in BICMOS (bipolar compIementary metal oxide semiconductor) integrated circuit |
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