CN115172528A - Solar cell, preparation process thereof and photovoltaic module - Google Patents
Solar cell, preparation process thereof and photovoltaic module Download PDFInfo
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- CN115172528A CN115172528A CN202210899931.4A CN202210899931A CN115172528A CN 115172528 A CN115172528 A CN 115172528A CN 202210899931 A CN202210899931 A CN 202210899931A CN 115172528 A CN115172528 A CN 115172528A
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- semiconductor substrate
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- solar cell
- boron diffusion
- surfactant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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Abstract
The application relates to a solar cell, a preparation process thereof and a photovoltaic module, which comprise: providing a semiconductor substrate; texturing the semiconductor substrate to form a pre-polarizing structure; b, carrying out boron diffusion on the textured semiconductor substrate to form a boron diffusion layer, and carrying out primary acid washing, water washing and primary drying treatment on the boron diffusion layer; carrying out water washing, alkali polishing, water washing, post-cleaning, secondary acid washing, water washing, slow extraction and secondary drying treatment on the back of the semiconductor substrate to convert the pre-polarization structure into a polarization structure, wherein a polishing treatment agent for alkali polishing comprises an alkali solution, a surfactant and a defoaming agent; the ratio of the surface area of the semiconductor substrate to the projected area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1; forming a tunneling layer and a doped conducting layer on the back of the semiconductor substrate subjected to the secondary drying treatment; forming a front passivation layer and a front electrode on the front surface of the semiconductor substrate subjected to the primary drying treatment; and forming a back passivation layer and a back electrode on the surface of the doped conductive layer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of solar cell processing, in particular to a monitoring method of a solar cell preparation process.
[ background of the invention ]
In recent years, social awareness has been strengthened about environmental and energy issues worldwide. In particular, global warming due to the so-called greenhouse effect of atmospheric CO2 increase has been expected to cause serious problems. In view of this, since the solar cell power generation system is a clean power generation system that generates power using sunlight that can be uniformly received anywhere in the world, and as a power generation source, the solar cell power generation system can obtain a high power generation efficiency without using a complicated large apparatus, and further the solar cell power generation system is expected to meet the increase in power demand in the future without causing environmental destruction, public attention has been focused on the solar cell power generation system, the core component of which is a solar cell.
In a solar cell manufacturing process, a semiconductor substrate is usually required to be subjected to cleaning, texturing, diffusion, polishing, etching and other treatment processes, and the process also comprises a plurality of specific processes, so that the solar cell manufacturing process is long and complex, the unit consumption cost of a product is increased, and the productivity is reduced due to long process time.
Therefore, how to increase the cost and the productivity in the process of preparing the solar cell also becomes a problem to be solved urgently by the photovoltaic industry.
[ summary of the invention ]
In order to overcome the defects, the application provides the solar cell, the preparation process thereof and the photovoltaic module, which can effectively reduce the manufacturing cost, improve the productivity and simultaneously improve the conversion efficiency of the solar cell.
In a first aspect, the present application provides a process for preparing a solar cell, comprising the steps of:
providing a semiconductor substrate;
performing texturing treatment on the semiconductor substrate to form a pre-polarizing structure;
carrying out boron diffusion on the textured semiconductor substrate to form a boron diffusion layer, and carrying out primary acid washing, water washing and primary drying treatment on the boron diffusion layer;
carrying out water washing, alkali polishing, water washing, post-cleaning, secondary acid washing, water washing, slow extraction and secondary drying treatment on the back surface of the semiconductor substrate to convert the pre-polarization structure into a polarization structure, wherein a polishing treatment agent for alkali polishing comprises an alkali solution, a surfactant and a defoaming agent; the ratio of the surface area of the semiconductor substrate to the projection area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
forming a tunneling layer and a doped conducting layer on the back of the semiconductor substrate subjected to the secondary drying treatment;
forming a front passivation layer and a front electrode on the front surface of the semiconductor substrate subjected to the primary drying treatment; and
and forming a back passivation layer and a back electrode on the surface of the doped conducting layer.
With reference to the first aspect, the thickness of the boron diffusion layer before the primary acid washing is 60nm to 120nm; and/or the thickness of the boron diffusion layer after the primary acid washing is 40 nm-90 nm.
With reference to the first aspect, the bottom side length of the pre-polarizing structure is 10 μm to 11 μm, and the bottom side length of the polarizing structure is 5 μm to 9 μm.
With reference to the first aspect, the polishing treatment agent includes the following components in percentage by mass: 90 to 95 percent of alkaline solution, 0.5 to 1 percent of surfactant, 0.3 to 0.5 percent of sodium citrate, 0.2 to 0.5 percent of sodium benzoate and 0.2 to 3 percent of defoaming agent.
In combination with the first aspect, the surfactant includes at least one of a fluorosurfactant and a polyether surfactant; and/or the mass ratio of the surfactant in the polishing treatment agent is 0.6-0.8%.
In combination with the first aspect, the defoamer comprises a silicone-based defoamer.
In a second aspect, the present application provides a solar cell comprising:
a semiconductor substrate having opposing front and back surfaces;
the boron diffusion layer, the front passivation layer and the front electrode are positioned on the front surface of the semiconductor substrate;
the semiconductor substrate comprises a tunneling layer and a doped conducting layer, wherein the tunneling layer and the doped conducting layer are positioned on the back surface of the semiconductor substrate, a polarizing structure is arranged on the surface of the semiconductor substrate, which is in contact with the tunneling layer, and the ratio of the surface area of the semiconductor substrate to the projection area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
and the back passivation layer and the back electrode are positioned on the surface of the doped conducting layer.
With reference to the second aspect, the morphology of the polarization structure includes at least one of a pyramid shape, a pyramid shape and a prism shape, and the bottom side length of the polarization structure is 5 μm to 9 μm.
With reference to the second aspect, the thickness of the boron diffusion layer is 40nm to 90nm.
In a third aspect, the present application provides a photovoltaic module comprising a plurality of strings of solar cells, each string of solar cells being formed by electrically connecting the solar cells of the second aspect.
Compared with the prior art, the method has the following steps:
the method removes a pre-cleaning process, and adopts a polishing treatment agent comprising an alkali solution, a surfactant and a defoaming agent for polishing the back of the semiconductor substrate, so that a pre-polarization structure formed by texturing the semiconductor substrate is converted into a polarization structure, wherein the ratio of the surface area of the semiconductor substrate to the projection area of the polarization structure on the surface of the semiconductor substrate is (1.0-1.4): 1, it shows that the surface structure of the textured semiconductor substrate is changed by removing the pre-cleaning process and adopting a specific polishing treatment agent, so that the back contact effect of the semiconductor substrate is improved, the filling factor of the cell is improved, and the conversion efficiency of the solar cell is improved. In addition, a pre-cleaning process is omitted, so that the yield of the semiconductor substrate is not adversely affected, the process cost is greatly reduced, and the productivity is improved.
Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application will be realized and attained by the structure particularly pointed out in the written description and drawings.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a flow chart of the solar cell fabrication process of the present application;
FIG. 2 is a schematic view showing the external appearance of a semiconductor substrate after an alkali polishing treatment without pre-cleaning according to the present application;
FIG. 3 is a top view of a pre-polarizing structure of the present application;
FIG. 4 is a top view of the polarizing structure of the present application;
fig. 5 is a schematic structural diagram of a photovoltaic module according to the present application.
In fig. 5:
1000-a photovoltaic module;
100-solar cell;
200-a first cover plate;
300-a first encapsulation glue layer;
400-a second packaging glue layer;
500-second cover plate.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be noted that the terms "upper", "lower", "left", "right", and the like used in the embodiments of the present invention are described in terms of the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on "or" under "the other element or be indirectly on" or "under" the other element via an intermediate element.
It should be noted that the steps shown in the flowcharts of the figures may be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, the order of the steps of the embodiments is not limited to be executed in the order listed in the present specification, and in some cases, the steps shown or described may be executed in an order different from the order shown or described according to specific needs.
In the production process of the TOPCon cell, a series of processes such as cleaning, texturing, diffusion and polishing are usually performed on a silicon wafer before other coatings are prepared on the silicon wafer, and the polishing process further comprises loading, pre-cleaning, water washing, polishing treatment, water washing, post-cleaning, acid washing, water washing, slow lifting and drying, wherein the pre-cleaning operation mainly has the effect of removing pollutants diffused to a polishing process through a mixed solution of potassium hydroxide and hydrogen peroxide in a pre-cleaning tank, and usually, 3 to 6 tanks are required to be arranged for pre-cleaning, and the silicon wafer must be completely immersed in a cleaning tank liquid, so that the preparation process of the solar cell is long and complicated, the unit consumption cost of the product is increased, and the productivity is reduced due to long process time.
Therefore, the preparation process of the solar cell provided by the application can improve the productivity of the product while removing the pre-cleaning process, is simple in process, has no influence on the yield of the solar cell, and can effectively reduce the cost and save the time.
The present application relates to a process for manufacturing a solar cell, as shown in fig. 1, including the following steps:
providing a semiconductor substrate;
texturing the semiconductor substrate to form a pre-polarizing structure;
carrying out boron diffusion on the front surface of the textured semiconductor substrate to form a boron diffusion layer, and carrying out primary acid washing, water washing and primary drying treatment on the boron diffusion layer;
carrying out water washing, alkali polishing, water washing, post-cleaning, secondary acid washing, water washing, slow extraction and secondary drying treatment on the back of the semiconductor substrate to convert the pre-polarization structure into a polarization structure, wherein a polishing treatment agent for alkali polishing comprises an alkali solution, a surfactant and a defoaming agent; the ratio of the surface area of the semiconductor substrate to the projected area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
forming a tunneling layer and a doped conducting layer on the back of the semiconductor substrate subjected to the secondary drying treatment;
forming a front passivation layer and a front electrode on the front surface of the semiconductor substrate subjected to the primary drying treatment; and
and forming a back passivation layer and a back electrode on the surface of the doped conducting layer.
In the scheme, the back of the semiconductor substrate is polished by adopting a polishing treatment agent comprising an alkali solution, a surfactant and a defoaming agent without a pre-cleaning process, so that a pre-polarization structure formed by etching the semiconductor substrate is converted into a polarization structure, wherein the ratio of the surface area of the semiconductor substrate to the projection area of the polarization structure on the surface of the semiconductor substrate is (1.0-1.4): 1, the fact that the pre-cleaning process is removed and a specific polishing treatment agent is adopted leads the surface structure of the textured semiconductor substrate to be changed, thereby improving the back contact effect of the semiconductor substrate, improving the filling factor of the cell and improving the conversion efficiency of the solar cell. In addition, the method and the device remove the pre-cleaning process, have no negative effect on the yield of the semiconductor substrate, greatly reduce the process cost and further improve the productivity.
It is understood that the pre-polarization structure and the polarization structure are textured structures formed by surface treatment on the semiconductor substrate, the textured structures can increase secondary reflection to reduce the reflectivity of the battery piece, and the polarization structure can be at least one of pyramid, pyramid and prism, for example.
In the present application, the ratio of the surface area of the semiconductor substrate to the projected area of the polarizing structure on the surface of the semiconductor substrate is (1.0 to 1.4): 1, specifically, for example, may be 1: 1. 1.1: 1. 1.2: 1. 1.3:1 or 1.4:1, etc., without limitation herein. According to the method, the semiconductor substrate is polished by the polishing treatment agent comprising the alkali solution, the surfactant and the defoaming agent, so that the surface area of the polarized light structure after polishing treatment is reduced, and the projection area of the polarized light structure on the surface of the semiconductor substrate is reduced.
Hereinafter, a process for manufacturing a solar cell according to the present application will be described in detail and fully with reference to the accompanying drawings in the embodiments of the present invention, wherein the embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
in some embodiments, the front surface of the semiconductor substrate is the surface facing the sun (i.e., the light-receiving surface) and the back surface of the semiconductor substrate is the surface facing away from the sun (i.e., the backlight surface).
In some embodiments, the semiconductor substrate is a silicon substrate, which may be a polycrystalline silicon substrate, a monocrystalline silicon substrate, or a quasi-monocrystalline silicon substrate.
In some embodiments, the semiconductor substrate may be an N-type substrate, and the solar cell fabricated therefrom is a TOPcon cell.
In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, which is not limited herein.
And 200, performing texturing treatment on the semiconductor substrate to form a pre-polarization structure.
In some embodiments, the texturing process may be performed by etching, and the etching process may be chemical etching, laser etching, mechanical method, plasma etching, and the like, which are not limited herein. Illustratively, when the semiconductor substrate is a single crystal silicon substrate, texturing may be performed using an alkaline solution such as a potassium hydroxide solution; when the semiconductor substrate is a polysilicon substrate, texturing may be performed using an acidic solution such as a hydrofluoric acid solution. In addition, a small amount of a texturing additive may be added to the acidic solution or the alkaline solution.
In the embodiment of the application, the surface of the silicon substrate has a pre-polarization structure through texturing, so that a light trapping effect is generated, the absorption quantity of the solar cell to light is increased, and the conversion efficiency of the solar cell is improved.
In some embodiments, the etching depth of one side of the semiconductor substrate is 3 μm to 6 μm, and specifically, the etching depth of one side may be 3 μm, 4 μm, 5 μm or 6 μm, but is not limited to the recited values, and other values not recited in the range of the values are also applicable.
In some embodiments, an emitter may be formed on the surface of the semiconductor substrate by using any one or more of high-temperature diffusion, slurry doping, or ion implantation before etching.
And 300, performing boron diffusion on the front surface of the textured semiconductor substrate to form a boron diffusion layer, and performing primary acid washing, water washing and primary drying treatment on the boron diffusion layer.
In some embodiments, a boron diffusion layer may be formed on a surface of a semiconductor substrate by any one or more of high temperature diffusion, slurry doping, or ion implantation.
In a specific embodiment, the boron diffusion process is to form a boron diffusion layer by diffusing boron atoms through a boron source. The boron source may be, for example, a boron tribromide diffusion process, whereby the microcrystalline silicon phase of the crystalline silicon is converted to the polycrystalline silicon phase. Because the surface of the semiconductor substrate has high-concentration boron, a borosilicate glass layer (BSG) is usually formed, the borosilicate glass layer has a metal gettering effect and can influence the normal operation of a solar cell, the borosilicate glass layer (BSG) needs to be removed by pickling the boron diffusion layer once, pickling solution remained on the surface of the silicon wafer is removed by washing with water, and the silicon wafer is dried once for subsequent treatment.
In some embodiments, the solution for the primary acid washing includes at least one of hydrofluoric acid, hydrogen peroxide, sulfuric acid, and nitric acid.
In some embodiments, the thickness of the boron diffusion layer before the primary acid cleaning is 60nm to 120nm, and specifically, may be 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, or 120nm, and the like, which is not limited herein. In some embodiments, the thickness of the boron diffusion layer after the primary acid washing is 40nm to 90nm, and specifically, may be 40nm, 50nm, 60nm, 70nm, 80nm, or 90nm, and the like, which is not limited herein.
Compared with the traditional process (the thickness of the boron diffusion layer is thinner), the thickness of the boron diffusion layer formed by boron diffusion is thicker and can reach 60 nm-120 nm, the diffusion layer with the thickness of 40 nm-90 nm is remained on the front surface of the semiconductor substrate after the semiconductor substrate is subjected to primary acid washing, the effect of protecting the semiconductor substrate can be achieved, and the influence of the subsequent back polishing process on the front surface of the semiconductor substrate is avoided.
Optionally, before the texturing process, a step of cleaning the semiconductor substrate may be further included to remove metal and organic contaminants on the surface.
the appearance of the semiconductor substrate (silicon wafer) processed in step 400 is shown in fig. 2, and as can be seen in fig. 2: the appearance of the silicon wafer is normal, and the silicon wafer is in a normal range after being detected by electroluminescent defects (component EL).
In some embodiments, the polishing treatment agent comprises the following components in percentage by mass: 90 to 95 percent of alkali solution, 0.5 to 1 percent of surfactant, 0.3 to 0.5 percent of sodium citrate, 0.2 to 0.5 percent of sodium benzoate and 0.2 to 3 percent of defoaming agent.
In some embodiments, the alkaline solution comprises at least one of sodium hydroxide and potassium hydroxide, and the semiconductor substrate is polished by the alkaline solution, so that nitrogen-containing polluted wastewater is not generated in a treatment link, the cost is reduced, and the environmental pollution is reduced.
In some embodiments, the surfactant comprises at least one of a fluorosurfactant and a polyether surfactant. The fluorine-containing surfactant can be, for example, a Fluorine Surfactant (FSA) which is a surfactant with fluorine carbon chains as nonpolar groups, i.e. hydrogen atoms on the hydrocarbon chains are partially or completely replaced by fluorine atoms, the FSA has high surface activity, high heat resistance stability and high chemical stability, and the lowest surface tension of the FSA can reach 20Mn/m, thereby being beneficial to the surface treatment of the semiconductor substrate by an alkali solution. The polyether surfactant comprises at least one of nonylphenol polyoxyethylene ether, isomeric tridecanol polyoxyethylene ether, ethylene glycol butyl ether and diethylene glycol dimethyl ether, and the polyether surfactant serving as a part of a polishing treatment agent can play a good role in surface activity and cleaning the surface of a semiconductor substrate silicon wafer, and particularly plays a good role in cleaning organic pollutants such as oil, mechanical oil and the like. Preferably, the molecular weight of the polyether surfactant is 1000 to 7000, and specifically 1000, 2000, 3000, 4000, 5000, 6000 or 7000.
In some embodiments, the surfactant is present in the polishing treatment agent in an amount of 0.5% to 1%, specifically 0.5%, 0.6%, 0.65%, 0.7%, 0.75%, 0.8%, 0.9%, or 1%, and preferably 0.6% to 0.8%.
In some embodiments, the defoamer comprises a silicone based defoamer, which can be, for example
Airex 900、
Airex 901W、
Airex 902W and
at least one of Airex 904W. The silicone defoaming agent is prepared by taking silicone oil and an organic silicon compound as basic components and matching with a proper solvent, an emulsifier or an inorganic filler through a special process. The siloxane in the defoaming agent integrates the characteristics of chemical stability, physiological inertia, good high-temperature and low-temperature performance and the like, and has the excellent effects of strong defoaming capability, high defoaming speed and long foam inhibition without rebound when used for treating a semiconductor substrate.
In some embodiments, the sodium citrate is present in the polishing agent in an amount of 0.3% to 0.5%, and specifically 0.3%, 0.4%, or 0.5%, and the like, and the sodium citrate in the above range has a strong metal ion complexing ability and a cleaning effect on the semiconductor substrate, so that the semiconductor substrate can be polished while achieving a certain cleaning effect.
In some embodiments, the sodium benzoate may be present in the polishing agent in an amount of 0.2% to 0.5%, specifically 0.2%, 0.3%, 0.4%, or 0.5%, and the like, and sodium benzoate in the above range may serve to stabilize the polishing agent system.
The alkali polishing treatment agent realizes good decontamination to the surface of a silicon wafer while realizing alkali polishing by solubilization, complexation and reduction of surface tension, so that a semiconductor substrate obtains a good cleaning effect through back polishing treatment. Moreover, through the interaction of the surfactant, the defoaming agent and the alkali solution, the corrosion of the polishing treatment agent to the front surface of the semiconductor substrate can be effectively reduced, the corrosion rate of the back surface of the semiconductor substrate is improved, the size of the tower base of the back surface polarization structure is reduced, the back surface contact effect of the semiconductor substrate is improved, the filling factor of the cell is improved, and the conversion efficiency of the solar cell is improved.
In some embodiments, the length of the bottom side of the pre-polarizing structure is 10 μm to 11 μm, specifically 10 μm, 10.1 μm, 10.2 μm, 10.3 μm, 10.4 μm, 10.5 μm, 10.6 μm, 10.7 μm, 10.8 μm, 10.9 μm, or 11 μm, and the length of the bottom side of the polarizing structure is 5 μm to 9 μm, specifically 5 μm, 6 μm, 7 μm, 8 μm, or 9 μm. Fig. 3 is a top view of a pre-polarizing structure prepared in the present application, and fig. 4 is a top view of a polarizing structure prepared in the present application, as can be seen by comparing fig. 3 and fig. 4: after the alkali polishing process, the side length of the bottom surface of the pre-polarization structure is reduced, the size of the tower base is reduced, and the projection area of the polarization structure on the surface of the semiconductor substrate is reduced.
And 500, forming a tunneling layer and a doped conducting layer on the back of the semiconductor substrate subjected to the secondary drying treatment.
In some embodiments, a tunneling layer may be formed on a back surface of the semiconductor substrate, and then a doped conductive layer may be formed on a surface of the tunneling layer.
In some embodiments, the present application is not limited to the specific operation of forming the tunneling layer. Illustratively, the rear surface of the semiconductor substrate 1 may be oxidized by any one of an ozone oxidation method, a high-temperature thermal oxidation method, and a nitric acid oxidation method.
In some embodiments, the tunneling layer is a thin oxide layer, for example, may be silicon oxide or a metal oxide, and may contain other additional elements, such as nitrogen. The tunneling layer may not have a perfect tunnel barrier in practical effect because it contains defects such as pinholes, for example, which may cause other charge carrier transport mechanisms (e.g., drift, diffusion) to dominate over the tunneling effect.
In some embodiments, the present application is not limited to the specific operation of forming the doped conductive layer. Illustratively, any one of the methods of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition and atmospheric pressure chemical vapor deposition may be used to deposit a doped conductive layer on the surface of the tunneling layer for protecting the tunneling layer, and then the conductive layer is doped with silicon to form a high-low junction (n/n) + Si) which can effectively reduce the recombination rate of carriers on the back surface of the cell, and further improve the conversion efficiency of the solar cell.
In some embodiments, the doped conductive layer may be formed by performing an in-situ doping process while depositing the conductive layer, and the doped conductive layer includes at least one of silicon carbide and polysilicon, that is, the doped conductive layer may be a doped polysilicon layer, a silicon carbide layer, or a composite layer of the doped polysilicon layer and the silicon carbide layer.
In some embodiments, the doped polysilicon layer is a phosphorus-doped polysilicon layer, and the phosphorus-doped polysilicon layer may be, for example: and depositing a polysilicon layer on the surface of the tunneling oxide layer and carrying out in-situ doping treatment to form a phosphorus-doped polysilicon layer. The phosphorus diffusion process may also use any one or more of high-temperature diffusion, slurry doping, or ion implantation, which is not limited herein.
In some embodiments, the phosphorus-doped polysilicon layer is doped heavilyDegree of 1X 10 19 cm -3 ～1×10 21 cm -3 The doping concentration may specifically be 1 × 10 19 cm -3 、1×10 20 cm -3 Or 1X 10 21 cm -3 And the like, the doping concentration is controlled within the range, which is beneficial to improving the passivation performance.
And 600, forming a front passivation layer and a front electrode on the front surface of the semiconductor substrate subjected to the primary drying treatment, and forming a back passivation layer and a back electrode on the surface of the doped conductive layer.
In some embodiments, the backside passivation layer may include, but is not limited to, a single-layer oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like. For example, the back passivation layer is made of silicon nitride, the silicon nitride thin film layer can play a role of an antireflection film, the silicon nitride thin film has good insulativity, compactness and stability and the capability of shielding impurity ions, and the silicon nitride thin film layer can passivate a semiconductor substrate, so that the photoelectric conversion efficiency of the solar cell is obviously improved.
In some embodiments, the front passivation layer may include, but is not limited to, a single-layer oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like. Of course, the front passivation layer may also be another type of passivation layer, and the specific material of the front passivation layer is not limited in the present invention, for example, in another embodiment, the front passivation layer may also be a stacked tunnel oxide layer of aluminum oxide and silicon nitride, etc. The front passivation layer can generate good passivation and antireflection effects on the semiconductor substrate, and is beneficial to improving the conversion efficiency of the cell.
In some embodiments, the front passivation layer and the back passivation layer may be respectively prepared by any one of Atomic Layer Deposition (ALD) and Plasma Enhanced Chemical Vapor Deposition (PECVD), and the preparation method of the front passivation layer and the back passivation layer is not limited in the present invention. Accordingly, the equipment used for deposition may be ALD equipment, PECVD equipment, etc.
It should be noted that, in the embodiments of the present application, the thicknesses of the front passivation layer and the back passivation layer are not limited, and can be adjusted by a person skilled in the art according to actual situations. Illustratively, the thickness of the front passivation layer is 10nm to 150nm, and may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, or the like. The thickness of the back passivation layer is 50nm to 150nm, and may be, for example, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, or the like.
In some embodiments, the front main grid and the front auxiliary grid are printed on the front surface of the semiconductor substrate by using slurry, and are dried to form corresponding front electrodes, the back main grid and the back auxiliary grid are printed on the back surface of the semiconductor substrate by using slurry, and are dried to form corresponding back electrodes, and finally the dried cell piece is sintered to obtain the solar cell.
The specific material of the front electrode and the back electrode is not limited in the embodiment of the invention. For example, the front electrode is a silver electrode or a silver/aluminum electrode, and the back electrode is a silver electrode or a silver/aluminum electrode.
The application provides a solar cell prepared by the preparation method, which comprises the following steps:
a semiconductor substrate having opposing front and back surfaces;
the boron diffusion layer, the front passivation layer and the front electrode are positioned on the front surface of the semiconductor substrate;
the semiconductor device comprises a tunneling layer and a doped conducting layer which are positioned on the back surface of a semiconductor substrate, wherein a polarizing structure is arranged on the surface of the semiconductor substrate, which is in contact with the tunneling layer, and the ratio of the surface area of the semiconductor substrate to the projection area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
and the back passivation layer and the back electrode are positioned on the surface of the doped conductive layer.
In the above aspect, in the solar cell of the present application, the ratio of the surface area of the semiconductor substrate to the projected area of the polarizing structure on the surface of the semiconductor substrate (1.0 to 1.4): 1, the surface area of the polarized structure on the surface of the semiconductor substrate is smaller, so that the metal composition of the electrode and the semiconductor substrate is reduced, and the photoelectric conversion efficiency of the cell is improved.
It is understood that the solar cell may be a TOPCon solar cell, the front electrode passes through the front passivation layer to form an ohmic contact with the boron diffusion layer, the back electrode passes through the back passivation layer to form an ohmic contact with the doped conductive layer, and the doped conductive layer and the tunneling layer form a TOPCon structure.
In some embodiments, the ratio of the surface area of the conductor substrate to the projected area of the polarizing structure on the surface of the semiconductor substrate is (1.0 to 1.4): 1, in particular, may be 1: 1. 1.1: 1. 1.2: 1. 1.3:1 or 1.4:1, etc. The polishing treatment agent for alkali polishing, which comprises an alkali solution, a surfactant and a defoaming agent, is used for polishing the semiconductor substrate, so that the bottom area of the pre-polarizing structure is reduced, the height of the pre-polarizing structure is unchanged, and the projection area of the polarizing structure on the surface of the semiconductor substrate is reduced.
In some embodiments, the semiconductor substrate is an N-type semiconductor substrate, and the N-type semiconductor substrate may be a crystalline silicon substrate (silicon substrate), such as one of a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the embodiments of the present application are not limited to the specific type of the semiconductor substrate.
In some embodiments, the thickness of the N-type semiconductor substrate is 60 μm to 240 μm, and specifically, may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, which is not limited herein.
In some embodiments, the boron-doped diffusion layer is an emitter.
In some embodiments, the boron diffusion layer has a thickness of 40nm to 90nm, and specifically may be 40nm, 50nm, 60nm, 70nm, 80nm, or 90nm.
In some embodiments, the topography of the polarizing structures comprises at least one of a pyramid shape, and a prism shape.
In some embodiments, the side length of the bottom surface of the polarization structure is 5 μm to 9 μm, and may be 5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8.5 μm or 9 μm, and it is understood that the bottom surface of the polarization structure is a polygonal structure, and the side length of the bottom surface of the polarization structure refers to the side length of a polygon of the polarization structure on the semiconductor substrate.
In some embodiments, the tunneling layer may be at least one or more of a silicon oxide layer, an aluminum oxide layer, and a silicon oxynitride layer. The thickness of the tunneling layer is 0.8 nm-2 nm. Specifically, the tunneling layer has a thickness of 0.8nm, 0.9nm, 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, or the like. The thickness of the tunneling layer refers to the thickness of the tunneling layer relative to the formation surface. The thickness of the tunneling layer is too large, which is not beneficial to reducing the contact resistance of the tunneling layer. By controlling the thickness of the tunneling layer, a decrease in the fill factor due to contact resistance can be suppressed. According to the solar cell, the tunnel layer is formed on the back surface of the semiconductor substrate, so that the open-circuit voltage of the solar cell can be improved, and the efficiency of the solar cell is enhanced.
In some embodiments, the tunneling layer is a thin oxide layer, for example, may be silicon oxide or a metal oxide, and may contain other additional elements, such as nitrogen. The tunneling layer may not have a perfect tunnel barrier in practical effect because it contains defects such as pinholes, for example, which may cause other charge carrier transport mechanisms (e.g., drift, diffusion) to dominate over the tunneling effect.
In some embodiments, the doped conductive layer includes at least one of silicon carbide and polysilicon, i.e., the doped conductive layer may be a doped polysilicon layer, a silicon carbide layer, or a composite layer of a doped polysilicon layer and a silicon carbide layer. Specifically, the dopant of the doped conductive layer is an n-type dopant, which may be, for example, an n-type impurity of a group V element (including P, as, bi, sb, and the like).
In some embodiments, the doped conductive layer is a phosphorus-doped polysilicon layer with a doping concentration of 1 × 10 19 cm -3 ～1×10 21 cm -3 The doping concentration may specifically be 1 × 10 19 cm -3 、1×10 20 cm -3 Or 1X 10 21 cm -3 And the like, the doping concentration is controlled within the range, which is beneficial to improving the passivation performance.
In some embodiments, the thickness of the doped conductive layer is 100nm to 200nm, and specifically, the thickness of the doped conductive layer may be, for example, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, or 200nm.
In some embodiments, the front passivation layer may include, but is not limited to, a single-layer oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like. The front passivation layer can generate a good passivation effect on the semiconductor substrate, and is beneficial to improving the conversion efficiency of the cell. It should be noted that the front passivation layer may also function to reduce reflection of incident light, and in some examples, may also be referred to as an anti-reflection layer.
In some embodiments, the thickness of the front passivation layer is in a range of 10nm to 150nm, and specifically may be 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, or the like, or may be other values within the above range, which is not limited herein.
In some embodiments, the backside passivation layer may include, but is not limited to, a single-layer oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like. When the back passivation layer is a silicon nitride layer and a silicon oxide layer which are arranged in a stacked mode or a silicon nitride layer and a silicon oxynitride layer which are arranged in a stacked mode, the silicon nitride layer is located on the surface of the doped conducting layer, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
In some embodiments, the thickness of the back passivation layer is in a range of 50nm to 150nm, and specifically may be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, or the like, or may be other values within the above range, which is not limited herein.
In some embodiments, the front electrode and the back electrode are both metal grid line electrodes, and the material of the metal grid line electrodes includes at least one of silver and aluminum.
The metal grid line electrode comprises a main grid line and an auxiliary grid line, the auxiliary grid line is connected with the main grid line and used for collecting current generated by the solar cell, and the main grid line is used for collecting the current on the auxiliary grid line.
Optionally, the plurality of main gate lines are distributed at equal intervals, so that the current collected by each main gate line is more uniform.
For the specific structure of the solar cell, such as the specific type of each layer, reference may be made to the description related to the preparation method of the solar cell, and the detailed description is omitted here.
In a third aspect, the present application provides a photovoltaic module 1000 comprising a string of solar cells as described above formed by electrical connections.
Specifically, referring to fig. 5, the photovoltaic module 1000 includes a first cover plate 200, a first encapsulant layer 300, a solar cell string, a second encapsulant layer 400, and a second cover plate 500.
In some embodiments, the solar cell string includes a plurality of solar cells 100 connected by conductive tapes, and the connection manner between the solar cells 100 may be partial lamination or splicing.
In some embodiments, the first cover plate 200 and the second cover plate 500 may be transparent or opaque cover plates, such as glass cover plates and plastic cover plates.
The two sides of the first packaging adhesive layer 300 are respectively contacted and attached with the first cover plate 200 and the battery string, and the two sides of the second packaging adhesive layer 400 are respectively contacted and attached with the second cover plate 500 and the battery string. The first and second encapsulant layers 300 and 400 may be ethylene-vinyl acetate copolymer (EVA) adhesive films, polyethylene octene co-elastomer (POE) adhesive films, or polyethylene terephthalate (PET) adhesive films, respectively.
The photovoltaic module 1000 may also be encapsulated in a side-edge-all-around manner, that is, the side edge of the photovoltaic module 1000 is encapsulated by an encapsulation tape, so as to prevent the photovoltaic module 1000 from generating a lamination offset phenomenon during the lamination process.
The photovoltaic module 1000 further includes an edge sealing member, which is fixedly sealed to a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixedly sealed to the edge of the photovoltaic module 1000 near the corner. The edge seal may be a high temperature resistant tape. The high-temperature-resistant adhesive tape has excellent high-temperature-resistant characteristic, cannot be decomposed or fall off in the laminating process, and can ensure reliable packaging of the photovoltaic module 1000. Wherein, two ends of the high temperature resistant adhesive tape are respectively fixed on the second cover plate 500 and the first cover plate 200. The two ends of the high-temperature-resistant adhesive tape can be respectively bonded with the second cover plate 500 and the first cover plate 200, and the middle part of the high-temperature-resistant adhesive tape can limit the side edge of the photovoltaic module 1000, so that the photovoltaic module 1000 is prevented from laminating and deviating in the laminating process.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A preparation process of a solar cell is characterized by comprising the following steps:
providing a semiconductor substrate;
performing texturing treatment on the semiconductor substrate to form a pre-polarizing structure;
carrying out boron diffusion on the textured semiconductor substrate to form a boron diffusion layer, and carrying out primary acid washing, water washing and primary drying treatment on the boron diffusion layer;
carrying out water washing, alkali polishing, water washing, post-cleaning, secondary acid washing, water washing, slow extraction and secondary drying treatment on the back surface of the semiconductor substrate to convert the pre-polarization structure into a polarization structure, wherein a polishing treatment agent for alkali polishing comprises an alkali solution, a surfactant and a defoaming agent, and the ratio of the surface area of the semiconductor substrate to the projection area of the polarization structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
forming a tunneling layer and a doped conducting layer on the back of the semiconductor substrate subjected to the secondary drying treatment;
forming a front passivation layer and a front electrode on the front surface of the semiconductor substrate subjected to the primary drying treatment; and
and forming a back passivation layer and a back electrode on the surface of the doped conducting layer.
2. The production process according to claim 1, wherein the thickness of the boron diffusion layer before the primary acid washing is 60nm to 120nm; and/or the thickness of the boron diffusion layer after the primary acid washing is 40 nm-90 nm.
3. The preparation process according to claim 1, wherein the bottom side of the pre-polarizing structure is 10 μm to 11 μm long, and the bottom side of the polarizing structure is 5 μm to 9 μm long.
4. The preparation process according to claim 1, wherein the polishing treatment agent comprises the following components in percentage by mass: 90 to 95 percent of alkaline solution, 0.5 to 1 percent of surfactant, 0.3 to 0.5 percent of sodium citrate, 0.2 to 0.5 percent of sodium benzoate and 0.2 to 3 percent of defoaming agent.
5. The production process according to claim 1, wherein the surfactant includes at least one of a fluorine-containing surfactant and a polyether-based surfactant; and/or the mass ratio of the surfactant in the polishing treatment agent is 0.6-0.8%.
6. The process of claim 1, wherein the defoamer comprises a silicone-based defoamer.
7. A solar cell, comprising:
a semiconductor substrate having opposing front and back surfaces;
the boron diffusion layer, the front passivation layer and the front electrode are positioned on the front surface of the semiconductor substrate;
the semiconductor substrate comprises a tunneling layer and a doped conducting layer, wherein the tunneling layer and the doped conducting layer are positioned on the back surface of the semiconductor substrate, a polarizing structure is arranged on the surface of the semiconductor substrate, which is in contact with the tunneling layer, and the ratio of the surface area of the semiconductor substrate to the projection area of the polarizing structure on the surface of the semiconductor substrate is (1.0-1.4): 1;
and the back passivation layer and the back electrode are positioned on the surface of the doped conducting layer.
8. The solar cell according to claim 7, wherein the topography of the polarization structure comprises at least one of a pyramid shape, and a prism shape, and wherein the bottom side of the polarization structure is 5 μm to 9 μm.
9. The solar cell according to claim 7, wherein the boron diffusion layer has a thickness of 40nm to 90nm.
10. A photovoltaic module comprising a plurality of strings of solar cells, each string of solar cells being formed by electrically connecting solar cells according to any one of claims 7 to 9.
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