CN115172165A - 一种逆导型mos栅控晶闸管的制造方法 - Google Patents

一种逆导型mos栅控晶闸管的制造方法 Download PDF

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CN115172165A
CN115172165A CN202210949239.8A CN202210949239A CN115172165A CN 115172165 A CN115172165 A CN 115172165A CN 202210949239 A CN202210949239 A CN 202210949239A CN 115172165 A CN115172165 A CN 115172165A
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刘超
汪淳朋
杨超
陈万军
张波
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363Thyristors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect

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Abstract

本发明属于功率半导体技术领域,具体的说是涉及一种逆导型MOS栅控晶闸管的制造方法。本发明中的一种逆导型MOS栅控晶闸管的制造方法,在进行结终端场限环注入的同时,在元胞区注入形成P+区,等效增加了器件反向导通时PN结的P区浓度,减小了器件反向的反向导通压降。本发明的一种逆导型MOS栅控晶闸管的制造方法,能够与现有MOS栅控晶闸管工艺相兼容。本发明的有益效果为:在牺牲器件部分正向导通能力的基础上,大幅提升了器件的反向导通能力。

Description

一种逆导型MOS栅控晶闸管的制造方法
技术领域
本发明属于功率半导体技术领域,具体的说是涉及一种逆导型MOS栅控晶闸管的制造方法。
背景技术
随着人类社会的不断发展,能源的消耗量也不断增加,增加产出的同时,对于电能的利用率有着越来越高的要求。这些要求的实现,有赖于电力电子器件的发展。MOS栅控晶闸管作为一种新型功率器件,也得到了大家的关注。
MOS栅控晶闸管(MOS Controlled Thyristor,简称MCT)是一种兼具功率MOS和晶闸管优点的半导体器件,它具有电压控制驱动、无电流饱和特性和功率密度高的优点,非常适合应用在高功率领域。典型的MCT器件不具备逆向导通能力,而实际电路中如想正常工作,往往需要并连一个反向二极管,以便实现反向续流能力。以脉冲放电电路为例,若不具备反向导通能力,则不能实现连续脉冲过程,其反向将产生电压停滞,能量难以得到顺畅释放,则易发生器件损坏。
为解决此问题,人们提出了RC-MCT(Reverse Conducting MCT)。相比于传统的MCT而言,RC-MCT可以使用在脉冲功率电路中,不需要并联续流二极管,器件内部存在反向电流泄放通道,这样的优点是在不增加晶胞宽度的基础上,实现反向逆导功能,减小脉冲电路复杂度,便于电路集成,降低成本。传统RC-MCT在反向导通过程中,由于p-well区的浓度不够高,导致反向的导通压降较高,不利于RC-MCT的应用。
发明内容
本发明的目的是提供一种逆导型MOS栅控晶闸管的制造方法,解决传统RC-MCT反向导通电压较高的问题。
本发明的技术方案:一种逆导型MOS栅控晶闸管的制造方法,包括以下步骤:
第一步:选取N型硅片作为衬底硅片,即结构中的N-漂移区8,首先在N-漂移区8背面一端通过离子注入N型杂质并推结形成N型FS层9;如图5所示;
第二步:在N-漂移区8上表面一端通过光刻离子注入P型杂质并推结形成P+区4和终端P型场限环;元胞如图6所示;
第三步:在N-漂移区8上表面一端通过热氧化形成栅氧化层3,并在栅氧化层3上淀积一层多晶硅/金属,再刻蚀形成栅电极1;如图7所示;
第四步:利用离子注入和高温推结工艺,在N-漂移区8上层注入P型杂质并推结形成P阱区7,P阱区7一端的上表面与栅氧化层3底部接触;如图8所示;
第五步:利用离子注入和高温推结工艺,在P阱区7上层注入N型杂质形成N阱区6,N阱区6一端的上表面与栅氧化层3底部接触;如图9所示;
第六步:利用离子注入和高温推结工艺,在N阱区6上层注入P型杂质形成P型深阱区5,P型深阱区5一端的上表面与栅氧化层3底部接触;如图10所示;
第七步:在器件上表面淀积BPSG绝缘介质层,刻蚀欧姆接触孔;
第八步:在N-漂移区8上表面另一端淀积金属,形成阴极金属2;阴极金属2的底部与P+区4、N阱区6、P型深阱区5另一端的上表面接触;如图11所示;
第九步:在器件表面淀积钝化层;
第十步:向背面N型FS层9下层通过光刻离子注入P型杂质并进行离子激活,形成P型阳极区10;
第十一步:向背面N型FS层9下层一端通过光刻离子注入N型杂质并进行离子激活,形成N型阳极区11;如图12所示;
第十二步:在器件下表面进行金属淀积形成阳极12;如图12所示;
本发明的有益效果为,本发明所提出的逆导MOS栅控晶闸管的制造方法,通过提高反向PN结P区的浓度,降低RC-MCT的反向导通压降。
附图说明
图1是常规平面栅型RC-MCT元胞结构示意图;
图2是本发明的平面栅型RC-MCT元胞结构示意图;
图3是常规的槽栅型RC-MCT元胞结构示意图;
图4是本发明的槽栅型RC-MCT元胞结构示意图;
图5是本发明的制造工艺流程中形成N型FS层8后的结构示意图;
图6是本发明的制造工艺流程中通过离子注入P型杂质推结形成P+区的结构示意图;
图7是本发明的制造工艺流程中形成栅氧后,在栅氧层上淀积一层多晶硅/金属再刻蚀形成栅电极的结构示意图;
图8是本发明的制造工艺流程中通过离子注入P型杂质推结形成P阱区的结构示意图;
图9是本发明的制造工艺流程中通过离子注入N型杂质推结形成N阱区的结构示意图;
图10是本发明的制造工艺流程中通过离子注入P型杂质推结形成P深阱区的结构示意图;
图11是本发明的制造工艺流程中正面金属化后的结构示意图;
图12是本发明的制造工艺流程中向背面注入P型杂质并进行离子激活,形成P型阳极区,再向背面注入N型杂质并进行离子激活,形成N型阳极区后的结构示意图;
图13是本发明的制造工艺流程中背面金属化的结构示意图;
图14为本发明制造工艺的RC-MCT与常规RC-MCT器件反向导通特性曲线对比示意图;
图15为本发明制造工艺的RC-MCT与常规RC-MCT器件正向导通特性曲线对比示意图;
具体实施方式
下面结合附图,详细描述本发明的技术方案:
本发明提供一种逆导型MOS栅控晶闸管的制造方法,结构示意图如图2,包括栅电极1、金属化阴极2、栅氧化层3、P+区4、P深阱5、N阱6、P阱7、N漂移区8、FS层9、P阳极区10、N阳极区11、金属化阳极12。P阱7位于漂移区8顶部,N阱6位于P阱7中,P深阱5位于N阱5中,P+区4位于漂移区8顶部靠近金属化阴极2一侧,栅氧化层3位于P深阱5、N阱6、P阱7、N漂移区8的表面,栅电极1位于栅氧化层3表面,金属化阴极2覆盖P深阱5和N阱6以及P+区4。N漂移区8的下表面设置有FS层9,FS层9下表面是P型阳极区10和N型阳极区11,金属化阳极12上部与N阳极区11和P型阳极区10接触。
本发明提出的一种逆导型MOS栅控晶闸管的制造方法,其栅极结构可设置为平面型栅或沟槽型栅,具有平面型栅的逆导型MOS栅控晶闸管元胞结构如图2所示,具有沟槽型栅的逆导型MOS栅控晶闸管元胞结构如图4所示。
由上可见,本发明逆导型MOS栅控晶闸管的制造方法的优点:在进行结终端场限环注入的同时,在元胞区注入形成P+区,与常规工艺流程相兼容,没有增加多余的工艺步骤,也对后续工艺没有影响。
本发明与常规的RC-MCT相比,通过增加P+区,等效增大了RC-MCT反向导通时的PN结P区的浓度,大大降低了RC-MCT的反向导通压降。
图14表示的是本制造方法的RC-MCT与常规RC-MCT器件反向导通特性曲线对比示意图。从图中可以看到,相较于常规结构,本制造方法制造的RC-MCT在电流密度为40000A/cm2时的反向导通电压降低了7.2V,下降了31%,此结果充分说明了本制造方法显著提升了器件的反向导通能力。
图15表示的是本制造方法的RC-MCT与常规RC-MCT器件正向导通特性曲线对比示意图。从图中可以看到,相较于常规结构,本制造方法制造的RC-MCT在电流密度为40000A/cm2时的正向导通电压只降低了1V,说明本发明的制造方法,在提高器件反向导通能力的同时,牺牲了一定的正向导通能力,但从总体来看,器件的性能还是有了较大的提升。

Claims (1)

1.一种逆导型MOS栅控晶闸管的制造方法,其特征在于,包括以下步骤:
第一步:选取N型硅片作为衬底硅片,即制备N-漂移区(8),在N-漂移区(8)背面通过离子注入N型杂质并推结形成N型FS层(9);
第二步:在N-漂移区(8)上层一端通过光刻离子注入P型杂质并推结形成P+区(4)和终端P型场限环;
第三步:在N-漂移区(8)上层另一端通过热氧化形成栅氧化层(3),并在栅氧化层(3)上淀积一层多晶硅/金属,通过刻蚀形成栅电极(1);
第四步:利用离子注入和高温推结工艺,在N-漂移区(8)上层注入P型杂质并推结形成P阱区(7),P阱区(7)一端的上表面与栅氧化层(3)底部接触,另一端与P+区(4)接触;
第五步:利用离子注入和高温推结工艺,在P阱区(7)上层注入N型杂质形成N阱区(6),N阱区(6)一端的上表面与栅氧化层(3)底部接触,另一端与P+区(4)接触;
第六步:利用离子注入和高温推结工艺,在N阱区(6)上层注入P型杂质形成P型深阱区(5),P型深阱区(5)一端的上表面与栅氧化层(3)底部接触;
第七步:在器件上表面淀积BPSG绝缘介质层,刻蚀欧姆接触孔;
第八步:在N-漂移区(8)上表面另一端淀积金属,形成阴极金属(2);阴极金属(2)的底部与P+区(4)、N阱区(6)、P型深阱区(5)另一端的上表面接触;
第九步:在器件表面淀积钝化层;
第十步:向背面N型FS层(9)下层一端通过光刻离子注入P型杂质并进行离子激活,形成P型阳极区(10);
第十一步:向背面N型FS层(9)下层另一端通过光刻离子注入N型杂质并进行离子激活,形成N型阳极区(11),N型阳极区(11)和P型阳极区(10)为并列设置并相互接触;
第十二步:在器件下表面进行金属淀积形成阳极(12)。
CN202210949239.8A 2022-08-09 2022-08-09 一种逆导型mos栅控晶闸管的制造方法 Pending CN115172165A (zh)

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