CN115148790A - Ultra-low parasitic capacitance bonding pad structure and manufacturing method - Google Patents
Ultra-low parasitic capacitance bonding pad structure and manufacturing method Download PDFInfo
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- CN115148790A CN115148790A CN202211068359.3A CN202211068359A CN115148790A CN 115148790 A CN115148790 A CN 115148790A CN 202211068359 A CN202211068359 A CN 202211068359A CN 115148790 A CN115148790 A CN 115148790A
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
The embodiment of the invention provides an ultra-low parasitic capacitance bonding pad structure, which comprises a substrate, wherein a groove array is arranged in a region corresponding to a bonding pad in the substrate, and an inner wall oxide layer and an air cavity surrounded by the inner wall oxide layer are arranged in each groove in the groove array; a thick oxidation layer is arranged above the substrate, a metal film is arranged above the thick oxidation layer, a passivation layer is arranged above the metal film, and a pad opening is carved at the position of the passivation layer corresponding to the pad to expose the pad. The embodiment of the invention also provides a manufacturing method of the ultra-low parasitic capacitance bonding pad structure. According to the invention, by utilizing the non-uniformity of oxygen flow during the oxidation of the deep groove, an air cavity is formed inside the deep and fine groove, and the parasitic capacitance below the metal of the integrated circuit bonding pad is greatly reduced by utilizing the internal gas medium.
Description
Technical Field
The invention belongs to the technical field of design and manufacture of semiconductor devices, and particularly relates to an ultra-low parasitic capacitance bonding pad structure and a manufacturing method thereof.
Background
The bonding pad (pad) is a necessary structure for leading out electrodes of an integrated circuit or a semiconductor device, but non-ideal parameters of the bonding pad can have a significant influence on the performance of the semiconductor device or the circuit; for example, in the field of low capacitance transient suppressors (TVS), the total capacitance of a single device is required to be within 0.5pF, and the parasitic capacitance of an individual pad can reach this magnitude, and as the frequency of an integrated circuit signal is higher and higher, the pad structure parasitic capacitance of the TVS will have a significant influence on the device performance; therefore, the pad parasitic capacitance must be reduced when designing the low capacitance TVS.
The traditional pad structure manufacturing process is shown in fig. 1, a thick oxide layer 6 is deposited on a substrate 1, a metal film 7 with a required thickness is deposited on the thick oxide layer 6, a passivation layer 8 is manufactured on the metal film 7, the passivation layer 8 in a corresponding area is etched through pad mask lithography to form a pad opening, a pad is exposed, and an external binding wire 9 is connected with the pad.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide an ultra-low parasitic capacitance bonding pad structure and a manufacturing method thereof. In order to achieve the technical purpose, the embodiment of the invention adopts the technical scheme that:
the embodiment of the invention provides an ultra-low parasitic capacitance bonding pad structure, which comprises a substrate, wherein a groove array is arranged in an area corresponding to a bonding pad in the substrate, and an inner wall oxide layer and an air cavity surrounded by the inner wall oxide layer are arranged in each groove in the groove array; a thick oxidation layer is arranged above the substrate, a metal film is arranged above the thick oxidation layer, a passivation layer is arranged above the metal film, and a pad opening is carved at the position of the passivation layer corresponding to the pad to expose the pad.
Furthermore, the groove depth of the groove array is 10-50 μm.
Furthermore, the groove depth of the groove array is 10-20 μm.
Further, the groove width of the groove array is 0.3-0.6 μm.
Furthermore, the groove width of the groove array is 0.4-0.5 μm.
Furthermore, the interval between the grooves of the groove array is 0.8-2 μm.
The embodiment of the invention also provides a manufacturing method of the ultra-low parasitic capacitance bonding pad structure, which comprises the following steps:
step S1, providing a substrate, wherein the substrate is an N-type substrate or a P-type substrate;
s2, etching a deep and thin groove array in a region of the substrate corresponding to the bonding pad through a groove mask;
s3, performing thermal oxidation on the substrate to form an inner wall oxide layer and a surface oxide layer; simultaneously forming an air cavity surrounded by the inner wall oxide layer in the groove of the groove array;
s4, performing CMP chemical mechanical planarization on the surface of the substrate to obtain a flat oxide layer;
s5, depositing an oxide layer with the required thickness on the flat oxide layer to obtain a thick oxide layer;
and S6, depositing a metal film on the thick oxide layer, growing a passivation layer on the metal film, and etching a pad opening at the position of the passivation layer corresponding to the pad to expose the pad.
Furthermore, the groove depth of the groove array is 10-50 μm, and the groove width is 0.3-0.6 μm.
Furthermore, the groove depth of the groove array is 10-20 μm, and the groove width is 0.4-0.5 μm.
Furthermore, the interval between the grooves of the groove array is 0.8-2 μm.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: according to the method, the air cavity is formed inside the deep and thin groove by utilizing the nonuniformity of oxygen flow during the oxidation of the deep groove, and the parasitic capacitance below the metal of the bonding pad of the integrated circuit is greatly reduced by utilizing the internal gas medium, so that the frequency performance of the circuit or the device is improved; the ultra-low parasitic capacitance bonding pad structure and the manufacturing method are particularly suitable for design and manufacture of a low capacitance transient suppressor (TVS) and a high-speed circuit.
Drawings
Fig. 1 is a schematic diagram of a conventional pad structure.
Fig. 2 is a schematic diagram of a pad structure in an embodiment of the invention.
FIG. 3a is a schematic view of a substrate in an embodiment of the invention.
Fig. 3b is a schematic diagram of the etched deep and thin trench array in the embodiment of the present invention.
FIG. 3c is a schematic diagram of forming an inner wall oxide layer and a surface oxide layer and a gas cavity by thermal oxidation according to an embodiment of the present invention.
FIG. 3d is a schematic illustration of CMP chemical mechanical planarization of the substrate surface in an embodiment of the present invention.
FIG. 3e is a schematic diagram of a thick oxide layer deposited according to an embodiment of the present invention.
Fig. 3f is a schematic diagram of manufacturing a metal film, a passivation layer and a pad opening in the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
As shown in fig. 2, in a first aspect, an embodiment of the present invention provides an ultra-low parasitic capacitance pad structure, including a substrate 1, a trench array 2 is disposed in a region corresponding to a pad inside the substrate 1, and an inner wall oxide layer 4 and an air cavity 10 surrounded by the inner wall oxide layer 4 are disposed in each trench in the trench array 2; a thick oxidation layer 6 is arranged above the substrate 1, a metal film 7 is arranged above the thick oxidation layer 6, a passivation layer 8 is arranged above the metal film 7, and a pad opening is carved on the passivation layer 8 corresponding to the pad to expose the pad; thereby enabling the external binding-wire 9 to be connected with the pad;
as the optimization of the embodiment, the groove depth of the groove array 2 is 10 μm to 50 μm; the optimal groove depth is 10-20 μm;
as optimization of the embodiment, the groove width of the groove array 2 is 0.3 μm to 0.6 μm; the optimal groove width is 0.4-0.5 μm;
as optimization of the embodiment, the interval between the trenches of the trench array 2 is 0.8 μm to 2 μm;
in a second aspect, an embodiment of the present invention further provides a method for manufacturing an ultra-low parasitic capacitance pad structure, including the following steps:
step S1, as shown in FIG. 3a, providing a substrate 1, wherein the substrate 1 is an N-type substrate or a P-type substrate;
step S2, as shown in FIG. 3b, etching a deep and thin groove array 2 in the region of the substrate 1 corresponding to the bonding pad through a groove mask;
the depth of the groove array 2 is 10-50 μm; the optimal groove depth is 10-20 μm; the groove width of the groove array 2 is 0.3-0.6 μm; the optimal groove width is 0.4-0.5 μm; the interval between the grooves of the groove array 2 is 0.8-2 μm;
step S3, as shown in fig. 3c, performing thermal oxidation on the substrate 1 to form an inner wall oxide layer 4 and a surface oxide layer 3; simultaneously forming an air cavity 10 surrounded by the inner wall oxide layer 4 in the groove of the groove array 2;
step S4, as shown in FIG. 3d, performing CMP chemical mechanical planarization on the surface of the substrate 1 to obtain a planar oxide layer 5;
step S5, as shown in FIG. 3e, depositing an oxide layer with a required thickness on the flat oxide layer 5 to obtain a thick oxide layer 6;
step S6, as shown in FIG. 3f, depositing a metal film 7 on the thick oxide layer 6, growing a passivation layer 8 on the metal film 7, and etching a pad opening at a position of the passivation layer 8 corresponding to the pad to expose the pad; thereby enabling the external binding-wire 9 to be connected with the pad;
in the step S3, during the thermal oxidation, the trench of the present application is a deep and thin trench instead of a conventional wider and shallower trench, so that the concentration and flow of oxygen introduced during the oxidation on the surface of the trench far exceed the inside of the trench; thus, the growth speed of the oxide layer on the surface of the deep and thin groove is far higher than that of the oxide layer inside and at the bottom of the deep and thin groove, and the result is that the groove is not filled with the oxide in the groove body when the surface oxide seals the whole groove, so that an air cavity is formed; the dielectric constant of the oxygen in the cavity is much less than that of the oxide layer, so that the parasitic capacitance of the pad will drop significantly in the same area when there are a large number of air cavity trenches under the metal.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (10)
1. An ultra-low parasitic capacitance pad structure comprising a substrate (1),
a groove array (2) is arranged in an area corresponding to the bonding pad in the substrate (1), and an inner wall oxide layer (4) and an air cavity (10) surrounded by the inner wall oxide layer (4) are arranged in each groove in the groove array (2); the upper portion of the substrate (1) is provided with a thick oxidation layer (6), a metal film (7) is arranged above the thick oxidation layer (6), a passivation layer (8) is arranged above the metal film (7), and a pad opening is carved at the position, corresponding to the pad, of the passivation layer (8) to expose the pad.
2. The ultra-low parasitic capacitance pad structure of claim 1,
the groove depth of the groove array (2) is 10-50 μm.
3. The ultra-low parasitic capacitance pad structure of claim 2,
the groove depth of the groove array (2) is 10-20 mu m.
4. The ultra-low parasitic capacitance pad structure of claim 1,
the groove width of the groove array (2) is 0.3-0.6 μm.
5. The ultra-low parasitic capacitance pad structure of claim 4,
the groove width of the groove array (2) is 0.4-0.5 μm.
6. The ultra-low parasitic capacitance pad structure of claim 1,
the interval between the grooves of the groove array (2) is 0.8-2 mu m.
7. A manufacturing method of an ultra-low parasitic capacitance bonding pad structure is characterized by comprising the following steps:
step S1, providing a substrate (1), wherein the substrate (1) is an N-type substrate or a P-type substrate;
s2, etching a deep and thin groove array (2) in a region of the substrate (1) corresponding to the bonding pad through a groove mask;
s3, performing thermal oxidation on the substrate (1) to form an inner wall oxide layer (4) and a surface oxide layer (3); simultaneously forming an air cavity (10) surrounded by the inner wall oxide layer (4) in the groove of the groove array (2);
s4, carrying out CMP chemical mechanical planarization on the surface of the substrate (1) to obtain a flat oxide layer (5);
s5, depositing an oxide layer with the required thickness on the flat oxide layer (5) to obtain a thick oxide layer (6);
and S6, depositing a metal film (7) on the thick oxide layer (6), growing a passivation layer (8) on the metal film (7), and etching a bonding pad opening at the position of the passivation layer (8) corresponding to the bonding pad to expose the bonding pad.
8. The method of claim 7, wherein the step of forming the ultra low parasitic capacitance pad structure comprises the steps of,
the groove depth of the groove array (2) is 10-50 μm, and the groove width is 0.3-0.6 μm.
9. The method of claim 7, wherein the step of forming the ultra low parasitic capacitance pad structure comprises the steps of,
the groove depth of the groove array (2) is 10-20 μm, and the groove width is 0.4-0.5 μm.
10. The method of claim 7, wherein the step of forming the ultra low parasitic capacitance pad structure comprises the steps of,
the interval between the grooves of the groove array (2) is 0.8-2 mu m.
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| CN202211068359.3A CN115148790B (en) | 2022-09-02 | 2022-09-02 | Ultra-low parasitic capacitance bonding pad structure and manufacturing method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456612A (en) * | 2010-10-27 | 2012-05-16 | 上海华虹Nec电子有限公司 | Manufacturing method and structure of semiconductor integrated inductor |
| WO2012089980A1 (en) * | 2010-12-31 | 2012-07-05 | Stmicroelectronics (Crolles 2) Sas | Insulated via hole |
| CN110707068A (en) * | 2019-09-09 | 2020-01-17 | 长江存储科技有限责任公司 | Semiconductor interconnection structure and preparation method thereof |
| CN114284233A (en) * | 2020-09-17 | 2022-04-05 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
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- 2022-09-02 CN CN202211068359.3A patent/CN115148790B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456612A (en) * | 2010-10-27 | 2012-05-16 | 上海华虹Nec电子有限公司 | Manufacturing method and structure of semiconductor integrated inductor |
| WO2012089980A1 (en) * | 2010-12-31 | 2012-07-05 | Stmicroelectronics (Crolles 2) Sas | Insulated via hole |
| CN110707068A (en) * | 2019-09-09 | 2020-01-17 | 长江存储科技有限责任公司 | Semiconductor interconnection structure and preparation method thereof |
| CN114284233A (en) * | 2020-09-17 | 2022-04-05 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
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