CN117524882A - Manufacturing process of semiconductor device and semiconductor device - Google Patents

Manufacturing process of semiconductor device and semiconductor device Download PDF

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Publication number
CN117524882A
CN117524882A CN202311690107.9A CN202311690107A CN117524882A CN 117524882 A CN117524882 A CN 117524882A CN 202311690107 A CN202311690107 A CN 202311690107A CN 117524882 A CN117524882 A CN 117524882A
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China
Prior art keywords
silicon wafer
layer
silicon
fin
region
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Pending
Application number
CN202311690107.9A
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Chinese (zh)
Inventor
苏炳熏
吕昆谚
叶甜春
罗军
赵杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Greater Bay Area Institute of Integrated Circuit and System
Ruili Flat Core Microelectronics Guangzhou Co Ltd
Original Assignee
Guangdong Greater Bay Area Institute of Integrated Circuit and System
Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Application filed by Guangdong Greater Bay Area Institute of Integrated Circuit and System, Ruili Flat Core Microelectronics Guangzhou Co Ltd filed Critical Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority to CN202311690107.9A priority Critical patent/CN117524882A/en
Publication of CN117524882A publication Critical patent/CN117524882A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention relates to the technical field of semiconductors, and discloses a manufacturing process of a semiconductor device and the semiconductor device.

Description

Manufacturing process of semiconductor device and semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing process of a semiconductor device and the semiconductor device.
Background
Wafers are the basic raw material for manufacturing semiconductor devices. The semiconductor with extremely high purity is prepared into a wafer through procedures such as crystal pulling, slicing and the like, the wafer forms an extremely tiny circuit structure through a series of semiconductor manufacturing processes, and the wafer is cut, packaged and tested to form a chip, so that the chip is widely applied to various electronic equipment.
The wafers can be classified into SOI wafers and Si wafers according to different manufacturing processes, and devices manufactured on the SOI wafers are SOI devices. The SOI wafer realizes the full-medium isolation of the device and the substrate through the insulating buried layer, compared with the Si wafer, the SOI wafer reduces parasitic capacitance, improves the operation speed, reduces electric leakage due to the reduction of the parasitic capacitance, has lower power consumption, eliminates the locking effect, inhibits the pulse current interference of the substrate, and reduces the occurrence of soft errors. The manufacturing cost of SOI wafers is relatively higher. The current methods for forming SOI wafers include deep injection of oxygen or nitrogen into the silicon substrate, laser (or electron beam, infrared, etc.) annealing recrystallization of polysilicon on silicon dioxide, heated recrystallization of graphite strips of polysilicon on silicon dioxide, porous silicon oxidation, lateral epitaxy of silicon, silicon wafer bonding, thinning, etc.
Disclosure of Invention
In view of the shortcomings of the background art, the invention provides a manufacturing process of a semiconductor device and the semiconductor device, which can manufacture an SOI device on a Si wafer and reduce the manufacturing cost of the SOI device.
In order to solve the technical problems, the invention provides the following technical scheme: a process for manufacturing a semiconductor device, comprising the steps of:
s1: the substrate is manufactured as follows: thinning the top of the silicon wafer from top to bottom at a first area, and sequentially growing an epitaxial layer and a semiconductor layer on the thinned silicon wafer;
s2: fabricating a fin on the semiconductor layer and at a second region on top of the silicon wafer;
s3: forming an isolation trench in the silicon wafer top, the isolation trench being configured to isolate a fin on the semiconductor layer from a fin at a second region of the silicon wafer top;
s4: depositing an oxide layer on the upper surface of the substrate;
s5: manufacturing a layer of mask plate at a second area on the top of the silicon wafer, wherein the mask plate covers the fins at the second area;
s6: etching the oxide layer at the first area on the top of the silicon wafer, and only keeping the oxide layer on the surface of the fin at the first area;
s7: removing the mask plate;
s8: depositing a second oxide layer on top of the substrate;
s9: and etching the second oxide layer to expose the fins on the semiconductor layer and the fins at the second area on the top of the silicon wafer to the outside.
In some embodiments, the epitaxial layer is a SiGe layer and the semiconductor layer is a silicon layer.
In some embodiments, the upper surface of the semiconductor layer is flush with the upper surface of the silicon wafer.
In one embodiment, the first and second regions of the top of the silicon wafer are disposed adjacent to each other, and the isolation trench is located on the first and second regions of the top of the silicon wafer, respectively.
In an embodiment, step S3 further includes removing the excess fin on the semiconductor layer, removing the excess fin on the second substrate, and removing the excess fin on the second region.
The utility model provides a semiconductor device, includes the silicon wafer, isolation trench has been seted up at the top of silicon wafer, the top of silicon wafer is in isolation trench one side is equipped with the epitaxial layer, be equipped with at least one silicon fin passageway on the epitaxial layer, the top of silicon wafer is in isolation trench opposite side is equipped with at least one silicon fin passageway, isolation trench is used for with silicon fin passageway on the epitaxial layer with the top of silicon wafer is in isolation trench opposite side's silicon fin passageway, the top of silicon wafer still is equipped with the oxide layer, the upper surface of oxide layer highly be less than the height of the upper surface of silicon fin passageway.
Compared with the prior art, the invention has the following beneficial effects: by manufacturing the epitaxial layer and the semiconductor layer on the silicon wafer, the SOI device can be manufactured on one silicon wafer, the SOI device is not required to be manufactured on the SOI wafer, and the manufacturing cost of the SOI device is reduced; in addition, the semiconductor manufacturing process integrates the manufacturing process of the SOI FinFET and the manufacturing process of the bulk silicon FinFET, the SOI FinFET and the bulk silicon FinFET can be manufactured on the silicon wafer at the same time, the manufacturing process has higher manufacturing compatibility, and compared with the manufacturing process of the SOI wafer, the manufacturing process of the bulk silicon FinFET has better cost advantage due to the adoption of the silicon wafer.
Drawings
FIG. 1 is a schematic view of a substrate of the present invention;
FIG. 2 is a schematic diagram of a fabricated fin on the substrate of FIG. 1;
fig. 3 is a schematic diagram of the structure of the isolation trench and the removal of the excess fin based on fig. 2;
FIG. 4 is a schematic diagram of an oxide layer formed on the basis of FIG. 3;
FIG. 5 is a schematic view of the structure of the second region of FIG. 4 after a reticle is fabricated thereon;
FIG. 6 is a schematic diagram of the structure of the oxide layer etched in the first substrate region in the structure of FIG. 5;
FIG. 7 is a schematic illustration of the reticle of FIG. 6 removed;
FIG. 8 is a schematic diagram of a structure for forming a second oxide layer over the structure of FIG. 7;
FIG. 9 is a schematic diagram of a structure for fabricating a silicon fin channel over the structure of FIG. 8;
fig. 10 is a flow chart of the present invention.
Detailed Description
Illustrative embodiments of the present application include, but are not limited to, a semiconductor device manufacturing process, a semiconductor device, and a substrate.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The term "if" as used herein may be interpreted as "at..once" or "when..once" or "in response to a determination", depending on the context.
As shown in fig. 10, a manufacturing process of a semiconductor device includes the steps of:
s1: the substrate is manufactured as follows: thinning the top of the silicon wafer 1 from top to bottom at a first area, and sequentially growing an epitaxial layer 3 and a semiconductor layer 2 on the thinned silicon wafer 1;
s2: fabricating a fin 4 on the semiconductor layer 2 and at a second region on top of the silicon wafer 1;
referring to fig. 1, in fig. 1, a region corresponding to an SOI region is a first region, a region corresponding to bulk silicon is a second region, a schematic structure diagram of a thinned silicon wafer 1 at the first region refers to an intermediate diagram in fig. 1, and a schematic structure diagram of a thinned silicon wafer 1 after sequentially growing an epitaxial layer 3 and a semiconductor layer 2 thereon refers to a right diagram in fig. 1;
as can be taken from fig. 1, in this embodiment, the epitaxial layer 3 is a SiGe layer and the semiconductor layer 2 is a silicon layer. In practical use, the epitaxial layer 3 may be GaAs, gaP, gaN, siC, or the like, and the semiconductor layer 2 may be Ge, or the like.
As can be taken from fig. 1, in the present embodiment, the upper surface of the semiconductor layer 2 is flush with the upper surface of the silicon wafer 1.
Specifically, step S2 specifically includes the steps of: .
In the actual production process, the positions, the heights and the widths of the fins 4 on the semiconductor layer 3 and the second area in step S20 may be determined according to the actual design layout, and are not particularly limited herein, and in addition, in the actual production process, the fins 4 on the semiconductor layer 3 and the second substrate 11 may have auxiliary fins in addition to the fins 4 actually required, and the resolution of the fins 4 on the design layout may be increased by the auxiliary fins.
S3: forming an isolation trench 5 on top of the silicon wafer 1, the isolation trench 5 being arranged to isolate the fin 4 on the semiconductor layer 3 from the fin 4 at the second region on top of the silicon wafer 1;
referring to fig. 1, in the present embodiment, a first region and a second region on top of a silicon wafer 1 are disposed adjacently, that is, an epitaxial layer 3 and a semiconductor layer 2 have contact surfaces with the silicon wafer 1 at the second region, respectively. Referring to fig. 3, in order to isolate the fin 4 on the upper semiconductor layer 3 from the fin 4 at the second region on top of the silicon wafer 1, an isolation trench 5 is opened between the first region and the second region on top of the silicon wafer 1, i.e., on the first region and the second region of the silicon wafer 1, respectively. The isolation trenches 5 extend further downwards than the bottom of the epitaxial layer 2. In some embodiments, the first region and the second region on top of the silicon wafer 1 may not be disposed adjacently.
Specifically, in step S3, photoresist may be coated on the upper surface of the structure of fig. 2, then the position of the isolation trench 5 is determined by exposure and development processes, and finally etching is performed at the position of the isolation trench 5 until the shape and depth of the isolation trench meet the requirements.
In addition, when the auxiliary fin is present on the semiconductor layer 3 and the fin 4 on the second region on top of the silicon wafer, the auxiliary fin is also removed from the semiconductor layer 3 and the second region in step S3. Referring to fig. 2 and 3, the leftmost and rightmost fins on the semiconductor layer 3 and the leftmost and rightmost fins on the second region on top of the silicon wafer 1 are auxiliary fins, respectively, so the auxiliary fins in fig. 2 are removed in step S3.
S4: depositing an oxide layer 6 on the upper surface of the substrate; the schematic structure of the deposited oxide layer 6 is shown in fig. 4;
in actual use, an oxide layer 6 is manufactured on the surface of the substrate by an atomic layer deposition technology, namely an ALD technology, and the thickness of the oxide layer 6 can be uniform by the atomic layer deposition technology;
s5: a layer of mask 7 is manufactured at a second area on the top of the silicon wafer 1, and the mask 7 covers the fins 4 at the second area; a schematic structural diagram of the mask 7 after fabrication is shown in fig. 5;
s6: etching the oxide layer 6 at the first region on top of the silicon wafer 1, leaving only the oxide layer on the surface of the fin 4 at the first region; the structure of the etched oxide layer 6 is schematically shown in fig. 6;
in actual use, since the mask 7 has been fabricated at the second region in step S5, the oxide layer at the second region on top of the silicon wafer 1 can be left unetched off by the mask 7 in step S6. In addition, since the top area of the silicon wafer 1 in the embodiment is divided into the first area and the second area, the mask 7 is fabricated only at the second area on the top of the silicon wafer 1 in step S5, and when there are other areas on the silicon wafer 1 besides the first area and the second area, the mask 7 can be fabricated at the other areas on the top of the silicon wafer 1 according to the actual requirement to protect the oxide layer 6 of the area from being etched in step S6.
Specifically, in step S6, the epitaxial layer 3 may be exposed by etching the oxide layer 6 at the first region on top of the silicon wafer 1.
S7: removing the mask 7, wherein the structure schematic diagram of the mask 7 after removal is shown in fig. 7;
in actual use, the reticle 7 may be removed by a dry or wet process.
S8: depositing a second oxide layer 8 on top of the substrate; a schematic structural diagram of the second oxide layer 8 after deposition is shown in fig. 8;
specifically, step S8 includes the steps of:
s9: etching the second oxide layer 8 to expose the fin 4 on the semiconductor layer 3 and the fin 4 at the second region on top of the silicon wafer 1 to the outside; a schematic structure of the second oxide layer 8 after etching is completed is shown in fig. 9;
in actual use, in step S9, the second oxide layer 8 is etched by an etching process. The fin body 40 is exposed by etching the oxide layer 8.
In practical use, the manufacturing process of the semiconductor device can manufacture the SOI device on one silicon wafer 1 by manufacturing the epitaxial layer 3 and the semiconductor layer 2 on the silicon wafer 1, so that the SOI device is not required to be manufactured on the SOI wafer, and the manufacturing cost of the SOI device is reduced; in addition, the manufacturing process of the semiconductor device integrates the manufacturing process of the SOI FinFET and the manufacturing process of the bulk silicon FinFET, the SOI FinFET and the bulk silicon FinFET can be manufactured on the silicon wafer 2 at the same time, the manufacturing process has higher process compatibility, and compared with the manufacturing process of the SOI wafer, the manufacturing process of the semiconductor device has better cost advantage due to the adoption of the silicon wafer.
Through step S1 of the manufacturing process of the semiconductor device of the present invention, a substrate in which an SOI finFET and a bulk silicon finFET can be manufactured simultaneously can be manufactured.
A substrate comprises a silicon wafer 1, wherein a semiconductor layer 3 and an epitaxial layer 2 are sequentially arranged at a first area of the top of the silicon wafer 1 from top to bottom. A schematic structural diagram of the substrate can be referred to fig. 1. The substrate can be used for manufacturing the SOI device on the silicon wafer, and the SOI device can be manufactured on the SOI wafer, so that the manufacturing cost of the SOI device is reduced.
In a certain embodiment, the epitaxial layer 2 is a SiGe layer and the semiconductor layer 3 is a silicon layer.
The utility model provides a semiconductor device, including silicon wafer 1, isolation trench 5 has been seted up at the top of silicon wafer 1, the top of silicon wafer 1 is equipped with epitaxial layer 3 in isolation trench one side, be equipped with at least one silicon fin passageway 9 on the epitaxial layer 3, the top of silicon wafer 1 is equipped with at least one silicon fin passageway 9 at isolation trench 5 opposite side, isolation trench 5 is used for keeping apart the silicon fin passageway 9 on epitaxial layer 3 and the silicon fin passageway 9 of silicon wafer 1's top at isolation trench 5 opposite side, the top of silicon wafer 1 still is equipped with the oxide layer, the height of the upper surface of oxide layer is less than the height of the upper surface of silicon fin passageway 9. Schematic structural diagram of semiconductor device referring to fig. 9, the second oxide layer 8 in fig. 9 is an oxide layer in the semiconductor device.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (6)

1. A manufacturing process of a semiconductor device, comprising the steps of:
s1: the substrate is manufactured as follows: thinning the top of the silicon wafer from top to bottom at a first area, and sequentially growing an epitaxial layer and a semiconductor layer on the thinned silicon wafer;
s2: fabricating a fin on the semiconductor layer and at a second region on top of the silicon wafer;
s3: forming an isolation trench in the silicon wafer top, the isolation trench being configured to isolate a fin on the semiconductor layer from a fin at a second region of the silicon wafer top;
s4: depositing an oxide layer on the upper surface of the substrate;
s5: manufacturing a layer of mask plate at a second area on the top of the silicon wafer, wherein the mask plate covers the fins at the second area;
s6: etching the oxide layer at the first area on the top of the silicon wafer, and only keeping the oxide layer on the surface of the fin at the first area;
s7: removing the mask plate;
s8: depositing a second oxide layer on top of the substrate;
s9: and etching the second oxide layer to expose the fins on the semiconductor layer and the fins at the second area on the top of the silicon wafer to the outside.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is a SiGe layer and the semiconductor layer is a silicon layer.
3. The method of manufacturing a semiconductor device according to claim 1, wherein an upper surface of the semiconductor layer is flush with an upper surface of the silicon wafer.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the first region and the second region of the top of the silicon wafer are disposed adjacently, and the isolation trench is located on the first region and the second region of the top of the silicon wafer, respectively.
5. The method of claim 1, wherein step S3 further comprises removing excess fin from the semiconductor layer and removing excess fin from the second region.
6. The semiconductor device is characterized by comprising a silicon wafer, wherein an isolation groove is formed in the top of the silicon wafer, an epitaxial layer is arranged on one side of the isolation groove on the top of the silicon wafer, at least one silicon fin channel is arranged on the epitaxial layer, at least one silicon fin channel is arranged on the other side of the isolation groove on the top of the silicon wafer, the isolation groove is used for isolating the silicon fin channel on the epitaxial layer from the silicon fin channel on the other side of the isolation groove on the top of the silicon wafer, an oxide layer is further arranged on the top of the silicon wafer, and the height of the upper surface of the oxide layer is lower than that of the upper surface of the silicon fin channel.
CN202311690107.9A 2023-12-08 2023-12-08 Manufacturing process of semiconductor device and semiconductor device Pending CN117524882A (en)

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