CN115101021A

CN115101021A - Circuit for selecting charge sharing mode, TCON and display equipment

Info

Publication number: CN115101021A
Application number: CN202210742947.4A
Authority: CN
Inventors: 张好聪; 马柯; 李年
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2022-09-23
Anticipated expiration: 2042-06-27
Also published as: CN115101021B

Abstract

The invention discloses a circuit for selecting a charge sharing mode, a TCON and a display device, wherein when a display picture is switched, a summing module calculates a sub-pixel summation value of a sub-pixel which does not participate in charge sharing in a previous display line in a current frame aiming at each preset charge sharing mode, calculates an absolute value of a difference value of a positive sub-pixel and a negative sub-pixel, calculates a total summation value of the sub-pixel summation value and the absolute value of the difference value, a minimum value determining module selects a minimum total summation value, outputs the minimum summation value and an identifier corresponding to the minimum summation value to a source electrode driving circuit, and the source electrode driving circuit controls enabling of a target charge sharing mode according to the identifier so as to realize charge sharing of the previous display line and the current display line. Since the target charge sharing mode is selected according to the sub-pixel value of the sub-pixel not participating in charge sharing, the sub-pixel value of the positive sub-pixel, and the sub-pixel value of the negative sub-pixel, the charge sharing requirement in dynamic display of the display panel can be met and power consumption can be reduced compared with the case of using a single charge sharing mode.

Description

Circuit for selecting charge sharing mode, TCON and display equipment

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to a circuit for selecting a charge sharing mode, a TCON and display equipment.

Background

A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is a Display panel that is widely used at present, improves image quality using a TFT technology, and a driving circuit in the TFT-LCD is particularly important as a representative of an active matrix Liquid Crystal Display.

A timing control circuit (TCON) is a core circuit for controlling the timing of a display panel, and controls when a scan driving circuit is activated, and provides information required for charge sharing to a Source Driver (Source Driver) circuit of a TFT-LCD, and the charge sharing circuit is an important part of the structure of the Source Driver circuit.

However, the charge sharing mode provided by the conventional TCON is single, and in the actual driving process, the gray scale voltage difference of the positive and negative polarities under the high frequency action is large, the dynamic power consumption of the driving circuit is large, and the single charge sharing mode cannot meet the purpose of reducing the power consumption.

Disclosure of Invention

The invention provides a circuit for selecting a charge sharing mode, a TCON and a TFT-LCD display panel, which are used for solving the problem that the power consumption cannot be reduced by using a single charge sharing mode in the prior art.

In a first aspect, an embodiment of the present invention provides a charge sharing circuit applied to a display device, including:

a summing module, configured to calculate, for each preset charge sharing mode and each display line in the current frame image, a sub-pixel sum of sub-pixels in a previous display line that do not participate in charge sharing in the preset charge sharing mode, calculate an absolute value of a difference between a positive sub-pixel and a negative sub-pixel in the previous display line, and calculate a total sum of the sub-pixel sum and the absolute value of the difference;

and the minimum value determining module is used for selecting a minimum total sum value from total sum values corresponding to a plurality of preset charge sharing modes, and outputting the minimum total sum value and an identifier corresponding to the minimum total sum value to a source driving circuit of the display device, so that the source driving circuit controls enabling of a target charge sharing mode according to the identifier, and the previous display line and the current display line are subjected to charge sharing.

In one possible implementation, the summing module includes a first computing unit, a second computing unit, and a total computing unit;

the first calculating unit is used for selecting a first sub-pixel which does not participate in charge sharing from the last display line according to the preset charge sharing mode, and calculating a sub-pixel sum value of a plurality of first sub-pixels;

the second calculation unit is used for selecting positive sub-pixels and negative sub-pixels from the previous display line, calculating positive sub-pixel accumulated values of all the positive sub-pixels and negative sub-pixel accumulated values of all the negative sub-pixels, and calculating absolute values of differences of the positive sub-pixel accumulated values and the negative sub-pixel accumulated values, wherein the positive sub-pixels are second sub-pixels with positive pixel electrodes, and the negative sub-pixels are second sub-pixels with negative pixel electrodes;

and the total calculating unit is used for calculating the total sum value of the sub-pixel sum value and the absolute value of the difference value.

In a possible implementation manner, the device further comprises a comparison module;

the comparison module is configured to compare the minimum sum total value with a preset threshold, and send the comparison result to the source driving circuit, so that the source driving circuit controls enabling of the target charge sharing mode according to the identifier.

In one possible implementation, the comparison module includes a third comparator;

the first input end of the third comparator is used for inputting the minimum total sum value and the identifier corresponding to the minimum total sum value, the second input end of the third comparator is used for inputting the preset threshold, and the output end of the third comparator is used for outputting the comparison result.

In a possible implementation, the first calculation unit includes a first selector, a second selector, and a first adder;

the input end of the first selector is used for inputting the shared value stored in the mode register, the control end of the first selector is connected with the first output end of the counter, and the output end of the first selector is connected with the control end of the second selector and used for outputting the shared value stored in the mode register under the control of the first count value output by the counter;

the input end of the second selector is used for inputting sub-pixel values in a plurality of first preset combinations, and the output end of the second selector is connected with the first input end of the first adder and is used for selecting one preset combination from the plurality of first preset combinations to be output according to the input shared value, wherein the first preset combination is a combination determined according to the sub-pixel value in each pixel unit in the previous display row;

and the output end of the first adder is connected with the second input end of the first adder and is used for accumulating the input sub-pixel values and outputting the sub-pixel sum value.

In a possible implementation manner, the second calculation unit includes a third selector, a fourth selector, a fifth selector, a second adder, a third adder, a first comparator, and a subtractor;

the input end of the third selector is used for inputting the polarity value stored in the polarity register, the control end of the third selector is connected with the second output end of the counter, and the output end of the third selector is connected with the control end of the fourth selector and used for outputting the polarity value stored in the polarity register under the control of a second count value output by the counter;

an input end of the fourth selector is configured to input a sub-pixel value in a second preset combination, a first output end of the fourth selector is connected to the first input end of the second adder, and a second output end of the fourth selector is connected to the first input end of the third adder, and is configured to select a second preset combination from the plurality of second preset combinations according to the input polarity value, and output a positive sub-pixel value and a negative sub-pixel value according to the sub-pixel value in the selected second preset combination, where the second preset combination is a combination determined according to the sub-pixel value in each pixel unit in the previous display row;

the output end of the second adder is connected with the second input end of the second adder, the first input end of the first comparator and the first input end of the subtracter, and is used for outputting the positive sub-pixel accumulated value;

the output end of the third adder is connected with the second input end of the third adder, the second input end of the first comparator and the second input end of the subtracter, and is used for outputting the negative sub-pixel accumulated value;

the output end of the first comparator is connected with the control end of the fifth selector and is used for comparing the positive sub-pixel accumulated value with the negative sub-pixel accumulated value and outputting a comparison result;

a first output end of the subtractor is connected with a first input end of the fifth selector and is used for outputting a first difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value, and a second output end of the subtractor is connected with a second input end of the fifth selector and is used for outputting a second difference value of the negative sub-pixel accumulated value and the positive sub-pixel accumulated value;

and the fifth selector is used for outputting the absolute value of the difference under the control of the comparison result. In one possible implementation, the total calculation unit includes a fourth adder;

a first input terminal of the fourth adder is configured to input the sub-pixel sum, a second input terminal of the fourth adder is configured to input an absolute value of the difference, and an output terminal of the fourth adder is configured to output the total sum.

In one possible implementation, the minimum determination module includes a plurality of second comparators;

the input end of the first-stage second comparator is used for inputting a total sum value corresponding to each preset charge sharing mode and an identifier corresponding to the total sum value, and the output end of the previous-stage second comparator is connected with the input end of the next-stage second comparator;

each second comparator is used for comparing the input total sum value pairwise to obtain a comparison result, wherein the comparison result output by the output end of the last-stage second comparator is the minimum total sum value and the identifier corresponding to the minimum total sum value.

In a second aspect, an embodiment of the present invention provides a timing controller TCON, including the circuit for selecting a charge sharing mode according to any one of the first aspect.

In a third aspect, embodiments of the present invention provide a display device, including the timing controller TCON according to the second aspect.

The invention has the following beneficial effects:

the embodiment of the invention provides a circuit for selecting a charge sharing mode, a TCON and a display device, when the display picture is switched, the summation module is used for calculating the sub-pixel summation value of the sub-pixels which do not participate in charge sharing in the previous display line aiming at each preset charge sharing mode and each display line in the current frame image, and calculating absolute values of differences between the positive and negative sub-pixels in the last display line and calculating a sum of the sub-pixels and the absolute value of the difference, the minimum determination module being adapted to select a minimum sum from the sums corresponding to the plurality of predefined charge sharing modes, and transmits the minimum sum total value and the flag corresponding thereto to the source driving circuit of the display device, and enabling the source electrode driving circuit to control the target charge sharing mode to enable according to the identification, and enabling the last display line and the current display line to carry out charge sharing. According to the invention, the target charge sharing mode can be selected from a plurality of preset charge sharing modes according to the pixel value of the sub-pixel which does not participate in charge sharing in each preset charge sharing mode and the absolute value of the difference value of the positive sub-pixel and the negative sub-pixel in each display line in the current frame image, and the target charge sharing mode is used for carrying out charge sharing on the previous display line and the current display line.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a driving circuit of a TFT-LCD according to the related art;

FIG. 2 is a schematic diagram of a TCON structure according to the related art;

FIG. 3 is a schematic diagram of a Source Driver circuit in the related art;

FIG. 4 is a schematic diagram illustrating polarity inversion of gray scale voltages according to the related art;

FIG. 5 is a schematic diagram of a charge sharing switch according to the related art;

FIG. 6 is a diagram illustrating a charge sharing state of a point inversion driving scheme according to the related art;

FIG. 7 is a schematic diagram of a circuit for selecting a charge sharing mode according to an embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating an arrangement of sub-pixels in a TFT-LCD panel according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a summing module according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating an arrangement of sub-pixels in another TFT-LCD panel according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a first computing unit according to an embodiment of the present invention;

FIG. 12 is a diagram illustrating a first predetermined combination according to an embodiment of the present invention;

FIG. 13 is a diagram illustrating a storage relationship between a subpixel and a mode register according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a second computing unit according to an embodiment of the present invention;

FIG. 15 is a diagram illustrating a second predetermined combination according to an embodiment of the present invention;

FIG. 16 is a diagram illustrating a storage relationship between a sub-pixel and a polarity register according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a total computing unit according to an embodiment of the present invention;

fig. 18 is a schematic structural diagram of a minimum value determining module according to an embodiment of the present invention;

FIG. 19 is a diagram illustrating a circuit for selecting a charge sharing mode according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of another minimum value determining module according to an embodiment of the present invention;

FIG. 21 is a circuit diagram of a comparison module according to an embodiment of the present invention;

FIG. 22 is a diagram illustrating a storage relationship between a sub-pixel and a mode register according to an embodiment of the present invention;

FIG. 23 is a diagram illustrating a storage relationship between a sub-pixel and a polarity register according to another embodiment of the present invention;

fig. 24 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, which is a schematic diagram of a driving circuit in a display device, the driving circuit includes a power circuit 101, a timing controller 102, a gray-scale circuit 103, a source driving circuit 104, a gate driving circuit 105, and a system interface 106.

Signals from the system are supplied to the drive circuit via the system interface 106 with various display data and timing control signals, and a part of these data and signals is transmitted to the power supply circuit 101, and the other part is transmitted to the timing controller 102. The power supply circuit 101 receives data and signals from the system interface 106, and generates voltages (an operating voltage 1, an operating voltage 2, and an operating voltage 3) necessary for the operations of other circuits, and a liquid crystal deflection reference voltage Vcom; the timing controller 102 receives data and signals from the system interface 106, and generates timing control signals (timing control signal 1 and timing control signal 2) that control the operation timings of the source driving circuit 104, the gate driving circuit 105, and other circuits (not shown in fig. 1) in the display device. The gate driving circuit 105 is used to generate high and low level digital voltages, output the voltages to the gates of the TFT switches, and control the switching state of each row of pixels.

When the gate driving circuit 105 turns on the tfts of the lcd panel row by row, the source driving circuit 104 converts the signals from the timing controller 102 related to the display data into analog voltages to charge the liquid crystal capacitors Clc and the storage capacitors Cs on the lcd panel to desired gray scale voltages.

The timing controller 102 is a core circuit for controlling timing in the display device, and is used for controlling when the gate driving circuit 105 and the source driving circuit 104 are activated. As shown in fig. 2, the timing controller 102 converts the image data signals (VX1/eDP/LVDS) received through the system interface 106 into the timing control signal 1 and the timing control signal 2 to provide the gate driving circuit 105 and the source driving circuit 104 with the required control signals and levels, so that the lcd panel of the display device can display correctly. Meanwhile, the liquid crystal display panel comprises various image processing circuit modules (not shown in figures 1 and 2) aiming at the liquid crystal display panel, so as to improve the defects generated in the production of the display panel and existing in principle.

It should be noted that VX1 is also called V-by-One HS, which is a signal transmission interface standard suitable for flat panel displays. eDP (Embedded Display Port) is an internal digital interface based on the DisplayPort architecture and protocol. LVDS (Low-Voltage Differential Signaling) is a Differential Signaling technique with Low power consumption, Low error rate, Low crosstalk, and Low radiation.

The source driver circuit 104 supplies a signal to the source line after the TFT is turned on, and charges the pixel electrode to a corresponding gray scale voltage. The structure of the source driver circuit 104 is divided into two blocks, a digital portion and an analog portion, as shown in fig. 3. The digital part comprises a Bi-directional Shift Register (S/R) 301, an Input Register 302, a Data Register 303 and a Level Shifter (L/S) 304; the Analog section includes a Digital-to-Analog Converter (DAC) 305, an Output Buffer circuit (Output Buffer)306, and a Charge Sharing circuit (Charge Sharing) 307.

In the driving process of the TFT-LCD in the liquid crystal display panel, the difference value of positive and negative polarity gray scale voltages is large, the dynamic power consumption of the source electrode driving circuit 104 is large under the high-frequency action of hundreds of MHz, and the power consumption can be reduced by the charge sharing technology. In the high level period (high impedance state) of the STB shown in fig. 4 (which controls the output of the Data Latch signal and the Latch of the Input Register signal at the same time), before and after the polarity inversion of the gray-scale voltage on the connected odd-even channel, the connected channels are short-circuited by the charge sharing switch SW3, as shown in fig. 5. During this time, the gray scale voltages with positive and negative polarities in the previous frame image are respectively restored to near Vcom potential by neutralization. When the gray scale voltage of the next frame image is inverted, the gray scale voltage with positive and negative polarities only needs to be charged and discharged from the vicinity of the Vcom potential to the target voltage, namely, the voltage only needs to drive half of the amplitude value, the full swing is not needed, and the power consumption can be reduced.

In fig. 5, the switches SW1 and SW2 are charge switches, and when the switch SW1 is closed, the pixel electrode corresponding to the switch SW1 is charged, and when the switch SW2 is closed, the pixel electrode corresponding to the switch SW2 is charged.

As shown in fig. 6, the charge sharing state is a dot inversion driving method.

The conventional TCON provides a single charge sharing mode, which cannot satisfy the requirement of sufficiently reducing power consumption according to the real-time display state of the TFT-LCD display panel.

In view of the above problems, the present invention provides a circuit for selecting a charge sharing mode, applied to a display device, as shown in fig. 7, the circuit comprising: a summing module 61 and a minimum determination module 62;

a summing module 61 for calculating a sub-pixel sum value of sub-pixels in a previous display line that do not participate in charge sharing in the preset charge sharing mode, calculating an absolute value of a difference value of positive and negative sub-pixels in the previous display line, and calculating a total sum value of the sub-pixel sum value and the absolute value of the difference value, for each preset charge sharing mode and each display line in the current frame image;

and a minimum value determining module 62, configured to select a minimum total sum value from total sums corresponding to multiple preset charge sharing modes, and output the minimum total sum value and an identifier corresponding to the minimum total sum value to a source driving circuit of the display device, so that the source driving circuit controls enabling of the target charge sharing mode according to the identifier, and enables charge sharing between a previous display line and a current display line.

When the display picture is switched, the summation module is used for calculating the sub-pixel summation value of the sub-pixels which do not participate in charge sharing under the element and charge sharing mode in the previous display line and calculating the absolute value of the difference value between the positive sub-pixel summation value and the negative sub-pixel summation value and calculating the total summation value of the sub-pixel summation value and the absolute value of the difference value, wherein the positive sub-pixel summation value is the pixel summation value of the sub-pixels of which the pixel electrodes are positive in the previous display line, the negative sub-pixel summation value is the pixel summation value of the sub-pixels of which the pixel electrodes are negative in the previous display line, the minimum value determination module is used for selecting the minimum total summation value from the total summation values corresponding to a plurality of preset charge sharing modes and outputting the identification corresponding to the minimum total summation value to the source electrode driving circuit of the display device, and enabling the source electrode driving circuit to control the target charge sharing mode to enable according to the mark, and enabling the previous display line and the current display line to carry out charge sharing. According to the invention, the target charge sharing mode can be selected from a plurality of preset charge sharing modes according to the pixel value of the sub-pixel participating in charge sharing in each preset charge sharing mode and the pixel values of all the sub-pixels in the display line in each display line in the current frame image, and the target charge sharing mode is used for carrying out charge sharing on the previous display line and the current display line.

It should be noted that the number of the preset charge sharing modes in the embodiment of the present invention is multiple, and when the charge sharing mode is selected, one of the multiple preset charge sharing modes is selected as the target charge sharing mode.

As shown in fig. 8, a schematic diagram of an arrangement of sub-pixels in a TFT-LCD display panel in a display device is shown, where the TFT-LCD display panel includes 4 rows of sub-pixels, each row includes 6 sub-pixels, each 3 sub-pixels is a pixel unit, a data line, which may also be referred to as a source line, is arranged along a first direction, and a gate line is arranged along a second direction, a pixel electrode of a first sub-pixel of a first display row is positive, a pixel electrode of a second sub-pixel is negative, a pixel electrode of a third sub-pixel is positive, a pixel electrode of a fourth sub-pixel is negative, a pixel electrode of a fifth sub-pixel is positive, and a pixel electrode of a sixth sub-pixel is negative.

With reference to fig. 8, a charge sharing switch is disposed between two corresponding sub-pixels between two display rows, for example, a charge sharing switch is disposed between a first sub-pixel of a first display row and a first sub-pixel of a second display row, and when the first sub-pixel in the first display row and the first sub-pixel of the second display row need to perform charge sharing, the charge sharing switch is closed to implement charge sharing.

It should be noted that the charge sharing switch may be designed according to actual needs, for example, a charge sharing switch is disposed between the sub-pixels corresponding to each two adjacent display lines, and then the charge sharing switch that needs to be closed is selected according to the charge sharing mode, and for example, a charge sharing switch is disposed between the sub-pixels corresponding to the odd display line and the even display line, and then the charge sharing switch that needs to be closed is selected according to the charge sharing mode.

In the charge sharing mode, i.e., the mode in which the charge sharing switch is opened and closed in the embodiment of the present invention, for example, the charge sharing switch between the first subpixel of the first display row and the first subpixel of the second display row is the charge sharing switch 1, the charge sharing switch between the second subpixel of the first display row and the second subpixel of the second display row is the charge sharing switch 2, the charge sharing switch between the third subpixel of the first display row and the third subpixel of the second display row is the charge sharing switch 3, the charge sharing switch between the fourth subpixel of the first display row and the fourth subpixel of the second display row is the charge sharing switch 4, the charge sharing switch between the fifth subpixel of the first display row and the fifth subpixel of the second display row is the charge sharing switch 5, the charge sharing switch between the sixth subpixel of the first display row and the sixth subpixel of the second display row is the charge sharing switch 6, in the charge sharing mode 1, the charge sharing switch 2 and the charge sharing switch 4 are closed, and the charge sharing switch 3, the charge sharing switch 5 and the charge sharing switch 6 are opened; in the charge sharing mode 2, the charge sharing switch 1, the charge sharing switch 3, and the charge sharing switch 6 are closed, and the charge sharing switch 2, the charge sharing switch 4, and the charge sharing switch 5 are opened.

In a charge sharing mode, if the charge sharing switch is turned on, it means that the two sub-pixels corresponding to the charge sharing switch do not need to share charges, and if the charge sharing switch is turned off, it means that the two sub-pixels corresponding to the charge sharing switch need to share charges.

The circuit for selecting the charge sharing mode provided by the embodiment of the invention can be integrated in an intelligent Source Driver Control (Smart Source Driver Control) module in the TCON.

In a specific implementation, as shown in fig. 9, the summing module 61 provided in the embodiment of the present invention may include a first calculating unit 611, a second calculating unit 612, and a total calculating unit 613;

a first calculating unit 611, configured to select a first sub-pixel not participating in charge sharing from a previous display line according to a preset charge sharing mode, and calculate a sub-pixel sum value of the plurality of first sub-pixels;

a second calculating unit 612, configured to select a positive sub-pixel and a negative sub-pixel from the previous display row, calculate positive sub-pixel accumulated values of all positive sub-pixels and negative sub-pixel accumulated values of all negative sub-pixels, and calculate an absolute value of a difference value between the positive sub-pixel accumulated values and the negative sub-pixel accumulated values;

a total calculation unit 613 for calculating a total sum of the sub-pixel sum and the absolute value of the difference.

For example, as shown in fig. 10, the first display line is the previous display line, the preset charge sharing mode includes a charge sharing mode 1 and a charge sharing mode 2, in the charge sharing mode 1, the sub-pixel a +, the sub-pixel B-, and the sub-pixel D-participate in charge sharing, and the sub-pixel C +, the sub-pixel E +, and the sub-pixel F-do not participate in charge sharing, the first calculating unit selects the first sub-pixel that does not participate in charge sharing from the first display line, that is, the sub-pixel C +, the sub-pixel E +, and the sub-pixel F-, and calculates the sub-pixel sum value of the sub-pixel C +, the sub-pixel E +, and the sub-pixel F-according to the charge sharing mode 1; the second calculating unit selects the sub-pixel with positive polarity and the sub-pixel with negative polarity according to the polarity of the sub-pixels in the first display line, and the sub-pixel with positive polarity is as follows: the sub-pixel a +, the sub-pixel C +, and the sub-pixel E +, which has negative polarity, is: and accumulating the sub-pixel value of the sub-pixel A +, the sub-pixel value of the sub-pixel C + and the sub-pixel value of the sub-pixel E + to obtain a positive sub-pixel accumulated value, accumulating the sub-pixel value of the sub-pixel B-, the sub-pixel of the sub-pixel D-and the sub-pixel of the sub-pixel F-to obtain a negative sub-pixel accumulated value, and then calculating the absolute value of the difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value.

In the charge sharing mode 2, the sub-pixel A +, the sub-pixel C + and the sub-pixel F-participate in charge sharing, and the sub-pixel B-, the sub-pixel D-and the sub-pixel E + do not participate in charge sharing, then the first calculating unit selects the first sub-pixel which does not participate in charge sharing, namely the sub-pixel B-, the sub-pixel D-and the sub-pixel E + from the first display line according to the charge sharing mode 2, and accumulates the sub-pixel value of the sub-pixel B-, the sub-pixel value of the sub-pixel D-and the sub-pixel value of the sub-pixel E +, so as to obtain a sub-pixel sum value; the second calculating unit selects the sub-pixel with positive polarity and the sub-pixel with negative polarity according to the polarity of the sub-pixels in the first display line, and the sub-pixel with positive polarity is as follows: the sub-pixel a +, the sub-pixel C +, and the sub-pixel E +, which has negative polarity, is: and accumulating the sub-pixel value of the sub-pixel A +, the sub-pixel value of the sub-pixel C + and the sub-pixel value of the sub-pixel E + to obtain a positive sub-pixel accumulated value, accumulating the sub-pixel value of the sub-pixel B-, the sub-pixel of the sub-pixel D-and the sub-pixel of the sub-pixel F-to obtain a negative sub-pixel accumulated value, and then calculating the absolute value of the difference value of the positive sub-pixel accumulated value and the negative sub-pixel accumulated value.

In a specific implementation, as shown in fig. 11, the first calculating unit 611 may include a first selector 6111, a second selector 6112 and a first adder 6113;

an input end of the first selector 6111 is configured to input the shared value stored in the mode register, a control end of the first selector 6111 is connected to a first output end of the counter, and an output end of the first selector 6111 is connected to a control end of the second selector 6112, and is configured to output the shared value stored in the mode register under control of a first count value output by the counter;

an input end of the second selector 6112 is configured to input sub-pixel values in a plurality of first preset combinations, and an output end of the second selector 6112 is connected to a first input end of the first adder 6113, and is configured to select one first preset combination from the plurality of first preset combinations to output according to an input shared value, where a sub-pixel value of the first preset combination is a sub-pixel value of a combination of sub-pixel values in each pixel unit in a previous display row;

the output end of the first adder 6113 is connected to the second input end of the first adder 6113, and is configured to accumulate the input pixel values of the first sub-pixels in the previous display line, and output a sub-pixel sum value.

In the embodiment of the present invention, each pixel unit includes 3 sub-pixels for illustration.

For a pixel unit including RGB, after combining 3 sub-pixels RGB, 8 first preset combinations are obtained, which are respectively combination 1: "R + G + B", combination 2: "R + G", combination 3: "R + B", combination 4: "R", combination 5: "G + B", combination 6: "G", combination 7: "B", combination 8: "0", if the pixel value of a sub-pixel occupies 8 bits in the register, 24 bits are needed to store 3 sub-pixel values in a pixel unit, for example, pre _ line _ [7:0] represents the sub-pixel value of B sub-pixel in a pixel unit, pre _ line _ [15:8] represents the sub-pixel value of G sub-pixel in the pixel unit, pre _ line _ [23:16] represents the sub-pixel value of R sub-pixel in the pixel unit, combination 1 is pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line [7:0], combination 2 is pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line _ [7:0], combination 3 is pre _ line _ [23:16] + pre _ line _ [7: 8], combination 3 is pre _ line _ [23:16] + pre _ line ] + 7:0], combination [ 4: 7:0] _ combination [23: 15:8] _ line _ [15:8] _ line ] _, and combination 3 is [15: [ 16] _ line ] _ 15: [15 ] _0] _, 6] _ line ] _, combination [7: 15: [1 ] is [1 ] _ 2 ] of [1, and combination [1 [15: [ 16] _ line ] _ 2 ] of [15: [ 16] _ line ] _1 ] of [15: [ 16] _ line ] _1 ] _ 8] _1 ] of [15:8] _1 ] of [ 16] _1 ] of [15:8] _1 ] of [15 [1 ] of [15:8] _1 ] of [15 [ 16] _1 ] of [15 [1 ] of [15:8] _1 ] of [15:8] _1 ] of [15: 15, 6] of [1 ] of [15, 6] of [1, 6] of [1, combination 7 is pre _ line _ [7:0], and combination 8 is 0.

Fig. 12 is a schematic diagram of a first predetermined combination according to an embodiment of the present invention.

If 0 represents no participation in charge sharing and 1 represents participation in charge sharing, when the result output from the first selector 6111 is 000, indicating that none of the three sub-pixels participate in charge sharing, the result output from the second selector 6112 is the result of adding the sub-pixel values of the three sub-pixels, i.e., pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line _ [7:0 ]; if the result output by the first selector 6111 is 111, it indicates that all three sub-pixels participate in charge sharing, and the result output by the second selector 6112 is 0; if the output result of the first selector 6111 is 011, it indicates that the sub-pixels corresponding to pre _ line _ [15:8] in the three sub-pixels do not participate in charge sharing, and the output result of the second selector 6112 is pre _ line _ [15:8], and other combinations are selected in the manner described above, and will not be described in detail herein.

In a specific implementation, the sub-pixel values may be stored in a 24-bit sub-pixel register.

In the embodiment of the invention, the mode register adopts a 6-bit register.

For example, as shown in fig. 13, each bit of the sharing information stored in the mode register indicates a value of whether a corresponding sub-pixel in a certain display line participates in charge sharing, every 6 sub-pixels are in one cycle, the 6 sub-pixels of the sub-pixels R0, G0, B0, R1, G1 and B1 are in one cycle, the mode register stores information of whether the sub-pixel corresponding to the cycle participates in charge sharing, similarly, the 6 sub-pixels of the sub-pixels R2, G2, B2, R3, G3 and B3 are in one cycle, the mode register also stores information … … of whether the sub-pixel corresponding to the cycle participates in charge sharing, and so on until all the information of whether all the sub-pixels (1920) participate in charge sharing is completely stored.

The shared information stored in the mode register is the shared information corresponding to each 6 sub-pixels in the previous display line, if the counter inputs a first value to the first selector 6111, the first input terminal of the first selector 6111 inputs the shared information in the first 3 bits in the mode register, i.e., dot _ mode [2:0], and if the counter inputs a second value to the first selector 6111, the first input terminal of the first selector 6111 inputs the shared information in the last 3 bits in the mode register, i.e., dot _ mode [5:3], where the first value may be 0, the second value may be 1, the first value may also be 1, and the second value may also be 0.

After the second selector 6112 receives the sharing information, it determines whether each sub-pixel in the pixel unit input to the second selector 6112 participates in charge sharing according to the sharing information, 0 represents not participating in charge sharing, 1 represents participating in charge sharing, the currently input sharing information is 001, which indicates that the first sub-pixel does not participate in charge sharing, the second sub-pixel does not participate in charge sharing, and the third sub-pixel participates in charge sharing, so as to select combination 2, when the sub-pixel value is input to the first input terminal of the first adder 6113, the output terminal of the first adder 6113 outputs the sub-pixel value, and then feeds back the sub-pixel value to the second input terminal of the first adder 6113, when the first input terminal of the first adder 6113 inputs another sub-pixel value, the output terminal of the first adder 6113 outputs the sum of the sub-pixel value and another sub-pixel value, and the subsequent steps can refer to the aforementioned steps, until all sub-pixel values are input.

In a specific implementation, as shown in fig. 14, the second calculating unit 612 may include a third selector 6121, a fourth selector 6122, a fifth selector 6127, a second adder 6123, a third adder 6124, a first comparator 6125, and a subtractor 6126;

an input end of the third selector 6121 is configured to input the polarity value stored in the polarity register, a control end of the third selector 6121 is connected to the second output end of the counter, and an output end of the third selector 6121 is connected to a control end of the fourth selector 6122, and is configured to output the polarity value stored in the polarity register under control of a second count value output by the counter;

a second input end of the fourth selector 6122 is configured to input a sub-pixel value of a sub-pixel in a previous display line, and an output end of the fourth selector 6122 is connected to a first input end of the second adder 6123 and a first input end of the third adder 6124, and is configured to input a positive sub-pixel value to the first input end of the second adder 6123 and input a negative sub-pixel value to the first input end of the third adder 6124 according to the input polarity value;

the output end of the second adder 6123 is connected to the second input end of the second adder 6123, the first input end of the first comparator 6125 and the first input end of the subtractor 6126, and is configured to output a positive subpixel accumulation value;

the output end of the third adder 6124 is connected to the second input end of the third adder 6124, the second input end of the first comparator 6125 and the second input end of the subtractor 6126, and is configured to output a negative sub-pixel accumulated value;

the output end of the first comparator 6125 is connected to the control end of the fifth selector 6127, and is configured to compare the positive sub-pixel accumulated value with the negative sub-pixel accumulated value and output a comparison result;

a first output end of the subtractor 6126 is connected to a first input end of the fifth selector 6127 and configured to output a first difference value between the positive sub-pixel accumulated value and the negative sub-pixel accumulated value, and a second output end of the subtractor 6126 is connected to a second input end of the fifth selector 6127 and configured to output a second difference value between the negative sub-pixel accumulated value and the positive sub-pixel accumulated value;

a fifth selector 6127, configured to output an absolute value of the difference under control of the comparison result.

For a pixel unit including three RGB sub-pixels, after combining 3 RGB sub-pixels, 8 second preset combinations are obtained, which are respectively a combination 9: "{ 0, R + G + B }", combination 2: "{ B, R + G }", combination 3: "{ G, R + B }", combination 4: "{ G + B, R }", combination 5: "{ R, G + B }", combination 6: "{, R + B, G }", combination 7: "{ R + G, B }", combination 8: "{ R + G + B, 0 }", if the pixel value of a sub-pixel occupies 8 bits in the register, 24 bits are required to store 3 sub-pixel values in a pixel unit, e.g., pre _ line _ [7:0] represents the sub-pixel value of B sub-pixel in a pixel unit, pre _ line _ [15:8] represents the sub-pixel value of G sub-pixel in the pixel unit, pre _ line _ [23:16] represents the sub-pixel value of R sub-pixel in the pixel unit, the combination 9 is {0, pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line _ [7:0] }, the combination 10 is { pre _ line _ [7:0], pre _ line _ [23:16] + pre _ line _ [15:8] + 8] }, the combination 11 is { pre _ line _ [7:0] } 15, the combination 10 is { pre _ line _ [15: 15 } line _ [15: 0] + 15, the combination 7:0] }, the combination 7: 12 is [15: 15 } line _ [15 } line ] + 15, the combination 7: 12, the combination 7: 15 } line [15: 15 }, pre _ line _ [23:16] }, combination 13 is { pre _ line _ [23:16], pre _ line _ [15:8] + pre _ line _ [7: 0}, combination 14 is { pre _ line _ [23:16] + pre _ line _ [7:0], pre _ line _ [15:8 }, combination 15 is { pre _ line _ [23:16] + pre _ line _ [15:8], pre _ line _ [7:0] }, combination 16 is { pre _ line _ [23:16] + pre _ line _ [15:8] -, pre _ line _ [7:0] }.

Fig. 15 is a schematic diagram of a second predetermined combination according to an embodiment of the present invention.

As can be seen from the above example, the second preset combination in the embodiment of the present invention includes two parts, namely, two parts before and after the comma in the brace, where the first part, namely, the part before the comma in the brace is the part output to the first input terminal of the second adder 6123, and the second part, namely, the part after the comma in the brace is the part output to the first input terminal of the third adder 6124, namely, the first part in the second preset combination corresponds to the positive sub-pixel value, and the second part corresponds to the negative sub-pixel value.

If 0 represents that the pixel electrode of the sub-pixel is negative, and 1 represents that the pixel electrode of the sub-pixel is negative, when the result output by the third selector 6121 is 000, which indicates that all three sub-pixels are negative sub-pixels, the third selector 6122 selects the output of the combination 9, i.e., the result output to the second adder 6123 is 0, and the result output to the third adder 6124 is the sum of the added sub-pixel values of the three sub-pixels, i.e., pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line _ [7:0 ]; if the result output by the third selector 6121 is 111, which indicates that all three sub-pixels are positive sub-pixels, the fourth selector 6122 selects the output of the combination 16, i.e., the result output to the second adder 6123 is the sum of the sub-pixel values of the three sub-pixels, i.e., pre _ line _ [23:16] + pre _ line _ [15:8] + pre _ line _ [7:0], and the result output to the third adder 6124 is 0; if the output of the third selector 6121 is 011, it means that the sub-pixel corresponding to pre _ line _ [23:16] of the three sub-pixels is a negative sub-pixel, and the other two sub-pixels are positive sub-pixels, then the fourth selector 6122 selects the output of the combination 12, i.e., pre _ line _ [15:8] + pre _ line _ [7:0] is input to the second adder 6123, and pre _ line _ [23:16] is input to the third adder 6124. Other combinations are selected in the manner described above and will not be described in detail here.

The polarity register in the embodiment of the present invention may be an 8-bit register.

As shown in fig. 16, each bit of the polarity register represents the positive and negative of the pixel polarity of each sub-pixel in the previous display line, each 8 sub-pixels form a cycle, the 8 sub-pixels R0, G0, B0, R1, G1, B1, R2, and G2 form a cycle, the polarity register stores the polarity information corresponding to each sub-pixel in the cycle, and the 8 sub-pixels B2, R3, G3, B3, R4, G4, B4, and R5 form a cycle in sequence, and similarly, the polarity register stores the polarity information … … corresponding to each sub-pixel in the cycle, and so on until all the polarity information of all the sub-pixels (1920) is stored.

The polarity information stored in the polarity register is the polarity information corresponding to each 8 sub-pixels in the previous display line, if the counter inputs a third value to the second selector 6121, the second selector 6121 outputs the polarity information in the first 3 bits stored in the polarity register, that is, [2:0], if the counter inputs a fourth value to the second selector 6121, the second selector 6121 outputs the polarity information in the second 3 bits stored in the polarity register, that is, [5:3], if the counter inputs a fifth value to the second selector 6121, the second selector 6121 outputs the polarity information in the last two bits stored in the polarity register and the polarity information in the first bit stored in the polarity register in the next cycle, that is, { [0], [7:6] }, and so on.

As shown in fig. 17, the total calculating unit 613 may include a fourth adder 6131, a first input terminal of the fourth adder 6131 is used for inputting the sub-pixel sum value, a second input terminal of the fourth adder 6131 is used for inputting the absolute value of the difference value, and an output terminal of the fourth adder 6131 is used for outputting the total sum value.

The fourth adder 6131 adds the input sum value and the absolute value of the difference value to obtain a total sum value, which is used to represent the suitability of the preset charge sharing mode, and if the total sum value is smaller, the preset charge sharing mode is more suitable.

In the embodiment of the present invention, each row in the TFT-LCD display panel is sequentially used as a previous display row, the first calculating unit 611 selects a first sub-pixel not participating in charge sharing from the previous display row according to the sharing information stored in the mode register, calculates a sub-pixel sum value of all the first sub-pixels in the previous display row, simultaneously adds sub-pixel values of sub-pixels having positive pixel electrodes in the previous display row according to the polarity information stored in the polarity register to obtain a positive sub-pixel accumulated value, adds sub-pixel values of sub-pixels having negative pixel electrodes in the previous display row to obtain a negative sub-pixel accumulated value, and calculates an absolute value of a difference between the positive sub-pixel accumulated value and the negative sub-pixel accumulated value, and the total calculating unit 613 calculates a total sum value of the pixel sum value and the absolute value of the difference.

In a particular embodiment, as shown in fig. 18, the minimum value determining module 62 may include a plurality of second comparators 621;

the input end of the first-stage second comparator 621 is used to input the total sum value corresponding to each preset charge sharing mode and the identifier corresponding to the sum value, and the output end of the previous-stage second comparator 621 is connected to the input end of the next-stage second comparator 621;

each second comparator 621 is configured to compare every two of the input multiple total summation values to obtain a comparison result and a corresponding identifier, where the comparison result output by the output end of the last-stage second comparator 621 is a minimum total summation value and an identifier corresponding to the minimum total summation value.

In fig. 18, n, m, and j are positive integers greater than 1, and in [ x0, Sum1_0], x0 represents a flag, and Sum1_0 represents a total Sum value. The number of the total sum values input to the input end of the first-stage second comparator 621 is the same as the number of the preset charge sharing modes, that is, each preset charge sharing mode corresponds to one total sum value, the first-stage second comparator 621 compares the input total sum values pairwise, and compares ((n +1)/2) times to obtain (m +1) comparison results, where m ═ ((n +1)/2) -1, (m +1) comparison results are input to the second-stage second comparator 621, and the second-stage second comparator 621 compares ((m +1)/2) times to obtain ((m +1)/4) comparison results, … …, until the last-stage second comparator 621 outputs one comparison result.

In the embodiment of the present invention, as shown in fig. 19, the summing module includes a plurality of summing modules, each summing module corresponds to a preset charge sharing mode, and therefore, when the summing module inputs the calculated total sum value to the minimum value determining module, the summing module also inputs the identifier corresponding to the summing module to the minimum value determining module.

The last-stage second comparator 621 sends the minimum sum value and the identifier corresponding to the minimum sum value to the source driving circuit of the display device, so that the source driving circuit controls the target charge sharing mode to be enabled according to the identifier, and the last display line and the current display line are charge-shared.

And after receiving the minimum total sum value and the identifier corresponding to the minimum total sum value, the source driving circuit determines a charge sharing mode corresponding to the received identifier according to the corresponding relation between the identifier and the charge sharing mode, takes the charge sharing mode as a target charge sharing mode and enables the target charge sharing mode. Wherein, the corresponding relation between the mark and the charge sharing mode is preset.

In a specific implementation, after the minimum value determining module 62 determines the minimum total sum value and the identifier corresponding to the minimum total sum value, the minimum total sum value and the identifier corresponding to the minimum total sum value may be further input to the comparing module 63, as shown in fig. 19, the comparing module 63 compares the minimum total sum value with a preset threshold, and sends the comparison result to the source driving circuit, so that the source driving circuit controls the target charge sharing mode to be enabled according to the comparison result.

Specifically, the comparing module 63 may include a third comparator 631, as shown in fig. 21, a first input terminal of the third comparator 631 is configured to input the minimum sum value and the identifier corresponding to the minimum sum value, a second input terminal of the third comparator 631 is configured to input a preset threshold, and an output terminal of the third comparator 631 is configured to output a comparison result, where the comparison result is the minimum sum value and the identifier corresponding to the minimum sum value if the minimum sum value is less than or equal to the preset threshold, and the comparison result is the preset threshold if the minimum sum value is greater than the preset threshold.

After receiving the minimum sum value and the identifier corresponding to the minimum sum value, the source electrode driving circuit determines a charge sharing mode corresponding to the received identifier according to the corresponding relation between the identifier and the charge sharing mode, takes the charge sharing mode as a target charge sharing mode and enables the target charge sharing mode; after the source driving circuit receives the preset threshold, if the most suitable charge sharing mode is not selected, any preset charge sharing mode is not enabled.

For ease of understanding, the present invention is described below in terms of specific implementations.

As shown in fig. 19, the circuit for selecting a charge sharing mode according to an embodiment of the present invention includes 16 summing modules, which are summing module 0, summing module 1, and summing module 2 … …, respectively, where each summing module corresponds to one preset charge sharing mode, for example, summing module 0 corresponds to charge sharing mode 0, and the corresponding identifier is 0; the summing module 1 corresponds to the charge sharing mode 1, and the corresponding identifier is 1; summing module 2 corresponds to charge sharing mode 2, corresponding to summing module 15 identified as 2 … … corresponds to charge sharing mode 15, corresponding to 15.

The following describes an embodiment of the present invention in detail with reference to fig. 11, 14, 17, 19, 20, 22, and 23.

The pixel values of the sub-pixels in the previous display line are input to the second selector 6112, meanwhile, the mode register inputs the stored mode information of the charge sharing mode 0 to the first selector 6111, the first selector 6111 outputs the mode information stored in the corresponding mode register to the second selector 6112 under the control of the first count value output by the counter, the second selector 6112 selects the output first preset combination according to the mode information, and the first adder 6113 accumulates the sub-pixel values in the output first preset combination to obtain the sub-pixel sum value sum _ un.

The polarity register inputs the stored polarity of the sub-pixel in the previous display line to the third selector 6121, the third selector 6121 outputs the polarity of the sub-pixel according to the second count value output by the counter, the fourth selector 6122 receives the pixel value of the sub-pixel in the previous display line, the fourth selector 6122 selects a second preset combination according to the received polarity of the sub-pixel, and outputs the positive sub-pixel value in each pixel unit to the second adder 6123 according to the selected second preset combination, and outputs the negative sub-pixel in each pixel unit to the third adder 6124, the second adder 6123 accumulates the received positive sub-pixel values to obtain a positive sub-pixel accumulated value sum _ pos, and the third adder 6124 accumulates the received negative sub-pixel value to obtain a negative sub-pixel accumulated value sum _ neg.

The second adder 6123 inputs the output positive sub-pixel accumulated value sum _ pos and the output negative sub-pixel accumulated value sum _ neg to the first input terminal and the second input terminal of the first comparator 6125 and the first input terminal and the second input terminal of the subtractor 6124, the first comparator 6125 compares the positive sub-pixel accumulated value sum _ pos and the negative sub-pixel accumulated value sum _ neg, outputs a comparison result, and outputs the comparison result to the control terminal of the fifth selector 6127; the subtractor 6126 receives the positive sub-pixel accumulated value sum _ pos and the negative sub-pixel accumulated value sum _ neg, subtracts the positive sub-pixel accumulated value sum _ pos and the negative sub-pixel accumulated value sum _ neg to obtain a first difference value, subtracts the negative sub-pixel accumulated value sum _ neg and the positive sub-pixel accumulated value sum _ pos to obtain a second difference value, and outputs the first difference value and the second difference value to the fifth selector 6127.

The fifth selector 6127 outputs the absolute value of the difference abs _ diff under the control of the comparison result, and if the comparison result is greater than 0, the fifth selector 6127 takes the first difference as the absolute value of the difference abs _ diff, otherwise takes the second difference as the absolute value of the difference abs _ diff.

The fourth adder 6131 adds the sum of the sub-pixels sum _ un and the absolute value abs _ diff of the difference obtained in the charge sharing mode 0 to obtain a total sum _0, where 0 may represent the identifier of the summing block or the identifier of the charge sharing mode.

Since the preset charge sharing mode has 16 types, that is, 16 mode registers, the above steps are repeated 16 times, and finally 16 accumulated values sum _ x are obtained, where x is an integer from 0 to 15.

The minimum determination module 62 compares the input 16 total sums to obtain a minimum total sum.

As shown in fig. 20, when there are 16 preset charge sharing modes, the minimum value determining module has a schematic structural diagram. The minimum value determining module 62 includes 4 second comparators 621, the first-stage second comparator 621 inputs 16 total sum values and an identifier corresponding to each total sum value, after comparing the 16 total sum values pairwise, 8 comparison results are output, the 8 comparison results are input to the second-stage second comparator 621, after comparing the 8 comparison results pairwise, the second-stage comparator 621 outputs 4 comparison results, outputs 2 comparison results, the 2 comparison results are input to the last-stage second comparator 621, and the last-stage comparator outputs one comparison result which is the minimum total sum value.

The comparing module 63 compares the minimum sum with a preset threshold, and outputs the sum and the identifier corresponding to the minimum sum if the minimum sum is smaller than or equal to the preset threshold, or outputs the preset threshold otherwise.

For example, if the minimum sum value is output by the sum block 0, the target charge share flag is 0.

Specific mode registers and polarity registers are described below.

As shown in fig. 22, for example, the polarities of the mode register reg _ dot _ mode [5:0] ═ 6' B01_0101, R0, G0, B0, R1, G1, B1, and then every 6 consecutive subpixels are stored in the 6-bit mode register, i.e., 0, 1, respectively. A 0 indicates that the corresponding sub-pixel does not participate in charge sharing, and a 1 indicates that the corresponding sub-pixel participates in charge sharing.

When the first output end of the counter counts 1 for the first time, the corresponding three sub-pixels are respectively R0, G0 and B0, and the corresponding polarity patterns are respectively 0, 1 and 0, namely R0 and B0 do not participate in charge sharing, and G0 participates in charge sharing. Referring to fig. 11, the pixel values of R0 and B0 are accumulated to sum _ un by the second selector 6122 and the first adder 6113. When the first output end of the counter counts to 2 for the first time, the corresponding three sub-pixels are respectively R1, G1 and B1, the corresponding polarity patterns are respectively 1, 0 and 1, that is, G1 does not participate in charge sharing, R1 and B1 participate in charge sharing, and the pixel value of G1 is accumulated to sum _ un through the second selector 6122 and the first adder 6113.

When the first output end of the counter counts 1 for the second time, the corresponding three sub-pixels are respectively R2, G2 and B2; when the first output end of the second time counts to 2, the corresponding three sub-pixels are respectively R3, G3 and B3; by analogy, if the entire row consists of 1920 pixels, the counter counts 960 groups of 2 times each.

As shown in fig. 23, the polarity register reg _ dot _ pol [7:0] ═ 8' B1011_1100, and the polarities of R0, G0, B0, R1, G1, B1, R2, G2, and then every 8 consecutive subpixels correspond to 8-bit polarity registers, that is, 1, 0, 1, 0, 1 is positive, 0 indicates that the pixel polarity is negative, and 1 indicates that the pixel polarity is positive. And accumulating the pixel value of the sub-pixel with the positive pixel polarity to a positive sub-pixel accumulated value sum _ pos, and accumulating the pixel value of the sub-pixel with the negative pixel polarity to a negative sub-pixel accumulated value sum _ neg.

When the second output end of the counter counts 1 for the first time, the corresponding three sub-pixels are respectively R0, G0 and B0, and the corresponding polarities are respectively 1, 0 and 1, that is, the voltage polarities of R0 and B0 are positive, and the voltage polarity of G0 is negative. Referring to fig. 14, the sub-pixel values of R0 and B0 are accumulated to sum _ pos by the third selector 6121, the fourth selector 6122 and the second adder 6123, and the sub-pixel value of G0 is accumulated to sum _ neg by the third selector 6121, the fourth selector 6122 and the third adder 6124. When the second output end of the counter counts 2 for the first time, the corresponding three sub-pixels are respectively R1, G1 and B1, the corresponding polarities are respectively 1, 1 and 1, that is, the voltage polarities of R1, G1 and B1 are all positive, and the pixel values of R1, G1 and B1 are accumulated to sum _ pos through the third selector 6121, the fourth selector 6122 and the second adder 6123; when the second output end of the counter counts for the first time to 3, the corresponding three sub-pixels are respectively R2, G2 and B2, the corresponding polarities are respectively 0, 0 and 1, that is, the voltage polarity of B2 is positive, the voltage polarities of R2 and G2 are negative, the pixel value of B2 is accumulated to sum _ pos by the third selector 6121, the fourth selector 6122 and the second adder 6123, and the pixel values of R2 and G2 are accumulated to sum _ neg.

When the second output end of the counter counts 1 for the second time, the corresponding three sub-pixels are respectively R8, G8 and B8; when the second output end of the counter counts 2 for the second time, the corresponding three sub-pixels are respectively R9, G9 and B9; by analogy, if the entire row consists of 1920 pixels, the counter counts up to 240 groups, each group counting 8 times. After the charge sharing mode of the TFT-LCD display panel is determined, the TCON transmits the minimum sum value and the corresponding identification data to the source electrode driving circuit, and the source electrode driving circuit converts the minimum sum value and the corresponding identification data into analog signals for charge sharing.

It should be noted that, in the embodiment of the present invention, the polarity of the pixel electrode of the sub-pixel is equal to the voltage polarity of the sub-pixel.

Based on the same inventive concept, the embodiment of the present invention further provides a TCON, which includes any one of the circuits for selecting the charge sharing mode. The principle of the TCON solution is similar to that of the circuit for selecting the charge sharing mode, so the implementation of the TCON can be referred to the implementation of the circuit for selecting the charge sharing mode, and repeated details are not repeated here.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 24, including any one of the TCONs 102 described above. The implementation of the display device can refer to the implementation of the TCON described above, and the repetition part is not described herein again.

As can be further seen from fig. 24, the display device according to the embodiment of the present invention further includes a source driving circuit 104, a gate driving circuit 105, and a display 241, and the TCON102 provides timing control signals for the source driving circuit 104 and the gate driving circuit 105, so that the display 241 can correctly display an image.

Various modifications and alterations of this invention may be made by those skilled in the art without departing from the spirit and scope of this invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A circuit for selecting a charge sharing mode, applied to a display device, comprising:

and the minimum value determining module is used for selecting a minimum total sum value from total sum values corresponding to a plurality of preset charge sharing modes, and outputting the minimum total sum value and an identifier corresponding to the minimum total sum value to a source electrode driving circuit of the display equipment so that the source electrode driving circuit controls enabling of a target charge sharing mode according to the identifier and enables the last display line and the current display line to carry out charge sharing.

2. The circuit of claim 1, wherein the summing module comprises a first computing unit, a second computing unit, and a total computing unit;

the first calculating unit is used for selecting first sub-pixels which do not participate in charge sharing from the previous display line according to the preset charge sharing mode, and calculating sub-pixel sum values of the first sub-pixels;

3. The circuit of claim 1, further comprising a comparison module;

4. The circuit of claim 3, wherein the comparison module comprises a third comparator;

5. The circuit of claim 2, wherein the first calculation unit includes a first selector, a second selector, and a first adder;

the input end of the second selector is used for inputting sub-pixel values in a plurality of first preset combinations, and the output end of the second selector is connected with the first input end of the first adder and is used for selecting one preset combination from the plurality of first preset combinations to be output according to the input shared value, wherein the first preset combination is a combination determined according to the sub-pixel value in each pixel unit in the previous display line;

6. The circuit of claim 5, wherein the second calculation unit includes a third selector, a fourth selector, a fifth selector, a second adder, a third adder, a first comparator, and a subtractor;

an input end of the fourth selector is configured to input a sub-pixel value in a second preset combination, a first output end of the fourth selector is connected to the first input end of the second adder, and a second output end of the fourth selector is connected to the first input end of the third adder, and is configured to select one second preset combination from the plurality of second preset combinations according to the input polarity value, and output a positive sub-pixel value and a negative sub-pixel value according to the sub-pixel value in the selected second preset combination, where the second preset combination is a combination determined according to the sub-pixel value in each pixel unit in the previous display line;

the output end of the first comparator is connected with the control end of the fifth selector, and is used for comparing the positive sub-pixel accumulated value with the negative sub-pixel accumulated value and outputting a comparison result;

and the fifth selector is used for outputting the absolute value of the difference under the control of the comparison result.

7. The circuit of claim 2, wherein the total computation unit includes a fourth adder;

8. The circuit of claim 1, wherein the minimum determination module comprises a plurality of second comparators;

9. A timing controller TCON comprising the circuit for selecting a charge share mode according to any one of claims 1 to 8.

10. A display device comprising the timing controller TCON of claim 9.