CN115097282A - Array chip testing method, system, computer device and storage medium - Google Patents
Array chip testing method, system, computer device and storage medium Download PDFInfo
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- CN115097282A CN115097282A CN202210632144.3A CN202210632144A CN115097282A CN 115097282 A CN115097282 A CN 115097282A CN 202210632144 A CN202210632144 A CN 202210632144A CN 115097282 A CN115097282 A CN 115097282A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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Abstract
The invention is suitable for the technical field of computers, and provides an array chip testing method, an array chip testing system, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring image information of the array chip; extracting chip information contained in the image information, and marking the chip information in a coordinate system according to position information; planning the motion track of the probe or the optical fiber or the wafer bearing table according to the position information of the chip in the coordinate system; the probe or the optical fiber or the wafer bearing platform is controlled to sequentially test the chip on the set motion track and output the test result, and the invention has the beneficial effects that: the chips to be tested are arranged in an array form, the positions of the chips are calibrated in a coordinate system, then the chips are sequentially tested according to the preset motion track, and the test result is output, so that the test of the chips can be completed at one time, the problem of automation of array test is solved, the test efficiency is improved, and the cost is reduced.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an array chip testing method, system, computer device, and storage medium.
Background
The chip, also called microcircuit, microchip, integrated circuit, refers to the silicon chip containing integrated circuit, the volume is very small, is an important component of computer and other electronic equipment. Because the chip has a fine structure, a complex manufacturing process and a complicated flow, potential defects are inevitably left in the production process, so that the manufactured chip cannot meet the standard requirements and can break down due to various reasons at any time. Therefore, in order to ensure the quality of chips, the chips are usually tested (a plurality of test items including electrical parameter measurement and functional test) to separate good products from defective products.
With the increase of the market demand of laser radars, the requirements for realizing the automatic test of the array chip and improving the efficiency become very urgent, and the existing automatic test scheme of a single chip cannot meet the requirements.
Disclosure of Invention
Embodiments of the present invention provide an array chip testing method, system, computer device, and storage medium, which are intended to solve the technical problems in the prior art identified in the background art.
The embodiment of the invention is realized in such a way that the array chip testing method comprises the following steps:
acquiring image information of the array chip;
extracting chip information contained in the image information, and marking the chip information in a coordinate system according to the position information;
planning the motion track of the probe or the optical fiber or the wafer bearing platform according to the position information of the chip in the coordinate system;
and controlling the probe or the optical fiber or the wafer bearing platform to sequentially test the chips on the set motion trail and output a test result.
As a further scheme of the invention: the step of acquiring image information of the array chip specifically includes:
acquiring real-time picture information of the array chip;
detecting the real-time picture information and adjusting the focal length of a camera to ensure that each chip unit in the array chip is positioned in the real-time picture information;
and when each chip unit in the array chip is in the real-time picture information, shooting the array chip to obtain the image information of the array chip.
As a still further scheme of the invention: the step of extracting the chip information contained in the image information and marking the chip information in a coordinate system according to the position information specifically includes:
identifying each chip contained in the image information;
marking each identified chip to obtain image information containing all chip marks;
and projecting the image information into a coordinate system matched with the image information, and representing the position information of each chip by coordinates.
As a still further scheme of the invention: the step of planning the motion track of the probe or the optical fiber or the wafer stage according to the position information of the chip in the coordinate system specifically comprises the following steps:
acquiring position information of each chip;
and determining the optimal motion track of the probe or the optical fiber or the wafer bearing table according to the motion rules from left to right and from top to bottom.
As a still further scheme of the invention: the step of controlling the probe, the optical fiber or the wafer bearing table to sequentially test the chip on the set motion track and output the test result specifically comprises the following steps:
controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail;
judging a test result of the chip at the corresponding position, adding a passing mark for the coordinate for representing the position of the corresponding chip when the test result is Y, and adding a failing mark for the coordinate for representing the position of the corresponding chip when the test result is N;
and after all the chips are tested, storing the test result.
As a still further scheme of the invention: after all the chips are tested and the test result is stored, the following steps are also executed:
traversing each test result;
judging whether each test result contains a fail flag;
when the test result comprises the non-passing mark, putting the corresponding test result and the chip coordinate into a set to be processed;
and outputting the to-be-processed set to a user.
Another objective of an embodiment of the present invention is to provide an array chip testing system, including:
the image acquisition module is used for acquiring image information of the array chip;
the position marking module is used for extracting chip information contained in the image information and marking the chip information in a coordinate system according to the position information;
the track planning module is used for planning the motion track of the probe or the optical fiber or the wafer bearing platform according to the position information of the chip in the coordinate system;
and the test module is used for controlling the probe or the optical fiber or the wafer bearing platform to sequentially test the chips on the set motion trail and output a test result.
It is another object of the embodiments of the invention to provide a computer apparatus, which includes a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, causes the processor to execute the steps of the array chip testing method.
It is another object of the embodiments of the present invention to provide a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, causes the processor to execute the steps of the array chip testing method.
Compared with the prior art, the invention has the beneficial effects that: the chips to be tested are arranged in an array form, the positions of the chips are calibrated in a coordinate system, then the chips are sequentially tested according to the preset motion track, and the test result is output, so that the test of the chips can be completed at one time, the problem of automation of array test is solved, the test efficiency is improved, and the cost is reduced.
Drawings
FIG. 1 is a flow chart of a method for testing an array chip.
Fig. 2 is a flowchart for acquiring image information of the array chip.
Fig. 3 is a flowchart for extracting chip information included in the image information and marking the chip information in a coordinate system according to position information.
FIG. 4 is a flow chart for planning the motion trajectory of the probe or fiber or stage based on the chip position information in the coordinate system.
Fig. 5 is a flowchart for controlling the probe or the optical fiber or the stage to sequentially test the chip on the set motion track and output the test result.
FIG. 6 is a flow chart of saving test results when all chips have been tested.
FIG. 7 is a flow chart of an array chip test system.
Fig. 8 is a schematic structural diagram of a computer device.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not delimit the invention.
Specific implementations of the present invention are described in detail below with reference to specific embodiments.
As shown in fig. 1, a flowchart of an array chip testing method according to an embodiment of the present invention includes the following steps:
s100, acquiring image information of the array chip.
The array chip in the embodiment of the present invention refers to a means for distributing the chips to be tested in an array form, and then performing a concentrated sequential test on the chips to improve the test effect.
S200, extracting chip information contained in the image information, and marking the chip information in a coordinate system according to the position information.
S300, planning the motion track of the probe or the optical fiber or the wafer bearing table according to the position information of the chip in the coordinate system.
And S400, controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail and outputting a test result.
In the embodiment of the invention, the chips to be tested are arranged in the form of an array, the positions of the chips are calibrated in a coordinate system, the chips are sequentially tested according to the preset motion track, and the test result is output, so that the test of a plurality of chips can be completed at one time, the problem of automation of array test is solved, the test efficiency is improved, and the cost is reduced.
As shown in fig. 2, as a preferred embodiment of the present invention, the step of acquiring image information of an array chip specifically includes:
s101, acquiring real-time picture information of the array chip.
S102, detecting the real-time picture information, and adjusting the focal length of the camera to enable each chip unit in the array chip to be in the real-time picture information.
S103, when each chip unit in the array chip is in the real-time picture information, shooting the array chip to obtain the image information of the array chip.
In the embodiment of the invention, the real-time picture information of the array chip can be acquired through the industrial CCD camera, and the real-time picture information is detected, so that the purpose is to judge whether the picture information is centered, whether the array chip can be paved with the whole picture and the like, and then each chip unit in the array chip is ensured to be in the real-time picture information by adjusting the focal length of the camera, the position of the camera and the like.
It should be noted that the array chip is preferably spread over the entire frame, so that the background or other problems in the subsequent recognition process can be prevented from adversely affecting the recognition process. And when each chip unit in the array chip is in the real-time picture information, shooting the array chip to obtain the image information of the array chip.
As shown in fig. 3, as another preferred embodiment of the present invention, the step of extracting chip information included in the image information and marking the chip information in a coordinate system according to position information specifically includes:
s201, identifying each chip included in the image information.
S202, marking each identified chip to obtain image information containing all chip marks.
S203, projecting the image information to a coordinate system matched with the image information, and expressing the position information of each chip by coordinates.
In the embodiment of the invention, the chip can be identified through the specific pins on the surface of the chip or the production identification information on the surface of the chip, after the chip is identified, each identified chip can be marked, so that the image information contains a plurality of chip marks, then the image information is projected into a coordinate system matched with the image information, the position of the origin of the coordinate system can correspond to a certain angle of the image information, so that each chip mark in the image information can correspondingly obtain a unique coordinate, and the position information of each chip can be represented by the coordinate.
As shown in fig. 4, as another preferred embodiment of the present invention, the step of planning the motion track of the probe or the optical fiber or the stage according to the position information of the chip in the coordinate system specifically includes:
s301, position information of each chip is obtained.
S302, determining the optimal motion track of the probe or the optical fiber or the wafer bearing table according to the motion rules from left to right and from top to bottom.
In the embodiment of the invention, after the position information of each chip is represented by coordinates, the position of each chip is equivalent to the position where the probe or the optical fiber or the wafer bearing table needs to stay or pass, and based on the position information, the optimal motion track of the probe or the optical fiber or the wafer bearing table can be generated to realize the test of all chips on the motion track.
As shown in fig. 5, as another preferred embodiment of the present invention, the step of controlling the probe, the optical fiber, or the stage to sequentially test the chip on the set motion trajectory and output the test result specifically includes:
s401, controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chip on the set motion track.
S402, judging the test result of the chip at the corresponding position, adding a pass mark for the coordinate representing the position of the corresponding chip when the test result is Y, and adding a fail mark for the coordinate representing the position of the corresponding chip when the test result is N.
And S403, after all the chips are tested, storing the test result.
The embodiment of the invention mainly tests the chips to be tested one by one in sequence, wherein Y represents that the test is passed or normal, N represents that the test is not passed or abnormal, and in practical application, if a space or an empty position exists between two chips, a probe or an optical fiber or a wafer bearing platform directly skips or does not carry out a stop test when passing the position, and the position is empty, so the position does not have chip coordinates, and the storage of the test result or the coordinate marking is not influenced.
As shown in fig. 6, as another preferred embodiment of the present invention, after the step of saving the test result after all the chips are tested, the following steps are further performed:
and S4031, traversing each test result.
S4032, determine whether each of the test results includes a fail flag.
And S4033, when the test result contains the non-passing mark, putting the corresponding test result and the chip coordinate into a set to be processed.
And S4034, outputting the to-be-processed set to a user.
In the embodiment of the invention, the purpose of traversing each test result is to judge all test results and avoid omission, and when the test result contains a non-passing mark, the corresponding test result and the chip coordinate are put into a to-be-processed set, wherein the to-be-processed set needs to be sent to a user, so that the user can further process and analyze the chip which does not pass the test.
As shown in fig. 7, an embodiment of the present invention further provides an array chip testing system, including:
an image obtaining module 100, configured to obtain image information of an array chip;
a position marking module 200, configured to extract chip information included in the image information, and mark the chip information in a coordinate system according to the position information;
the trajectory planning module 300 is used for planning the motion trajectory of the probe or the optical fiber or the wafer stage according to the position information of the chip in the coordinate system;
and the test module 400 is used for controlling the probe or the optical fiber or the wafer stage to sequentially test the chips on the set motion trail and output a test result.
In the embodiment of the invention, the chips to be tested are arranged in the form of an array, the positions of the chips are calibrated in a coordinate system, the chips are sequentially tested according to the preset motion track, and the test result is output, so that the test of a plurality of chips can be completed at one time, the problem of automation of array test is solved, the test efficiency is improved, and the cost is reduced.
As shown in fig. 8, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, where the memory stores a computer program, and when the computer program is executed by the processor, the computer program causes the processor to execute:
s100, acquiring image information of the array chip.
S200, extracting chip information contained in the image information, and marking the chip information in a coordinate system according to the position information.
S300, planning the motion track of the probe or the optical fiber or the wafer bearing table according to the position information of the chip in the coordinate system.
And S400, controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail and outputting a test result.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the processor is caused to execute:
s100, acquiring image information of the array chip.
S200, extracting chip information contained in the image information, and marking the chip information in a coordinate system according to the position information.
S300, planning the motion track of the probe or the optical fiber or the wafer bearing table according to the position information of the chip in the coordinate system.
And S400, controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail and outputting a test result.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in a strict order unless explicitly stated herein, and may be performed in other orders. Moreover, at least a portion of the steps in the embodiments may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by a computer program, which may be stored in a non-volatile computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (9)
1. The array chip testing method is characterized by comprising the following steps:
acquiring image information of an array chip;
extracting chip information contained in the image information, and marking the chip information in a coordinate system according to position information;
planning the motion track of the probe or the optical fiber or the wafer bearing table according to the position information of the chip in the coordinate system;
and controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail and output a test result.
2. The method for testing an array chip according to claim 1, wherein the step of obtaining the image information of the array chip specifically comprises:
acquiring real-time picture information of the array chip;
detecting the real-time picture information and adjusting the focal length of a camera to enable each chip unit in the array chip to be in the real-time picture information;
and when each chip unit in the array chip is in the real-time picture information, shooting the array chip to obtain the image information of the array chip.
3. The method for testing an array chip according to claim 1, wherein the step of extracting chip information included in the image information and marking the chip information in a coordinate system according to position information specifically comprises:
identifying each chip contained in the image information;
marking each identified chip to obtain image information containing all chip marks;
and projecting the image information into a coordinate system matched with the image information, and expressing the position information of each chip by coordinates.
4. The method for testing an array chip according to claim 1, wherein the step of planning the motion trajectory of the probe or the optical fiber or the stage according to the position information of the chip in the coordinate system specifically comprises:
acquiring position information of each chip;
and determining the optimal motion track of the probe or the optical fiber or the wafer bearing table according to the motion rules from left to right and from top to bottom.
5. The method according to claim 1, wherein the step of controlling the probe or the optical fiber or the stage to sequentially test the chips on the set motion trajectory and output the test result specifically comprises:
controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail;
judging a test result of the chip at the corresponding position, adding a passing mark for the coordinate for representing the position of the corresponding chip when the test result is Y, and adding a failing mark for the coordinate for representing the position of the corresponding chip when the test result is N;
and after all the chips are tested, storing the test result.
6. The method for testing the array chip of claim 5, wherein after the step of storing the test results after all the chips are tested, the following steps are further performed:
traversing each test result;
judging whether each test result contains a fail flag;
when the test result comprises a non-passing mark, putting the corresponding test result and the chip coordinate into a set to be processed;
and outputting the to-be-processed set to a user.
7. An array chip test system, comprising:
the image acquisition module is used for acquiring image information of the array chip;
the position marking module is used for extracting chip information contained in the image information and marking the chip information in a coordinate system according to the position information;
the track planning module is used for planning the motion track of the probe or the optical fiber or the wafer bearing platform according to the position information of the chip in the coordinate system;
and the test module is used for controlling the probe or the optical fiber or the wafer bearing table to sequentially test the chips on the set motion trail and output a test result.
8. A computer device comprising a memory and a processor, the memory having stored therein a computer program that, when executed by the processor, causes the processor to perform the steps of the array chip testing method of any one of claims 1 to 6.
9. A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the steps of the array chip testing method of any one of claims 1 to 6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316262A (en) * | 2023-11-30 | 2023-12-29 | 深圳市领德创科技有限公司 | Automatic FLASH chip detection machine |
| CN118191565A (en) * | 2024-05-15 | 2024-06-14 | 龙南鼎泰电子科技有限公司 | Detection system and detection method for manufacturing circuit board of passenger car |
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- 2022-06-07 CN CN202210632144.3A patent/CN115097282A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316262A (en) * | 2023-11-30 | 2023-12-29 | 深圳市领德创科技有限公司 | Automatic FLASH chip detection machine |
| CN117316262B (en) * | 2023-11-30 | 2024-04-09 | 深圳市领德创科技有限公司 | Automatic FLASH chip detection machine |
| CN118191565A (en) * | 2024-05-15 | 2024-06-14 | 龙南鼎泰电子科技有限公司 | Detection system and detection method for manufacturing circuit board of passenger car |
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