CN115223882A

CN115223882A - Method, device and equipment for determining dislocation of wafer test mapping map and storage medium

Info

Publication number: CN115223882A
Application number: CN202210848252.4A
Authority: CN
Inventors: 张俊; 沈丹江; 任先鹏; 俞琪云
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2022-10-21

Abstract

The invention relates to a method, a device, equipment and a storage medium for determining dislocation of a wafer test mapping graph. The method comprises the following steps: acquiring a first position of a marked tube core in a wafer test mapping chart; obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along a plurality of directions, and respectively determining first qualified rates of the tube cores at the plurality of second positions; determining the dislocation condition between the wafer test mapping chart and the wafer according to the first qualified rate; the wafer test map is a layout map for mapping all die positions on the wafer according to movement of a test head. The method for determining the dislocation of the wafer test mapping chart can determine the dislocation condition between the wafer test mapping chart and the wafer, is not easy to miss inspection, and is low in labor cost.

Description

Method, device and equipment for determining dislocation of wafer test mapping map and storage medium

Technical Field

The present invention relates to the field of wafer testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for determining misalignment of a wafer test map.

Background

After the wafer is manufactured, dies (die or chip) on the wafer need to be tested so as to remove the unqualified dies and package the qualified dies. This test, also known as a central test (CP), is used to test the electrical performance and circuit function of each die. During the middle measurement, the test probe (Prober) performs a sequential walking test according to a middle measurement walking Map (CP Recipe Map), which maps all wafer positions in the physical wafer, and thus may also be referred to as a wafer test Map. The wafer test map of each wafer is related to the Reference Die (Reference Die) on the edge of the physical wafer, but due to the limited accuracy of image recognition of the test probes, the wafer test map may be misaligned (map shift) with respect to the physical wafer, which may cause a problem of error in the test result. Although the misalignment of the wafer test map with respect to the actual wafer can be found by human eyes, the misalignment is easy to miss and the labor cost is high.

Disclosure of Invention

Accordingly, the embodiments of the present application provide a method for determining misalignment of a wafer test map to solve at least one of the problems of the background art.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, this embodiment provides a method for determining misalignment of a wafer test map, where the method includes:

acquiring a first position of a marked tube core in a wafer test mapping chart;

obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along a plurality of directions, and respectively determining first qualified rates of the tube cores at the plurality of second positions;

determining the dislocation condition between the wafer test mapping chart and the wafer according to the first qualified rate; the wafer test map is a layout map for mapping all die positions on the wafer according to the movement of the test head.

Optionally, the obtaining that the first position is integrally moved in the wafer test map along multiple directions by multiple preset distances respectively and then corresponds to multiple second positions in the wafer test map includes:

obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position integrally moves for a plurality of times of preset distances in a first direction, a second direction, a third direction and a fourth direction in the wafer test mapping chart respectively; wherein the first direction is opposite to the second direction, the third direction is opposite to the fourth direction, and the first direction is perpendicular to the third direction.

Optionally, the preset distance of each movement is equal to a distance between two adjacent dies in the wafer test map in the direction of the current overall movement.

Optionally, the number of movements in any direction in the multiple integral movements of the preset distance is less than or equal to half of the number of dies covered by one wafer exposure.

Optionally, the determining the first yield of the dies located at the plurality of second positions respectively includes:

and acquiring the test results of the plurality of dies at the second position aiming at each second position, and determining the first qualified rate according to the qualified quantity and the total quantity of the dies in the test results.

Optionally, the determining, according to the first yield, a misalignment between the wafer test map and the wafer includes:

if any one first qualified rate is less than one-half second qualified rate, dislocation exists between the wafer test mapping chart and the wafer;

or, if any one of the first qualified rates is smaller than a preset value, a dislocation exists between the wafer test mapping chart and the wafer; the second yield is the yield of all dies of the wafer currently tested.

Optionally, the obtaining a first position of the marked die in the wafer test map includes:

scanning the wafer test map;

coordinates of a marked die in a wafer test map in the wafer test map are obtained.

In a second aspect, there is provided an apparatus for determining misalignment of a wafer test map, the apparatus comprising:

the obtaining module is used for obtaining a first position of the marking tube core in the wafer test mapping chart;

the first determining module is used for acquiring a plurality of second positions in the wafer test mapping chart corresponding to the first position after the first position is integrally moved for a plurality of times of preset distances in a plurality of directions in the wafer test mapping chart, and respectively determining first qualified rates of the dies located at the plurality of second positions;

and the second determining module is used for determining the dislocation condition between the wafer test mapping chart and the wafer according to the first qualified rate.

In a third aspect, an apparatus is provided in this embodiment, the apparatus comprising: a memory, a communication bus, and a processor, wherein:

the memory is used for storing a program of a method for determining the dislocation of the wafer test mapping;

the communication bus is used for realizing connection communication between the memory and the processor;

the processor is configured to execute a method program for determining wafer test map misalignment to implement any of the above method steps.

In a fourth aspect, the present embodiments provide a computer readable storage medium having stored thereon an executable program which, when executed by a processor, implements the steps of any of the methods described above.

The method for determining the dislocation of the wafer test mapping diagram provided by the embodiment of the application comprises the following steps: acquiring a first position of a marked tube core in a wafer test mapping chart; obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along a plurality of directions, and respectively determining first qualified rates of the tube cores at the plurality of second positions; and determining the dislocation condition between the wafer test mapping chart and the wafer according to the first qualified rate. According to the method for determining the wafer test mapping map dislocation, the dislocation condition between the wafer test mapping map and the wafer can be determined by obtaining the test qualified rate corresponding to a plurality of positions of the marked tube core after the marked tube core integrally moves for a plurality of times of preset distances along a plurality of directions in the wafer test mapping map. Therefore, the method for determining the dislocation of the wafer test mapping chart can determine the dislocation condition between the wafer test mapping chart and the wafer, is not easy to miss detection, and is low in labor cost.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic flowchart illustrating a method for determining misalignment of a wafer test map according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a wafer test map without misalignment in the method for determining misalignment of a wafer test map according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a wafer test map with misalignment in the method for determining misalignment of a wafer test map according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an apparatus for determining misalignment of a wafer test map according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of an apparatus in a method for determining misalignment of a wafer test map according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, can be practiced otherwise than as specifically described.

To solve the technical problems in the related art, an embodiment of the present application provides a method for determining a misalignment of a wafer test map, where the method may be implemented by a test device under test, where the test device under test needs to be installed with corresponding software, or implemented by other similar computers, as shown in fig. 1, and the method includes:

step 101: acquiring a first position of a marked tube core in a wafer test mapping chart;

step 102: obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along a plurality of directions, and respectively determining first qualified rates of the tube cores at the plurality of second positions;

step 103: and determining the dislocation condition between the wafer test mapping chart and the wafer according to the first qualified rate.

Here, the wafer test map is a layout map for mapping all die locations on the wafer according to which a test head is moved. Namely, the wafer test mapping map is a middle test walking position virtual map generated by the middle test device according to the wafer to be tested, and the generated wafer test mapping map is relatively independent from the real wafer and does not change any more in the test process. The marked die is an abnormal die on the wafer identified before testing, corresponding marking is carried out on the wafer test mapping chart, and testing is not needed in the testing process. There are typically multiple marking dies in the wafer, and thus, the first position here may be a position of one die or a layout position of multiple dies. Accordingly, the same is true for the second positions, and the plurality of second positions refers to a plurality of second positions in a plurality of directions, that is, the plurality of second positions refers to second positions in a plurality of directions. For the purpose of distinguishing from the wafer test map, the wafer may also be referred to as a physical wafer, and the wafer and the physical wafer are mentioned as one meaning hereinafter. The test head here may be a test probe as described above.

In the embodiment of the present application, the reason why the wafer test mapping map is misaligned with respect to the physical wafer is: before the intermediate test, a wafer test mapping chart is made of a first wafer to be tested, and the position of a marked die (mark die) is marked on the wafer test mapping chart. The wafer test map is generated by the specification of the wafer to be tested and identifying the locations of the reference dies. The wafer test map corresponding to the first wafer to be tested generally has no misalignment due to manual identification of the reference die. The wafer test mapping map is automatically formed by the image recognition of the reference die position of the test probe on the basis of the first wafer test mapping map of the same batch of wafers, so that the dislocation (map shift) of the wafer test mapping map relative to the real wafer can be caused, because the accuracy of the image recognition of the test probe is limited or the positioning device of the wafer has errors. According to the identification principle of the test probe and the positioning device of the wafer, the dislocation distance of the wafer test mapping image relative to the physical wafer is integral multiple of the distance between the adjacent tube cores. That is, the wafer test map has a dislocation relative to the physical wafer, the position of any one of the mapped die in the wafer test map has a difference of 1-N times the distance between the adjacent die and the die in the physical wafer, and N is a positive integer.

For convenience of understanding, the misalignment of the wafer test map is described with reference to fig. 2 and 3, and fig. 2 and 3 are schematic diagrams of a wafer test map without misalignment and a wafer test map with misalignment in the method for determining the misalignment of the wafer test map according to the embodiment of the present application. As shown in fig. 2, the outermost circular thick line frame is a frame of the real wafer, and the circular thin line frame next to the circular thick line frame is a frame of the wafer test map. The gaps of the two frames at the upper, lower, left and right sides are relatively uniform, so that the wafer test mapping graph has no dislocation relative to the real wafer. The reference die position in the figure is a black dot on the upper edge, the coordinate is set to be (0, 0), a plurality of white small blocks in the figure are used for marking the position mapping of the die, the shape is square, and the reference die position is set to be not tested during testing without influencing the accuracy of the test result.

As shown in fig. 3, the outermost circular thick line frame is a frame of the real wafer, and the circular thin line frame next to the circular thick line frame is a frame of the wafer test map. The gap between the two frames on the left side is smaller than the gap on the right side, even on the left side, the frame of the wafer test mapping chart is already collided with or exceeds the frame of the physical wafer, and therefore the wafer test mapping chart is misplaced relative to the physical wafer. The reference die positions in the figure are two small black dots on the upper edge, the left side is the reference die defined by the wafer test map, the coordinates of the wafer test map are (0, 0), the right side is the reference die defined by the physical wafer and is mapped on the wafer test map, and the coordinates of the wafer test map are (1, 0), namely, the positions of the two reference dies are staggered, and the staggered distance is the distance between the two adjacent dies. The two reference die positions are misaligned, which causes the whole wafer test map to be misaligned relative to the physical wafer, i.e., the positions of the marked dies are also misaligned. In the drawing, a plurality of white small blocks are position mapping of marked dies, and due to the misalignment, the positions of the marked dies mapped in the real wafer to the wafer test mapping map are the right ends of the white small blocks, but in the wafer test mapping map, the left ends of the white small blocks are mistaken as the positions of the marked dies, so that the dies at the positions of the right ends of the white small blocks are tested during testing, namely the dies which are not originally tested are tested, but the dies which are originally required to be tested, namely the dies at the positions of the left ends of the white small blocks are not tested. Therefore, the accuracy of the test result is affected by the misalignment of the wafer test map with respect to the physical wafer, and therefore, it is necessary to determine whether the wafer test map is misaligned with respect to the physical wafer.

In fig. 3, the misalignment distance of the wafer test map with respect to the physical wafer is the distance between two adjacent dies, and since the dies are basically close to each other, the misalignment distance of the wafer test map with respect to the physical wafer can also be considered as the width of one die, in fig. 3, the marked die position in the wafer test map and the die position of the physical wafer are basically connected together to form a rectangular white small block, that is, two squares form a rectangle. It can be understood that the wafer test map may have a staggered distance with respect to the physical wafer, which may be 2 times, 3 times, etc. the distance between two adjacent dies, so that the marked die position in the wafer test map and the die position of the physical wafer are not connected together.

The principle of the method for determining the dislocation of the wafer test mapping provided by the embodiment of the application is as follows: if the wafer test mapping image has dislocation relative to the physical wafer, the position of the marked die in the wafer test mapping image can wholly shift to a certain direction, namely the position of the marked die in the wafer test mapping image and the position of the marked die in the physical wafer are dislocated. During the test, the following occurs: marked dies on the wafer are tested while some unmarked dies on the wafer are untested. The results of misleading marked dies are mostly poor, i.e., the yield is very low or much less than the yield of the wafer as a whole. And because the misalignment of the wafer test map relative to the physical wafer is an overall offset, the distribution of the misdetected marked dies on the wafer is unchanged. Therefore, the method for determining the misalignment of the wafer test map may be: and searching positions of a plurality of dies with the yield rate far smaller than the whole wafer yield rate and consistent with the distribution of the marked dies in the wafer test mapping chart. Therefore, the test yield at the plurality of positions can be respectively obtained by obtaining the plurality of positions of the marked die after the marked die integrally moves for a plurality of times by the preset distance along a plurality of directions in the wafer test mapping chart. If the test yield at any position is far less than the overall yield of the wafer, it indicates that the correct position of the marked die in the physical wafer is found, and it indicates that the wafer test mapping chart has dislocation relative to the physical wafer. If the test yield at all positions is not much less than the whole wafer yield, even close to the whole wafer yield, the wafer test mapping chart has no dislocation relative to the physical wafer.

Note that: the above conclusion of no misalignment is only that of the test equipment. Further judgment by the operator or a technician involved is required as to whether there is actually no misalignment. For example, the test result indicates that the wafer test map has no misalignment relative to the physical wafer, and although the conclusion may be incorrect, the probability of actually generating the misalignment may be considered to be relatively low, for example, the probability of the misalignment may be less than 1%. The method of the embodiment of the application has many reasons for determining errors, for example, there are dislocations, but the distance between the dislocations is very large, so that the positions of the marked die cannot be found at a plurality of positions after the overall movement for obtaining a plurality of preset distances. As another example, the original test result is recorded incorrectly, or the test result itself is incorrect due to the failure of the test equipment, etc., but in general, the probability of these situations is relatively low.

According to the method for determining the wafer test map dislocation, the dislocation condition between the wafer test map and the wafer can be determined by obtaining the test yield corresponding to the position of the marked tube core after the marked tube core integrally moves for multiple times along multiple directions for a preset distance respectively in the wafer test map. Therefore, the method for determining the dislocation of the wafer test mapping chart can determine the dislocation condition between the wafer test mapping chart and the wafer, is not easy to miss detection, and is low in labor cost.

In some embodiments, in step 102, the obtaining that the first position corresponds to a plurality of second positions in the wafer test map after performing a plurality of integral movements of a preset distance in a plurality of directions in the wafer test map respectively includes:

obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along a first direction, a second direction, a third direction and a fourth direction in the wafer test mapping chart respectively; wherein the first direction is opposite to the second direction, the third direction is opposite to the fourth direction, and the first direction is perpendicular to the third direction.

Namely, the plurality of directions include a first direction, a second direction, a third direction and a fourth direction, and the relative relationship among the four directions is as follows: the first direction is opposite to the second direction, the third direction is opposite to the fourth direction, and the first direction is perpendicular to the third direction. Therefore, the four directions can be considered as X and Y directions in a rectangular plane coordinate system, i.e., X positive direction, X negative direction, Y positive direction, and Y negative direction. The four directions are set in relation to the directions of misalignment between the wafer test map and the wafer, and in general, the misalignment is in the four directions.

In some embodiments, in step 102, the preset distance of each movement is equal to a distance between two adjacent dies in the wafer test map in the direction of the current overall movement. As mentioned above, the misalignment distance of the wafer test map relative to the physical wafer is typically 1-N times the pitch between adjacent dies, where N is a positive integer. Thus, the distance of each movement is set to the pitch of two adjacent dies in the direction of movement. Thus, there is no omission in the determination process.

In some embodiments, in step 102, the number of movements in any direction of the plurality of integral movements of the preset distance is less than or equal to half of the number of dies covered by one wafer exposure. Here, the number of times of movement in either direction is set based on the accuracy of image recognition by the test probe and the positioning accuracy by the positioning device of the wafer, and a sufficient margin is left so that omission does not occur and efficiency is higher. Generally, the number of dies covered by a single wafer exposure is related to the size of the wafer, and the misalignment distance of the wafer test map relative to the physical wafer is also related to the size of the wafer, but in general intermediate-test equipment, the misalignment distance of the wafer test map relative to the physical wafer is generally not more than half of the number of dies covered by a single wafer exposure, otherwise, only the intermediate-test equipment fails or needs to be scrapped.

In some embodiments, the step 102 of separately determining a first yield of the dies located at the plurality of second locations comprises:

and acquiring the test results of the plurality of dies at the second position aiming at each second position, and determining the first qualified rate according to the qualified quantity and the total quantity of the dies in the test results. For example, there are 100 marked dies on the wafer, and each of the second positions has a position corresponding to 100 dies, and there are 100 test results, and if 90 of them pass, the first yield is 90%, and if 10 of them pass, the first yield is 10%.

In some embodiments, the determining the misalignment between the wafer test map and the wafer according to the first yield in step 103 includes:

if any one first qualified rate is less than one-half second qualified rate, dislocation exists between the wafer test mapping chart and the wafer; the second yield is the yield of all dies of the wafer currently tested.

For example, the second yield is 80%, and if any one of the first yields is less than 40%, there is a misalignment between the wafer test map and the wafer.

Otherwise, if all the first qualified rates are greater than or equal to one-half of the second qualified rate, the wafer test mapping chart and the wafer do not have dislocation. For example, the second yield is 80%, and if all the first yields are greater than or equal to 40%, there is no misalignment between the wafer test map and the wafer. As mentioned above, this is the conclusion given by the test equipment that further judgment by the operator or a technician involved is required as to whether there is actually no misalignment.

In some embodiments, in step 103, the determining a misalignment between the wafer test map and the wafer according to the first yield may further include:

if any one of the first qualified rates is smaller than the preset value, dislocation exists between the wafer test mapping chart and the wafer.

The preset value may be the second yield as described above, or may be other values, because the yield of the marked die is much lower than the normal value, and therefore, the preset value may be set to a fixed value of 30% or 20% to simplify the calculation process.

In some embodiments, in step 101, acquiring a first position of the marked die in the wafer test map includes:

scanning the wafer test map;

Scanning, as used herein, is understood to mean traversing the records in a predetermined order, which may be from top to bottom and from left to right, and recording the coordinates of the location of the corresponding marked die when the location of the marked die is encountered. The coordinates here may be coordinates of a rectangular plane coordinate system, i.e., a horizontal axis X and a vertical axis Y, for example, the coordinates of the reference die described above represent (0, 0), the coordinate value of the X axis represents 0, and the coordinate value of the Y axis represents 0.

The embodiment of the present application further provides a device 400 for determining a misalignment of a wafer test map, as shown in fig. 4, the device 400 includes an obtaining module 401, a first determining module 402, and a second determining module 403; wherein,

the obtaining module 401 is configured to obtain a first position of a marked die in a wafer test map;

the first determining module 402 is configured to obtain a plurality of second positions in the wafer test map corresponding to the first position after the first position is moved integrally in a plurality of directions by a preset distance, and determine first yield of dies located in the plurality of second positions;

the second determining module 403 is configured to determine a misalignment between the wafer test map and the wafer according to the first yield.

In some embodiments, the first determining module 402 is specifically configured to:

Namely, the plurality of directions comprise a first direction, a second direction, a third direction and a fourth direction, and the relative relationship among the four directions is as follows: the first direction is opposite to the second direction, the third direction is opposite to the fourth direction, and the first direction is perpendicular to the third direction. Therefore, the four directions can be regarded as X and Y directions in a rectangular plane coordinate system, that is, X positive direction, X negative direction, Y positive direction, and Y negative direction.

In some embodiments, the first determining module 402 is further configured to: and obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along the first direction, the second direction, the third direction and the fourth direction in the wafer test mapping chart. And the preset distance of each movement is equal to the distance between two adjacent die cores in the wafer test mapping chart in the direction of the whole movement. As mentioned above, the misalignment distance of the wafer test map relative to the physical wafer is typically 1-N times the pitch between adjacent dies, where N is a positive integer. Therefore, the distance of each movement is set to the pitch of the adjacent two dies in the moving direction. Thus, there is no omission in the determination process.

In some embodiments, the first determining module 402 is further configured to: and obtaining a plurality of second positions of the first position in the wafer test mapping chart after the first position is integrally moved for a plurality of times of preset distances along the first direction, the second direction, the third direction and the fourth direction in the wafer test mapping chart. And the moving times in any direction in the integral movement of the multiple preset distances are less than or equal to half of the number of the dies covered by one wafer exposure. Here, the number of times of movement in either direction is set based on the accuracy of image recognition by the test probe and the positioning accuracy by the positioning device of the wafer, and a sufficient margin is left so that omission does not occur and efficiency is higher.

In some embodiments, the first determining module 402 is further configured to:

and acquiring the test results of the plurality of dies at the second position aiming at each second position, and determining the first qualified rate according to the qualified quantity and the total quantity of the dies in the test results. For example, there are 100 marked dies on the wafer, and each of the second positions has a position corresponding to 100 dies, and there are 100 test results, wherein if there are 90 qualified dies, the first yield is 90%, and if there are 10 qualified dies, the first yield is 10%.

In some embodiments, the second determining module 403 is specifically configured to:

if any first qualified rate is less than one-half second qualified rate, determining that dislocation exists between the wafer test mapping chart and the wafer; the second yield is the yield of all dies of the wafer currently tested.

For example, the second yield is 80%, and if any one of the first yields is less than 40%, it is determined that there is a misalignment between the wafer test map and the wafer. That is, if the wafer test map has no misalignment, the first yield of any one of the wafer test maps is relatively close to 80% and not lower than 40%.

In some embodiments, the second determining module 403 is further configured to:

and if any first qualified rate is smaller than the preset value, determining that dislocation exists between the wafer test mapping chart and the wafer.

In some embodiments, the obtaining module 401 is specifically configured to:

scanning the wafer test map;

Scanning, as used herein, is understood to mean traversing the records in a predetermined order, which may be from top to bottom and from left to right, and recording the coordinates of the location of the corresponding marked die when the location of the marked die is encountered.

The apparatus 400 in the embodiment of the present invention may be a device installed in the test equipment, or may be a separate device connected to and communicating with the test equipment.

In some embodiments, the apparatus 400 according to the embodiment of the present invention may be configured to execute the method for determining the wafer test map misalignment described in the foregoing embodiments, and certainly may also include a module configured to execute any flow and/or step in the method for determining the wafer test map misalignment described in the foregoing embodiments, which is not described again for brevity.

The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus according to the invention, reference is made to the description of the embodiments of the method according to the invention for understanding.

Each module included in the embodiment of the invention can be realized by a processor in the test equipment; of course, the test can also be realized by logic circuits in the test equipment; in implementation, the processor may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.

An embodiment of the present application further provides an apparatus 500, as shown in fig. 5, where the apparatus 500 includes: a memory 501, a communication bus 502, and a processor 503, wherein:

the memory 501 is used for storing a program of a method for determining the misalignment of the wafer test map;

the communication bus 502 is used for realizing connection communication between the memory 501 and the processor 503;

the processor 503 is configured to execute the program of the method for determining the wafer test map misalignment, so as to implement any one or more steps of the method for determining the wafer test map misalignment as described above.

Specifically, the processor 503 may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like; the memory 501 may be implemented by any type of volatile or non-volatile storage device, or combination thereof. For example, FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, removable memory, or any combination thereof. .

Specifically, the apparatus 500 further comprises: an external communication interface 504, a test probe 505, and a display 506, wherein:

the external communication interface 504 may be used to communicate with the outside, the external terminal includes a server or a client, and the external communication interface 504 may include a wired interface and a wireless interface;

the test probes 505 may be used to test the electrical performance and circuit function of each die;

the display 506 may be used to display a wafer test map, probe test positions, and test results.

The above description of the embodiment of the apparatus 500 is similar to the description of the method embodiment described above with similar benefits to the method embodiment. For technical details not disclosed in the apparatus 500 of the present embodiment, please refer to the description of the method embodiment of the present invention for understanding.

Embodiments of the present application further provide a computer-readable storage medium, which stores thereon an executable program, and when the executable program is executed by a processor, the executable program implements any one or any plurality of steps of the method for determining the wafer test map misalignment as described above.

The computer-readable storage medium may be implemented by any type of volatile or non-volatile storage device, or combination thereof. The nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random Access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical Disc, or a Read Only Disc (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), synchronous Static Random Access Memory (SSRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), direct bus Dynamic Random Access Memory (DRM), and the like. The storage media described in the embodiments of the present application are intended to comprise, without being limited to, these and any other suitable types of memory.

The above description of the computer-readable storage medium embodiments is similar to the description of the method embodiments described above, with similar beneficial effects as the method embodiments. For technical details not disclosed in the computer-readable storage medium of the present embodiment, please refer to the description of the method embodiment of the present invention for understanding.

In the embodiments of the present invention, if the terms "first \ second \ third" are used, similar objects are distinguished only, and a specific ordering for the objects is not represented, it should be understood that "first \ second \ third" may be interchanged with a specific order or sequence as the case may be.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not imply an order of execution, and the order of execution of the processes should be determined by their functions and internal logics, and should not limit the implementation processes of the embodiments of the present invention in any way. The above-mentioned serial numbers of the embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and in actual implementation, there may be other division ways, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or in other forms.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules; the network module can be located in one place or distributed on a plurality of network modules; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all the functional modules in the embodiments of the present invention may be integrated into one processing module, or each functional module may be separately used as one module, or two or more functional modules may be integrated into one module; the integrated module can be realized in a hardware mode, and can also be realized in a mode of hardware and a software functional module.

Those of ordinary skill in the art will understand that: all or part of the steps of implementing the above method embodiments may be implemented by hardware associated with program instructions, and the program may be stored in a computer-readable storage medium, and when executed, performs the steps including the above method embodiments.

Alternatively, the above-described integrated module of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Likewise, various features of the above embodiments may also be combined in any combination to form additional embodiments of the invention that may not be explicitly described. Therefore, the above examples only represent some embodiments of the present invention, and do not limit the scope of the present invention.

Claims

1. A method for determining misalignment of a wafer test map, the method comprising:

acquiring a first position of a marked tube core in a wafer test mapping chart;

2. The method as claimed in claim 1, wherein the obtaining the first position corresponds to a plurality of second positions in the wafer test map after performing a plurality of integral movements along a plurality of directions for a predetermined distance, respectively, in the wafer test map comprises:

3. The method as claimed in claim 1 or 2, wherein the predetermined distance for each movement is equal to a distance between two adjacent dies in the wafer test map in the direction of the global movement.

4. The method as claimed in claim 3, wherein the number of movements in any direction of the overall movement of the predetermined distance is less than or equal to half of the number of dies covered by one wafer exposure.

5. The method as claimed in claim 1 or 2, wherein the determining the first yield of the dies located at the plurality of second positions comprises:

6. The method as claimed in claim 1, wherein the determining the misalignment between the wafer test map and the wafer according to the first yield comprises:

if any one first qualified rate is less than one half of a second qualified rate, dislocation exists between the wafer test mapping chart and the wafer;

or if any one first qualified rate is smaller than a preset value, dislocation exists between the wafer test mapping chart and the wafer; the second yield is the yield of all dies of the wafer currently tested.

7. The method as claimed in claim 1 or 2, wherein the obtaining the first position of the marked die in the wafer test map comprises:

scanning the wafer test map;

8. An apparatus for determining misalignment of a wafer test map, the apparatus comprising:

9. An apparatus, characterized in that the apparatus comprises: a memory, a communication bus, and a processor, wherein:

the memory is used for storing a program of the determining method for the dislocation of the wafer test mapping chart;

the processor is configured to execute a method program for determining wafer test map misalignment to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, having stored thereon an executable program which, when executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.