CN117078597A - MAP graph-based wafer test offset detection method, system and storage medium - Google Patents

MAP graph-based wafer test offset detection method, system and storage medium Download PDF

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Publication number
CN117078597A
CN117078597A CN202310894440.5A CN202310894440A CN117078597A CN 117078597 A CN117078597 A CN 117078597A CN 202310894440 A CN202310894440 A CN 202310894440A CN 117078597 A CN117078597 A CN 117078597A
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map
overall yield
arc
annular region
wafer test
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周乃新
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Zhejiang Quean Technology Co ltd
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Zhejiang Quean Technology Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/0002Inspection of images, e.g. flaw detection
    • G06T7/0004Industrial image inspection
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/60Analysis of geometric attributes
    • G06T7/62Analysis of geometric attributes of area, perimeter, diameter or volume
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/30Subject of image; Context of image processing
    • G06T2207/30108Industrial image inspection
    • G06T2207/30148Semiconductor; IC; Wafer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses a wafer test offset detection method, a system and a storage medium based on MAP, which comprise the following steps: acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively; according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region; dividing the target annular region into a plurality of identical arc regions, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated when the difference between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference. The invention can find the map shift generated in the wafer test process in time, and avoid causing great economic loss while improving the judgment accuracy.

Description

MAP graph-based wafer test offset detection method, system and storage medium
Technical Field
The present invention relates to the field of integrated circuit testing technologies, and in particular, to a wafer test offset detection method, system and storage medium based on MAP.
Background
In the wafer test, the wafer is tested after the test head is aligned with the probe station, but if deviation occurs between the test head and the wafer alignment position on the probe station, MAP shift (MAP shift) occurs, and the MAP generated at this time is actually in error with the wafer correspondence, so that in the wafer packaging link, the original test result is shifted when corresponding to the actual wafer, and the test result is completely invalid.
Accordingly, there is a need to provide a solution to the above-mentioned problems.
Disclosure of Invention
In order to solve the technical problems, the invention provides a wafer test offset detection method, a system and a storage medium based on MAP.
The wafer test offset detection method based on the MAP comprises the following steps:
acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively;
according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region;
dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
The wafer test offset detection method based on the MAP has the following beneficial effects:
the method can detect the wafer test result, discover the map shift generated in the wafer test process in time, improve the judgment accuracy of the map shift, and avoid causing great economic loss.
Based on the scheme, the wafer test offset detection method based on the MAP can be improved as follows.
Further, the process of calculating the overall yield of any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
Further, the step of dividing the target annular region into a plurality of arc-shaped regions with the same size includes:
constructing a rectangular coordinate system by taking a DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis;
dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
Further, the preset overall yield is 50%.
Further, the preset difference is 50%.
The wafer test offset detection system based on the MAP has the following technical scheme:
comprising the following steps: the device comprises an acquisition module, a processing module and a detection module;
the acquisition module is used for: acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively;
the processing module is used for: according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region;
the detection module is used for: dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
The wafer test offset detection system based on the MAP has the following beneficial effects:
the system can detect the wafer test result, discover the map shift generated in the wafer test process in time, and avoid causing great economic loss while improving the judgment accuracy of the map shift.
Based on the scheme, the wafer test offset detection system based on the MAP can be improved as follows.
Further, the process of calculating the overall yield of any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
Further, the detection module is specifically configured to:
constructing a rectangular coordinate system by taking a DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis;
dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
Further, the preset overall yield is 50%.
The technical scheme of the storage medium is as follows:
the storage medium stores instructions that, when read by a computer, cause the computer to perform the steps of the MAP-based wafer test offset detection method of the present invention.
Drawings
FIG. 1 is a schematic flow chart of an embodiment of a wafer test offset detection method based on MAP provided by the invention;
fig. 2 is a schematic diagram of a wafer test principle in an embodiment of a wafer test offset detection method based on MAP provided by the present invention;
FIG. 3 is a diagram showing a first example of a MAP in an embodiment of a MAP-based wafer test offset detection method according to the present invention;
FIG. 4 is a diagram showing a second example of a MAP in an embodiment of a MAP-based wafer test offset detection method provided by the invention;
FIG. 5 is a third exemplary MAP of a MAP-based wafer test offset detection method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an embodiment of a wafer test offset detection system based on MAP provided in the present invention.
Detailed Description
Fig. 1 is a schematic flow chart of an embodiment of a wafer test offset detection method based on MAP provided by the present invention. As shown in fig. 1, the method comprises the following steps:
step 110: and acquiring an MAP of the wafer to be detected, and calculating the overall yield of the annular region between the outermost ring of the MAP and each inner ring.
Wherein, (1) the wafer test is completed by the cooperation of the tester and the probe station. As shown in fig. 2, a wafer to be tested (water) is placed on a Probe station, and when a test instruction is issued by a tester, a Probe of a Probe Card (Probe Card) is contacted with each chip (DIE) on the wafer to be tested, so as to determine whether each DIE is good or bad. (2) Fig. 3 is a schematic diagram of a MAP diagram in which no offset occurs, each of the small squares in fig. 3 represents one DIE, and the number (BIN value) on each DIE represents the quality of the DIE. Where a BIN value of 1 indicates a DIE that passed the test (good chip) and a BIN value of 2 indicates a DIE that failed the test (bad chip).
Fig. 4 is a schematic diagram of a MAP in which an offset occurs. By comparing fig. 3 and fig. 4, the appearance of the two is not distinguished, i.e. the wafer shape is not changed, but the correspondence of each chip (DIE) on the MAP is shifted. At this time, the probe card is shifted to the right when the wafer to be tested is tested, and the probe card in the test area on the right side of the wafer is shifted out of the wafer, so that the DIE with the BIN value of 2 in the test result on the left side of the wafer is reduced, the edge on the right side may actually be shifted out of the wafer to be tested, and the BIN value of the DIE outside the wafer to be tested is also changed to 2, so that the DIE with the BIN value of 2 is significantly more. At this time, if the user uses the map shift test result as a basis, it is obvious that the test result of each did is not a real result.
Step 120: and according to the size of the radius difference value between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as the target annular region.
Wherein, (1) default overall yield is 50%, and can be set according to actual requirements without limitation. (2) The overall yield of the target annular region is greater than or equal to 50%.
Step 130: dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
Wherein (1) the size of the arc-shaped region is determined according to the number of divisions. For example, when the target annular region is divided into 4 arc-shaped regions of the same size, then the size of each arc-shaped region is 1/4 of the target annular region. (2) The preset difference is set to be 50% by default, and can be set according to actual requirements without limitation.
Preferably, the process of calculating the overall yield of any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
For example, a certain area has 100 DIE, where the DIE with BIN of 1 is composed of 40 DIE, and the overall yield of the area is: 40/100=40%.
Preferably, the step of dividing the target annular region into a plurality of arc-shaped regions of the same size includes:
and constructing a rectangular coordinate system by taking the DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis.
Dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
As shown in fig. 5, each arc area is located in one quadrant of the rectangular coordinate system, and the arc areas in each quadrant are the same and continuous in size. As can be seen from fig. 5, the overall yield in the first and fourth quadrants is significantly smaller than that in the second and third quadrants. And if the difference between the maximum overall yield (80%) and the minimum overall yield (20%) is larger than the preset difference, determining that the wafer to be detected is deviated in the wafer test.
The technical scheme of the embodiment can detect the wafer test result, discover the map shift generated in the wafer test process in time, and avoid causing great economic loss while improving the judgment accuracy of the map shift.
Fig. 6 is a schematic structural diagram of an embodiment of a wafer test offset detection system based on MAP provided in the present invention. As shown in fig. 6, the system 200 includes: an acquisition module 210, a processing module 220, and a detection module 230.
The obtaining module 210 is configured to: acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively;
the processing module 220 is configured to: according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region;
the detection module 230 is configured to: dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
Preferably, the process of calculating the overall yield of any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
Preferably, the detection module 230 is specifically configured to:
constructing a rectangular coordinate system by taking a DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis;
dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
Preferably, the preset overall yield is 50%.
The technical scheme of the embodiment can detect the wafer test result, discover the map shift generated in the wafer test process in time, and avoid causing great economic loss while improving the judgment accuracy of the map shift.
The steps for implementing the corresponding functions by the parameters and the modules in the embodiment of the MAP-based wafer test offset detection system 200 provided in the present invention may refer to the parameters and the steps in the embodiment of the MAP-based wafer test offset detection method provided in the foregoing, and are not described herein.
The storage medium provided by the embodiment of the invention comprises: the storage medium stores instructions that, when read by a computer, cause the computer to execute steps of the wafer test offset detection method based on MAP, and specifically, reference may be made to each parameter and step in the embodiment of the wafer test offset detection method based on MAP provided above, which are not described herein.
Computer storage media such as: flash disk, mobile hard disk, etc.
Those skilled in the art will appreciate that the present invention may be implemented as a method, system, and storage medium.
Thus, the invention may be embodied in the form of: either entirely hardware, entirely software (including firmware, resident software, micro-code, etc.), or entirely software, or a combination of hardware and software, referred to herein generally as a "circuit," module "or" system. Furthermore, in some embodiments, the invention may also be embodied in the form of a computer program product in one or more computer-readable media, which contain computer-readable program code. Any combination of one or more computer readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. The wafer test offset detection method based on the MAP is characterized by comprising the following steps of:
acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively;
according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region;
dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
2. The MAP-based wafer test offset detection method of claim 1, wherein the process of calculating the overall yield of any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
3. The MAP-based wafer test offset detection method of claim 1, wherein the step of dividing the target annular region into a plurality of arc-shaped regions of the same size comprises:
constructing a rectangular coordinate system by taking a DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis;
dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
4. The MAP-based wafer test offset detection method of any one of claims 1-3, wherein the predetermined overall yield is 50%.
5. The MAP-based wafer test offset detection method of any one of claims 1-3, wherein the predetermined difference is 50%.
6. A MAP graph-based wafer test offset detection system, comprising: the device comprises an acquisition module, a processing module and a detection module;
the acquisition module is used for: acquiring an MAP of a wafer to be detected, and calculating the overall yield of an annular region between the outermost ring of the MAP and each inner ring respectively;
the processing module is used for: according to the size of the radius difference between the outermost ring and the inner ring corresponding to each annular region, arranging all the annular regions in an ascending order to obtain a target queue, and determining the annular region with the first overall yield greater than or equal to the preset overall yield in the target queue as a target annular region;
the detection module is used for: dividing the target annular region into a plurality of arc regions with the same size, obtaining the overall yield of each arc region, and judging that the wafer to be detected is deviated in the wafer test when the difference value between the highest overall yield and the lowest overall yield in all the arc regions is larger than a preset difference value.
7. The MAP-based wafer test offset detection system of claim 6, wherein the process of calculating the overall yield for any region is:
and acquiring a BIN value of each DIE in any area, and determining the ratio of the number of DIEs with BIN value of 1 in any area to the total number of DIEs in any area as the overall yield of any area.
8. The MAP-based wafer test offset detection system of claim 6, wherein the detection module is specifically configured to:
constructing a rectangular coordinate system by taking a DIE at the center point of the MAP as an origin, taking the horizontal direction as an X axis and taking the vertical direction as a Y axis;
dividing the target annular region into four arc-shaped regions by using the rectangular coordinate system; each arc-shaped area is respectively located in one quadrant of the rectangular coordinate system, and the arc-shaped areas in each quadrant are identical and continuous in size.
9. The MAP-based wafer test offset detection system of any one of claims 6-8, wherein the predetermined overall yield is 50%.
10. A storage medium having instructions stored therein that, when read by a computer, cause the computer to perform the MAP-based wafer test offset detection method of any one of claims 1 to 5.
CN202310894440.5A 2023-07-20 2023-07-20 MAP graph-based wafer test offset detection method, system and storage medium Pending CN117078597A (en)

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CN202310894440.5A CN117078597A (en) 2023-07-20 2023-07-20 MAP graph-based wafer test offset detection method, system and storage medium

Applications Claiming Priority (1)

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CN202310894440.5A CN117078597A (en) 2023-07-20 2023-07-20 MAP graph-based wafer test offset detection method, system and storage medium

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CN117078597A true CN117078597A (en) 2023-11-17

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