CN115084058A - Power semiconductor device packaging structure - Google Patents
Power semiconductor device packaging structure Download PDFInfo
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- CN115084058A CN115084058A CN202210979702.3A CN202210979702A CN115084058A CN 115084058 A CN115084058 A CN 115084058A CN 202210979702 A CN202210979702 A CN 202210979702A CN 115084058 A CN115084058 A CN 115084058A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
Abstract
The invention provides a power semiconductor device packaging structure, which comprises: a chip having a first surface and a second surface; meanwhile, welding an insulating substrate integrated with a heat dissipation micro-channel on the first surface of the chip and/or the second surface of the chip; the heat dissipation micro-channel comprises a micro-channel, an insulating layer and a first heat conduction layer from inside to outside, and cooling liquid is injected into the micro-channel; wherein the surface area of the first heat conducting layer is larger than the surface areas of the first surface and the second surface of the chip. The heat dissipation micro-channel is integrated in the insulating substrate, so that the heat dissipation performance is enhanced, the crusting thermal resistance of the packaging structure is reduced, and the stray inductance and the packaging volume in the packaging structure are effectively reduced; furthermore, the insulating layer arranged between the micro-channel and the first heat conducting layer can ensure the insulating function of the cooling liquid and the electrified part of the insulating substrate, and the use cost of the power semiconductor device is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a power semiconductor device packaging structure.
Background
The power semiconductor device is also called a power electronic device, is the basis of power electronic technology, and is also a core device constituting a power electronic conversion circuit. Power semiconductor devices are used in almost all electronic products and electronic equipment manufacturing industries. With the further development of electronic power technology, the power semiconductor device has larger current and higher power density, which inevitably causes the power semiconductor device to generate a large amount of heat during operation.
In order to avoid the burning loss of the power semiconductor device due to high temperature, the heat of the power semiconductor device must be dissipated, and the semiconductor chip is particularly important for the efficient heat dissipation of the power semiconductor device which can realize certain functions. At present, a common heat dissipation mode of a chip is to weld a radiator on one surface of a substrate so as to realize heat dissipation of the chip welded on the substrate; but the distance between the radiator and the chip is far, so that the radiating effect is poor; even if the heat radiators are welded on the two sides of the substrate to radiate the chip, the problem that the heat radiators have poor radiating effect on the chip cannot be well solved.
Therefore, how to perform better heat dissipation on the chip to achieve efficient heat dissipation of the power semiconductor device package structure becomes a research focus of those skilled in the art.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a power semiconductor device package structure to enhance the heat dissipation effect of the power semiconductor device.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a power semiconductor device package structure, comprising:
a chip having a first surface and a second surface;
an insulating substrate integrated with a heat dissipation micro-channel is welded on the first surface of the chip and/or the second surface of the chip;
the heat dissipation micro-channel comprises a micro-channel, an insulating layer and a first heat conduction layer from inside to outside, and cooling liquid is injected into the micro-channel;
wherein a surface area of the first thermally conductive layer is greater than a surface area of the first and second surfaces of the chip.
Optionally, one surface of the insulating substrate, which is welded to the surface of the chip, is made of an insulating material;
the surface of the insulating substrate, which is not welded with the surface of the chip, is made of a heat conduction material with a preset thickness;
the micro-channel is a through hole horizontally cut on the heat conduction material according to a preset size, and the through direction of the through hole is parallel to the chip;
the insulating layer is formed by a first groove added with insulating materials at the periphery of the micro-channel, and the first groove is obtained by cutting the heat conducting materials at the periphery of the micro-channel according to a preset width;
the first heat conduction layer is made of the heat conduction material left on the periphery of the insulation layer;
wherein, the preset width and the preset size are both smaller than the preset thickness.
Optionally, the power semiconductor device package structure further includes: a second thermally conductive layer;
one surface of the insulating substrate, which is welded with the surface of the chip, is made of an insulating material;
the surface of the insulating substrate, which is not welded with the surface of the chip, is made of a heat conduction material with a preset thickness;
the micro-channel is a through hole horizontally cut on the heat conduction material according to a preset size, and the through direction of the through hole is parallel to the chip;
the second heat conduction layer is formed by a second groove which is formed by depositing heat conduction materials on the periphery of the micro-channel, and the second groove is obtained by cutting the heat conduction materials on the periphery of the micro-channel according to a second preset width;
the insulating layer is formed by a first groove added with insulating materials at the periphery of the micro-channel, and the first groove is obtained by cutting the heat conducting materials at the periphery of the micro-channel according to a preset width;
the first heat conduction layer is made of the heat conduction material left on the periphery of the insulation layer;
the preset width, the second preset width and the preset size are all smaller than the preset thickness.
Optionally, the microchannel is located close to the chip.
Optionally, the number of microchannels comprises one or more.
Optionally, if the number of the microchannels comprises one, the shape of the microchannel comprises one of a square shape, a serpentine shape, a conical shape and a circular shape;
if the number of the micro-channels comprises a plurality of micro-channels, the shape of the micro-channels comprises one or more combinations of square, serpentine, conical and circular.
Optionally, the thermally conductive material of the first thermally conductive layer comprises copper or aluminum.
Optionally, the insulating material of the insulating layer includes ceramic or aluminum nitride.
Optionally, the thermally conductive material of the second thermally conductive layer comprises copper or aluminum.
Optionally, the first heat conduction layer serves as a power terminal of the power semiconductor device.
Based on the power semiconductor device packaging structure provided by the embodiment of the invention, the power semiconductor device packaging structure comprises a chip with a first surface and a second surface, and an insulating substrate integrated with a heat dissipation micro-channel is welded on the first surface of the chip and/or the second surface of the chip; the heat dissipation micro-channel comprises a micro-channel, an insulating layer and a first heat conduction layer from inside to outside, and cooling liquid is injected into the micro-channel. In this scheme, through the heat dissipation microchannel on insulating substrate, make the heat conduction to first heat-conducting layer with insulating substrate welded chip production, the first heat-conducting layer of rethread conducts the microchannel with the heat to carry out high-efficient heat dissipation to the chip through the coolant liquid in the microchannel. The heat dissipation micro-channel is integrated in the insulating substrate, so that the heat dissipation performance is enhanced, the crusting thermal resistance of the packaging structure is reduced, and the stray inductance and the packaging volume in the packaging structure are effectively reduced; furthermore, the insulating layer arranged between the micro-channel and the first heat conducting layer can ensure the insulating function of the cooling liquid and the electrified part of the insulating substrate, and the use cost of the power semiconductor device is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of one embodiment of the schematic structure of FIG. 1 taken along the line A-A1;
FIG. 4 is a cross-sectional view of one embodiment of the schematic structure of FIG. 2 taken along the line B-B1;
FIG. 5 is a cross-sectional view of yet another embodiment of the schematic structure of FIG. 1 taken along the line A-A1;
FIG. 6 is a cross-sectional view of yet another embodiment of the schematic structure of FIG. 2 taken along the line B-B1;
fig. 7 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view of one embodiment of the schematic structure of FIG. 7 taken along the direction C-C1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As shown in fig. 1 to 8, an embodiment of the present invention provides a power semiconductor device package structure, including: a chip 1 and an insulating substrate 2.
The chip 1 has a first surface and a second surface.
The first surface and the second surface are two opposite surfaces.
The insulating substrate 2 is integrated with a heat dissipation micro-channel.
The number of the insulating substrates 2 may be one or two.
As shown in fig. 1, when the number of the insulating substrates 2 is one, the insulating substrate 2 is soldered to the first surface or the second surface of the chip 1.
As shown in fig. 2, when the number of the insulating substrates 2 is two, the insulating substrates 2 are respectively bonded to the first surface and the second surface of the chip 1.
The welding method may be preferably sintering.
As shown in fig. 3, the heat dissipation micro-channel comprises, from inside to outside, a micro-channel 6, an insulating layer 4 and a first heat conduction layer 3, and a cooling liquid is injected into the micro-channel 6.
The surface area of the first heat conduction layer 3 is larger than the surface areas of the first surface and the second surface of the chip 1, so that heat on the chip 1 is conducted to the micro-channel 6 through the first heat conduction layer 3 to the maximum extent, and the heat is taken away by using a cooling liquid circulating in the micro-channel 6.
In one embodiment of the present invention, the microchannel 6 has a channel inlet and a channel outlet, the channel inlet is connected to the water inlet pipe of the external water-cooling circulation system, and the channel outlet is connected to the water outlet pipe of the external water-cooling circulation system, so as to realize the injection and circulation flow control of the cooling liquid under the control of the external water-cooling circulation system.
In an embodiment of the present invention, the cooling liquid may be a conventional alcohol-type cooling liquid, a glycerin-type cooling liquid, or a glycol-type cooling liquid, but of course, those skilled in the art may also use other specific cooling liquids according to actual needs, and the present invention is not limited thereto.
In the power semiconductor device package structure disclosed in the embodiment of the present invention, when heat is generated on the chip 1, the heat is sequentially conducted to the first heat conducting layer 3, the insulating layer 4, and the micro channel 6 through the first surface and/or the second surface of the chip 1 welded to the insulating substrate 2, so that the heat is taken away by the cooling liquid circulating in the micro channel 6, thereby achieving efficient heat dissipation of the chip 1 and reducing the junction-shell thermal resistance of the package structure; meanwhile, stray inductance inside the packaging structure and the packaging volume are reduced.
In one embodiment of the present invention, an insulating material is used on the surface of the insulating substrate 2 to be bonded to the surface of the chip 1.
In an embodiment of the present invention, the insulating material is made of epoxy resin or polyimide, so as to ensure that the bonding surface between the chip 1 and the insulating substrate 2 is in an insulating state, and at the same time, the insulating material has good thermal conductivity while insulating, so as to conduct heat.
The surface of the insulating substrate 2, which is not welded with the surface of the chip 1, is made of a heat conducting material with a preset thickness. The heat conducting material can be made of metal with good heat conducting performance, and the preset thickness of the heat conducting material can be selected according to the requirements of different applications and different systems, the size and the shape of the heat dissipation micro-channel to be integrated and other factors.
The micro-channel 6 is a through hole horizontally cut on the heat conducting material according to a preset size, and the through direction of the through hole is parallel to the chip 1.
The micro-channel 6 is parallel to the chip 1 in the penetrating direction, so that the cooling liquid in the micro-channel 6 can absorb the heat conducted from the chip 1 to the insulating layer 4 to the maximum extent.
Wherein, the number of the micro-channels 6 can be any number, and the shape of the micro-channels 6 can be any shape.
As shown in fig. 4, in an embodiment of the present invention, the insulating substrates 2 are bonded to the first surface and the second surface of the chip 1, the number of the micro channels 6 on each insulating substrate 2 is 1, and the shape of the micro channel 6 is a square.
The insulating layer 4 is formed by a first groove formed by adding an insulating material to the periphery of the microchannel 6, and the first groove is formed by cutting a heat conducting material on the periphery of the microchannel 6 according to a preset width.
The insulating layer 4 is formed by cutting off the heat conduction material with a certain width on the periphery of the micro-channel 6 and printing an etching insulating material at the position corresponding to the cut heat conduction material, so that the insulating layer 4 with a preset width is obtained.
In one embodiment of the present invention, the insulating material of the insulating layer 4 is aluminum nitride or ceramic. The insulating material adopted by the insulating layer 4 has good heat-conducting property while insulating, so that the heat conduction of the chip 1 is facilitated.
In addition, the existence of the insulating layer 4 can well isolate the cooling liquid from the first heat conduction layer 3, so that the insulation of the cooling liquid and the electrified part of the first heat conduction layer 3 is ensured, the deionized cooling liquid is not needed any more, and the cost of the power semiconductor device packaging structure is reduced.
The first heat conduction layer 3 is made of the heat conduction material remaining around the insulating layer 4.
The first heat conduction layer 3 is the peripheral part of the insulating layer 4 on the side of the insulating substrate 2 not welded with the chip 1, and the first heat conduction layer 3 is used for conducting the heat of the chip 1 to the insulating layer 4 and further conducting the heat into the micro-channel 6 so as to dissipate the heat through cooling liquid.
Meanwhile, the first heat conduction layer 3 is also used for realizing electrical connection with the chip 1.
It should be noted that, because the heat dissipation micro channel is integrated on the insulating substrate 2, the thickness of the insulating substrate 2 must be greater than the thickness of the insulating layer 4 and the size of the micro channel 6, that is, the preset width and the preset size are both smaller than the preset thickness.
In one embodiment of the present invention, the power semiconductor device package structure further comprises: a second heat conducting layer 5.
The second heat conduction layer 5 is formed by depositing a second groove with heat conduction materials on the periphery of the micro-channel 6, the second groove is obtained by cutting the heat conduction materials on the periphery of the micro-channel 6 according to a second preset width, and the second heat conduction layer 5 is obtained by depositing the heat conduction materials in the second groove and etching the second groove.
As shown in fig. 5, in an embodiment, the insulating substrate 2 is soldered to the first surface or the second surface of the chip 1, and the heat dissipation micro-channels are, from inside to outside, the micro-channel 6, the second heat conduction layer 5, the insulating layer 4, and the first heat conduction layer 3.
In another embodiment, as shown in fig. 6, the insulating substrate 2 is soldered to the first surface and the second surface of the chip 1, and the heat dissipation micro-channels are, from inside to outside, the micro-channel 6, the second heat conduction layer 5, the insulating layer 4, and the first heat conduction layer 3.
The second heat conducting layer 5 can be made of heat conducting and corrosion resistant material, and the heat conducting material of the second heat conducting layer 5 is used for rapidly conducting the heat of the insulating layer 4 to the micro-channel 6.
Meanwhile, the second heat conduction layer 5 is also used for separating the insulating layer 4 from the cooling liquid so as to protect the insulating layer 4 from being eroded by the cooling liquid, and avoid the insulating layer 4 from being worn by the cooling liquid, thereby causing failure.
In one embodiment of the invention, the microchannel 6 is located close to the chip 1.
Because the sizes of the first heat conduction layer 3, the insulation layer 4, the second heat conduction layer 5 and the micro-channel 6 can be designed by self, the micro-channel 6 can be as close as possible to the chip 1 according to different applications and different system requirements during design, so as to achieve the optimal heat dissipation effect. I.e. the position of the microchannel 6 on the insulating substrate 2, close to the side/position where the insulating substrate 2 is soldered to the chip 1.
Note that the microchannel 6 is arranged eccentrically with respect to the center line of the chip 1, and is located on a side close to a face/position where the insulating substrate 2 is bonded to the chip 1.
In one embodiment of the present invention, the number of the micro channels 6 may be only one, two, or more than two. After the size of the chip 1 is determined, one or more micro-channels 6 with a certain distance can be arranged inside the insulating substrate 2 according to the actual heat dissipation requirement.
The specific number of the micro-channels 6 can be selected by those skilled in the art according to the actual heat dissipation requirement, and is not limited herein.
In one embodiment of the present invention, if the number of the micro channels 6 is one, the shape of the micro channels 6 includes one of a square shape, a serpentine shape, a tapered shape, and a circular shape. If the number of the micro-channels 6 is plural, the shape of the micro-channels 6 includes one or more combinations of square, serpentine, conical and circular.
The microchannels 6 may all be of the same shape.
As shown in fig. 7, in one embodiment of the present invention, the number of the micro channel 6 is 3, and the micro channel 6 has a square shape.
The microchannels 6 may also be a combination of different shapes.
In one embodiment of the present invention, the number of the micro channels 6 is 3, one micro channel 6 is square, one micro channel 6 is circular, and one micro channel 6 is tapered.
The number and shape of the micro-channels 6 can be designed by those skilled in the art according to the actual heat dissipation requirement, and are not limited herein.
In an embodiment of the present invention, the heat conductive material of the first heat conductive layer 3 may be copper, and may also be aluminum.
The copper material or the aluminum material has high thermal conductivity, and can ensure that when the chip 1 conducts heat to the insulating layer 4 through the first heat conduction layer 3, the heat conduction speed is high, and the heat conduction resistance is small.
At the same time, the copper or aluminum material has good electrical conductivity, which facilitates electrical connection between the charged portion of the first heat conducting layer 3 and the chip 1.
Of course, the first heat conduction layer 3 may also be made of a material with good heat conduction and electrical conductivity, such as a copper alloy, an aluminum alloy, and the like, which is not limited herein.
In an embodiment of the present invention, the insulating material of the insulating layer 4 may be ceramic, or may be aluminum nitride. The ceramic or aluminum nitride has good insulating property and good thermal stability at high temperature, so that the size of the insulating layer 4 is ensured not to be obviously changed due to high temperature while insulating, and the structure of the insulating layer 4 is prevented from being obviously deformed or damaged after being heated.
Of course, the insulating layer 4 may also be made of other insulating materials with good insulating effect and good thermal conductivity, and is not limited herein.
In an embodiment of the present invention, the heat conductive material of the second heat conduction layer 5 may be copper, and may also be aluminum. Adopt copper or aluminium material to form second heat-conducting layer 5 has good heat conductivity, makes insulating layer 4 can give the coolant liquid through second heat-conducting layer 5 is fast with the heat conduction, simultaneously, because copper or aluminium have stronger corrosion resistance, the coolant liquid in the microchannel 6 is difficult for corroding second heat-conducting layer 5, fine protection insulating layer 4 does not receive the erosion of coolant liquid, and then has avoided the coolant liquid to the influence of the electrified part of first heat-conducting layer 3.
Of course, the first heat conduction layer 3 may also be made of a material with good heat conduction and electrical conductivity, such as a copper alloy, an aluminum alloy, and the like, which is not limited herein.
The materials used for the first heat conducting layer 3 and the second heat conducting layer 5 may be the same or different.
The thickness of the insulating layer 4 and the thickness of the second heat conducting layer 5 may be the same or different.
In one embodiment of the invention, the thickness of the second heat conducting layer 5 is smaller than the thickness of the insulating layer 4.
In one embodiment of the invention said first heat conducting layer 3 serves as a power terminal of the power semiconductor device.
The first heat conduction layer 3 is made of heat conduction materials with good electric conductivity, can be used as a heat conduction medium and can be used as a power terminal to be electrically connected with a power semiconductor device, the power terminal does not need to be additionally manufactured independently, and the cost of the packaging structure of the power semiconductor device is saved.
The related package parameters of the power semiconductor package structure part of the present invention will be described with reference to the prior art, specifically as follows:
the existing heat dissipation method of the power semiconductor device packaging structure comprises the following steps:
a, mode: and welding the chip on an insulating substrate, and welding the insulating substrate on a thick copper substrate to realize a complete power module. The power module is connected to the heat sink by coating silicone grease, and the heat generated by the chip during operation is taken away by the flow of the cooling liquid in the heat sink. However, the use of silicone grease and thick copper substrates poses problems of high thermal resistance and high cost.
b, mode: the insulating substrate is directly welded on the radiator, then the insulating substrate is welded with the bottom surface of the chip, and the cooling liquid in the radiator flows to take away the heat generated by the chip during working.
c, mode: the upper surface of the chip is welded with a radiator which is the same as the bottom surface through the insulating substrate, the heat generated by the chip is simultaneously dissipated from the upper surface and the bottom surface, and the thermal resistance is further reduced.
The results of comparing the thermal resistances of the three types of packages are shown in table 1:
TABLE 1
Compared with the heat dissipation modes a, the heat dissipation modes b and c reduce the thermal resistance to a certain extent, but the heat dissipation effect is still not ideal, and the volume of the packaging structure of the power semiconductor device is larger due to the existing heat dissipation modes.
Therefore, the present invention has been intensively studied on how to enhance the heat dissipation effect and reduce the volume of the power semiconductor device package structure.
As shown in fig. 8, in an embodiment, the first thermal conduction layer 3 is made of copper, the insulating layer 4 is made of aluminum nitride, and the second thermal conduction layer 5 is made of copper, a steady-state thermal characteristic simulation is performed on the high-power LD chip and the package structure thereof by testing and using a Finite Element Method (FEM), and the calculated package parameters are as follows:
the thermal resistance ratio is reduced to 32% of the junction-to-shell thermal resistance of the conventional package structure as shown in table 2.
TABLE 2
The stray inductance ratio is reduced to 37% of the stray inductance inside the conventional package structure as shown in table 3.
TABLE 3
Meanwhile, the heat dissipation micro-channel is integrated on the insulating substrate 2, so that the packaging volume is effectively reduced, and compared with the conventional heat dissipation type power semiconductor device packaging structure, the volume of the power semiconductor device packaging structure is reduced to 70% -80%.
In the power semiconductor device packaging structure provided by the embodiment of the invention, the power semiconductor device packaging structure comprises a chip 1 with a first surface and a second surface, and an insulating substrate 2 integrated with a heat dissipation micro-channel is welded on the first surface of the chip 1 and/or the second surface of the chip 1; the heat dissipation micro-channel comprises a micro-channel 6, an insulating layer 4 and a first heat conduction layer 3 from inside to outside, and cooling liquid is injected into the micro-channel 6. In the scheme, through the heat dissipation micro-channel on the insulating substrate 2, heat generated by the chip 1 welded with the insulating substrate 2 is conducted to the first heat conduction layer 3, and then the heat is conducted to the micro-channel 6 through the first heat conduction layer 3, so that the chip 1 is efficiently dissipated through cooling liquid in the micro-channel 6. The heat dissipation micro-channel is integrated in the insulating substrate 2, so that the heat dissipation performance is enhanced, the crusting thermal resistance of the packaging structure is reduced, and the stray inductance and the packaging volume in the packaging structure are effectively reduced; furthermore, the insulating layer 4 arranged between the micro-channel 6 and the first heat conducting layer 3 can ensure the insulating function of the cooling liquid and the electrified part of the insulating substrate 2, and reduces the use cost of the power semiconductor device; in addition, the first heat conduction layer 3 can also be directly used as a power terminal of a power semiconductor device, and the power terminal does not need to be additionally installed, so that the applicability of the insulating substrate 2 is improved, and the cost of a packaging structure is saved.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Accordingly, the application is not intended to be limited to the embodiments shown herein,
but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power semiconductor device package structure, comprising:
a chip having a first surface and a second surface;
an insulating substrate integrated with a heat dissipation micro-channel is welded on the first surface of the chip and/or the second surface of the chip;
the heat dissipation micro-channel comprises a micro-channel, an insulating layer and a first heat conduction layer from inside to outside, and cooling liquid is injected into the micro-channel;
wherein a surface area of the first thermally conductive layer is greater than a surface area of the first and second surfaces of the chip.
2. The power semiconductor device package structure according to claim 1, wherein a surface of the insulating substrate, to which the surface of the chip is bonded, is made of an insulating material;
the surface of the insulating substrate, which is not welded with the surface of the chip, is made of a heat conduction material with a preset thickness;
the micro-channel is a through hole horizontally cut on the heat conduction material according to a preset size, and the through direction of the through hole is parallel to the chip;
the insulating layer is formed by a first groove added with insulating materials at the periphery of the micro-channel, and the first groove is obtained by cutting the heat conducting materials at the periphery of the micro-channel according to a preset width;
the first heat conduction layer is made of the heat conduction material left on the periphery of the insulation layer;
wherein, the preset width and the preset size are both smaller than the preset thickness.
3. The power semiconductor device package structure of claim 1, further comprising: a second thermally conductive layer;
one surface of the insulating substrate, which is welded with the surface of the chip, is made of an insulating material;
the surface of the insulating substrate, which is not welded with the surface of the chip, is made of a heat conduction material with a preset thickness;
the micro-channel is a through hole horizontally cut on the heat conduction material according to a preset size, and the through direction of the through hole is parallel to the chip;
the second heat conduction layer is formed by a second groove, wherein heat conduction materials are deposited on the periphery of the micro channel, and the second groove is formed by cutting the heat conduction materials on the periphery of the micro channel according to a second preset width;
the insulating layer is formed by a first groove added with insulating materials at the periphery of the micro-channel, and the first groove is obtained by cutting the heat conduction materials at the periphery of the micro-channel according to a preset width;
the first heat conduction layer is made of the heat conduction material left on the periphery of the insulation layer;
the preset width, the second preset width and the preset size are all smaller than the preset thickness.
4. The power semiconductor device package structure according to any one of claims 1 to 3, wherein the micro channel is located close to the chip.
5. The power semiconductor device package structure according to any one of claims 1 to 3, wherein the number of microchannels comprises one or more.
6. The power semiconductor device package structure according to any one of claims 1 to 3, wherein if the number of the micro channels includes one, the shape of the micro channel includes one of a square shape, a serpentine shape, a tapered shape, and a circular shape;
if the number of the micro-channels comprises a plurality of micro-channels, the shape of the micro-channels comprises one or more combinations of square, serpentine, conical and circular.
7. The power semiconductor device package structure of any one of claims 1-3, wherein the thermally conductive material of the first thermally conductive layer comprises copper or aluminum.
8. The power semiconductor device package structure according to any one of claims 1 to 3, wherein the insulating material of the insulating layer comprises ceramic or aluminum nitride.
9. The power semiconductor device package of claim 3, wherein the thermally conductive material of the second thermally conductive layer comprises copper or aluminum.
10. The power semiconductor device package structure of any one of claims 1-3, wherein the first thermally conductive layer serves as a power terminal for a power semiconductor device.
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Address after: 311100 Floor 2, Building 1, No. 96, Longchuanwu Road, Donghu Street, Linping District, Hangzhou, Zhejiang Patentee after: Hangzhou Feishide Technology Co.,Ltd. Address before: 311100 2 / F, building 1, No. 96, longchuanwu Road, Donghu street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: HANGZHOU FIRSTACK TECHNOLOGY Co.,Ltd. |