CN115083914A - 具有改进的击穿性能的ldmos - Google Patents

具有改进的击穿性能的ldmos Download PDF

Info

Publication number
CN115083914A
CN115083914A CN202210243775.6A CN202210243775A CN115083914A CN 115083914 A CN115083914 A CN 115083914A CN 202210243775 A CN202210243775 A CN 202210243775A CN 115083914 A CN115083914 A CN 115083914A
Authority
CN
China
Prior art keywords
location
distance
ldmos
polysilicon
conductive electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210243775.6A
Other languages
English (en)
Inventor
林欣
祝荣华
张志宏
吴玉静
皮特·罗德里克斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of CN115083914A publication Critical patent/CN115083914A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7826—Lateral DMOS transistors, i.e. LDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种具有改进的击穿性能的LDMOS。一种用于制造半导体装置的方法包括在隔离区上方形成板结构。形成电连接到在所述隔离区下方的漂移区的漏极电极，其中所述漏极电极沿着所述半导体装置的有源区域的中心轴线在所述半导体装置的源极与漏极之间的电流流动的方向上与所述板结构的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述板结构的第二位置间隔开第二距离。所述第一距离小于所述第二距离。

Description

具有改进的击穿性能的LDMOS
技术领域
本公开大体上涉及用于高电压半导体装置的制造工艺。
背景技术
智能电力技术已在汽车、工业和消费型应用中具有增加的需求。将具有高侧能力的高电压装置集成到高级CMOS平台上在技术上和经济上都具有挑战性。在许多应用中，为了防止来自静电放电(ESD)效应的损坏，集成的高电压装置通常由ESD夹钳保护，所述ESD夹钳在操作电压之上且在装置击穿电压之下触发。因此，实现具有紧密分布的足够击穿电压对于ESD保护的成功是至关重要的。
在一些情况下，随着常规高电压装置的装置宽度减小，这些装置的击穿电压(BV)减小。此外，这些窄装置的BV变化也可能增大。因此，随着高电压装置的尺寸减小以实现特定设计目标，提供适当ESD保护变得更具有挑战性。增大高电压装置的最小装置宽度将改进BV特性。然而，较大的最小装置宽度将导致一些不利的特性(例如，当将高电压装置用作感测FET时的较高感测电流，以及到基板的较大寄生电容)。因此，非常需要通过创新装置设计改进击穿性能，同时维持最小装置宽度。
发明内容
根据本发明的第一方面，提供一种用于制造横向扩散金属氧化物半导体(LDMOS)的方法，包括：
在隔离区上方形成导电电极；以及
形成电连接到在所述隔离区下方的漂移区的漏极电极，所述导电电极围绕所述漏极电极，其中所述漏极电极沿着所述LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
在一个或多个实施例中，制造所述LDMOS包括制造p型场效应晶体管。
在一个或多个实施例中，制造所述LDMOS包括制造n型场效应晶体管。
在一个或多个实施例中，形成所述导电电极包括在所述第一位置处形成直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，形成所述导电电极包括在所述第一位置处形成倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，形成所述导电电极包括在所述第一位置处形成阶梯式多晶硅翻板，其中所述阶梯式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，所述导电电极包括多晶硅栅极部分，所述多晶硅栅极部分在所述LDMOS的有源区域中连接到场板部分。
在一个或多个实施例中，所述导电电极包括场板，其中所述场板在所述LDMOS的有源区域中与导电栅极结构横向间隔开。
根据本发明的第二方面，提供一种设备，包括：
在隔离区上方的导电电极；以及
连接到在所述隔离区下方的漂移区的漏极电极，所述导电电极围绕所述漏极电极，其中所述漏极电极沿着所述LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
在一个或多个实施例中，所述LDMOS是p型场效应晶体管。
在一个或多个实施例中，所述LDMOS是n型场效应晶体管。
在一个或多个实施例中，所述第一位置包括直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，所述第一位置包括倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，所述第一位置包括阶梯式多晶硅翻板，其中所述阶梯式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，所述导电电极包括多晶硅栅极部分，所述多晶硅栅极部分在所述LDMOS的有源区域中连接到场板部分。
在一个或多个实施例中，所述导电电极包括场板，其中所述场板在所述设备的有源区域中与导电栅极结构横向间隔开。
根据本发明的第三方面，提供一种用于制造半导体装置的方法，包括：
在隔离区上方形成板结构；以及
形成电连接到在所述隔离区下方的漂移区的漏极电极，其中所述漏极电极沿着所述半导体装置的有源区域的中心轴线在所述半导体装置的源极与漏极之间的电流流动的方向上与所述板结构的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述板结构的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
在一个或多个实施例中，所述板结构在所述半导体装置的有源区域中与导电电极横向间隔开。
在一个或多个实施例中，形成所述板结构包括在所述第一位置处形成直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。
在一个或多个实施例中，形成所述板结构包括在所述第一位置处形成倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。
本发明的这些和其它方面将根据下文中所描述的实施例显而易见，且参考这些实施例予以阐明。
附图说明
本发明借助于例子示出并且不受附图的限制，在附图中的类似标记指示类似元件。图式中的元件为简单和清楚起见被示出并且不必按比例绘制。
图1为p型横向扩散金属氧化物半导体(LDMOS)的示例实施例的横截面图。
图2为图1的示例实施例的层的子集的平面图。
图3为图1的示例实施例的多晶硅(polysilicon、poly)层和漏极区的平面图。
图4为对应于图1的示例实施例的图2和图3的层的俯视图。
图5为在装置宽度为40μm的情况下的图1的示例实施例的BV特性的图解视图。
图6为在装置宽度为5μm的情况下的图1的示例实施例的BV特性的图解视图。
图7为根据本公开的示例实施例的具有经修改多晶硅层的图1的LDMOS的BV特性的图解视图，所述经修改多晶硅层具有各种多晶硅标志到漏极间距。
图8为根据本公开的示例实施例的包括图1的单个阶梯式翻板和漏极区的经修改多晶硅层的示意图。
图9为根据本公开的示例实施例的包括图1的倒角式翻板和漏极区的经修改多晶硅层的示意图。
图10为根据本公开的示例实施例的包括图1的多个阶梯式翻板和漏极区的经修改多晶硅层的示意图。
图11为根据本公开的示例实施例的在装置宽度为40μm且进一步包括多晶硅翻板的情况下的图1的BV特性的图解视图。
图12为根据本公开的示例实施例的在装置宽度为5μm且进一步包括多晶硅翻板的情况下的图1的BV特性的图解视图。
图13为根据本公开的示例实施例的用于制造具有改进的击穿性能的LDMOS的方法的流程图表示。
图14为根据本公开的示例实施例的用于制造具有改进的击穿性能的LDMOS的另一方法的流程图表示。
具体实施方式
本文中所描述的实施例提供BV的改进。具体来说，在主装置操作区域中使用独特的多晶硅翻板，其中所述多晶硅翻板具有比装置终止末端附近的栅极长度更大的长度(且因此到有源漏极区域的距离较短)。因此，对装置宽度的BV相依性减小，且BV分布也变窄，而不需要在特定感测应用中具有寄生电容的对应增大和较高感测电流的较宽装置宽度。
图1示出了被布置成一对分裂栅极晶体管的p型LDMOS的示例实施例10。所述LDMOS形成于n型晶片(例如，n晶片)12上。块状氧化物(例如，内埋氧化物)14形成于n晶片12上。氧化物16围封垂直n型多晶硅18。n型内埋层(例如，lnbl)20形成于内埋氧化物14上。内埋氧化物14和氧化物16形成屏蔽区，在所述屏蔽区内形成晶体管。p型外延层(例如，p-epi)22形成于lnbl 20上方。N型高电压植入物(例如，nhv)24形成于lnbl 20上方以形成用于实施例10中所包括的两个晶体管中的每一个的相应主体区。p型外延层22保持在氧化物16与相应nhv24之间。一对p型高电压p阱(例如，hvpw)26形成于p-epi 22中。浅沟槽隔离(STI)28形成于每个相应晶体管的主体触点40与由氧化物16和多晶硅18形成的深沟槽隔离(DTI)之间。主体触点40形成到nhv 24的低阻抗连接。源极触点42邻接主体触点40。一对p型轻掺杂漏极植入物(例如，pldd)44邻近于源极触点42形成。STI 50形成于用于每一相应晶体管的hvpw 26漂移区中。
第一多晶硅栅极电极52形成于沟道区56上方，且控制沟道区56的形成和导电。共享漏极53形成于hvpw 26和p-epi 22中。第二多晶硅栅极电极54形成于用于每一相应晶体管的STI 50中的每一个上方以形成相应场板。第二多晶硅栅极电极54中的每一个形成具有在hvpw 26中的下伏漂移区的相应场板。间隔件58横向地形成于第一多晶硅栅极电极52的接近于源极42的侧上和第二多晶硅栅极电极54的接近于漏极53的侧上。间隔件59形成于每一第一多晶硅栅极电极52与第二多晶硅栅极电极54之间。硅化物60形成于用于每一相应晶体管的对接的主体触点40和源极触点42上方。硅化物60还形成于每一多晶硅栅极电极52和54以及共享漏极53上方。在另一实施例中，hvpw 26中的漂移区进一步包括n型补偿(NCOM)区62以降低此区中的掺杂浓度。第二多晶硅栅极电极54与漏极53间隔开第一距离64。图1的示例实施例10示出了分裂栅极设计。应理解，贯穿本公开的教示还适用于使用单个多晶硅栅极设计的实施例，其中所述单个多晶硅栅极用于形成沟道区56以及场板。
图2为示出图1的实施例10的若干处理层的示例实施例70的平面图。图3为示出图1的实施例10的额外处理层的示例实施例80的平面图。继续参考图1，图2示出了围绕形成主体区的nhv区24的DTI 18。nhv区24围绕形成漂移区的hvpw区26。在一个实施例中，漂移区进一步包括植入式NCOM区62以通过降低漂移区中的掺杂浓度来改进热载流子注入(HCI)-时间相依性介电击穿(TDDB)稳健性。DTI 18和内埋氧化物14(未示出)将晶体管对与相邻装置隔离以改进隔离。DTI 18与nhv 24之间的p型外延层22(图2中的未填充区域)进一步增大用于高侧(HS)和低侧(LS)电力应用两者的BV。有源区72限定于沟道导电发生的位置。在示例实施例70中，有源区72被示出为单个矩形区域。限定中心轴线74，所述中心轴线74在源极42与漏极53之间的电流流动的方向上平分有源区域72。
继续参考图1和图2，图3示出了以导电方式合并有源区域72外部的第一栅极电极52(形成沟道区56上方的多晶硅栅极)与第二栅极电极54(形成STI 50上方的场板)的合并多晶硅层82。一对间隙84用于通过将第一栅极电极52与第二栅极电极54间隔开而形成分裂栅极晶体管。漏极53在有源区域72的中心轴线74上的第一位置90处与第二多晶硅栅极电极54间隔开第一距离64。第二多晶硅栅极电极54在第一位置90处包括第一场翻板长度92。漏极53在远离中心轴线74且在示例实施例10的有源区域72内的第二位置94处与第二多晶硅栅极电极54间隔开第二距离86。第二多晶硅栅极电极54在第二位置94处包括第二场翻板长度96。
上覆hvpw 26或漂移区中的STI 50的第二栅极电极54包括右侧部分100、左侧部分102、顶部部分104和底部部分106。在图3的上下文中提供术语右侧、左侧、顶部和底部是为了易于说明，且并不希望对示例实施例80赋予定向限制。接近第一位置90的电荷平衡不同于装置终端(例如，接近第二位置94)处的电荷平衡。举例来说，接近第一位置90的漂移区(在hvpw 26区中)仅由右侧部分100下方的主体区耗尽。相比之下，接近第二位置94的漂移区的耗尽由右侧部分100和顶部部分104下方的主体区实现。因此，BV特性以及第一位置90和第二位置94是不同的，且因此，第一场翻板长度92与第二场翻板长度96的所需长度是不同的。图4示出了图2和图3的组合层的示例实施例120，出于解释清楚起见而单独地呈现。
图5示出了在装置宽度为40μm的情况下的示例实施例10的BV特性的图解视图。在图5中所示的例子中，五个管芯的所测量的BV 132超过135V的BV阈值130。所测量的BV 132还表现出紧密的电压分布。然而，如图6中所示，当装置宽度减小到5μm时，所测量的BV 140减小到低于135V的BV阈值130，且展现较宽的电压分布。
图7为根据本公开的示例实施例的具有经修改多晶硅层的图1的LDMOS的BV特性的图解视图，所述经修改多晶硅层具有各种多晶硅标志到漏极间距。图7比较了在装置宽度为40μm与5μm的情况下随着多晶硅翻板与漏极之间的第一距离64而变的BV。在图7的示例实施例中，对于40μm装置宽度，凭经验确定使BV最大化(超过BV阈值130)的3.4μm的最优第一距离150。对于5μm装置宽度，凭经验确定使BV最大化(超过BV阈值130)的3.8μm的最优第一距离152。优化第一距离64取决于装置宽度，因为装置终端在较窄装置中起更重要的作用，其中漂移区可在较短多晶硅翻板(例如，较大翻板到漏极空间，或第一距离64)的辅助下完全耗尽。
图8、图9和图10分别示出了具有经修改多晶硅翻板设计以改进BV特性的经修改多晶硅层的三个示例实施例160、170和180。为了考虑装置终端对装置性能的影响，每一实施例的多晶硅翻板在终端处以及接近于终端的区域中缩短，而有源区域72的中心轴线74处的多晶硅翻板保持不变。参考图8，参考图3和图7，示出了单个阶梯式翻板的示例实施例。如所论述，关于图7，在一个实施例中，凭经验确定第一距离64(且因此确定第一场翻板长度92)。类似地，在另一实施例中，凭经验确定翻板宽度162和翻板间距164以使BV最大化而超过BV阈值130。图9示出了示例实施例170，示例实施例170类似于实施例160的单个阶梯式翻板但具有倒角式翻板。图10示出了示例实施例180，示例实施例180类似于实施例160的单个阶梯式翻板但具有多个阶梯式翻板。
图11和图12示出了具有图8中的实施例160的多晶硅翻板的示例实施例10的BV特性的图解视图。类似于图5，在装置宽度为40μm的情况下，图11中的实施例示出了超过135V的BV阈值130的五个管芯的所测量BV 190。所测量BV 190表现出与图5中所示类似的紧密电压分布。与图6形成对比，在装置宽度为5μm的情况下，图12中的实施例示出了超过135V的BV阈值130的五个管芯的所测量BV 200。所测量BV 200进一步表现出与图6所示的分布相比显著改进的紧密电压分布。
图13示出了用于制造具有改进的击穿性能的LDMOS的方法的示例实施例210。参考图13，继续参考图1和图3，在214处，在隔离区50上方形成导电电极54(例如，场板)。在216处，形成漏极电极53，且将漏极电极53连接到漂移区26。漏极电极53由导电电极54围绕。栅极电极54的第一位置90在有源区域72的中心轴线74上。导电电极54在平行于中心轴线74且在有源区域72内的线上具有比在导电电极54的第二位置94处长的场翻板长度92。
图14示出了用于制造具有改进的击穿性能的LDMOS的方法的另一示例实施例220。参考图14，继续参考图1和图3，在222处，在隔离区50上方形成板结构54。形成漏极电极53，且将漏极电极53连接到漂移区26。板结构54的第一位置90在有源区域72的中心轴线74上。板结构54在平行于中心轴线74且在有源区域72内的线上具有比在板结构54的第二位置94处长的场翻板长度92。
如应了解，如所公开的实施例包括至少以下内容。在一个实施例中，一种用于制造横向扩散金属氧化物半导体(LDMOS)的方法包括在隔离区上方形成导电电极。形成电连接到在所述隔离区下方的漂移区的漏极电极。所述导电电极围绕所述漏极电极，其中所述漏极电极沿着所述LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离。所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离。所述第一距离小于所述第二距离。
用于制造横向扩散金属氧化物半导体(LDMOS)的方法的替代实施例包括以下特征之一或所述特征的任何组合。制造LDMOS包括制造p型场效应晶体管。制造LDMOS包括制造n型场效应晶体管。形成所述导电电极包括在所述第一位置处形成直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。形成所述导电电极包括在所述第一位置处形成倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。形成所述导电电极包括在所述第一位置处形成阶梯式多晶硅翻板，其中所述阶梯式多晶硅翻板不在所述第二位置处。所述导电电极包括在LDMOS的有源区域中连接到场板部分的多晶硅栅极部分。所述导电电极包括场板，其中所述场板在所述LDMOS的有源区域中与导电栅极结构横向间隔开。
在另一实施例中，一种设备包括在隔离区上方的导电电极。漏极电极连接到在隔离区下方的漂移区。所述导电电极围绕所述漏极电极，其中所述漏极电极沿着LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离。所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离。所述第一距离小于所述第二距离。
设备的替代实施例包括以下特征之一或所述特征的任何组合。LDMOS是p型场效应晶体管。LDMOS是n型场效应晶体管。所述第一位置包括直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。所述第一位置包括倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。所述第一位置包括阶梯式多晶硅翻板，其中所述阶梯式多晶硅翻板不在所述第二位置处。所述导电电极包括在LDMOS的有源区域中连接到场板部分的多晶硅栅极部分。所述导电电极包括场板，其中所述场板在所述设备的有源区域中与导电栅极结构横向间隔开。
在另一实施例中，一种用于制造半导体装置的方法包括在隔离区上方形成板结构。形成电连接到在所述隔离区下方的漂移区的漏极电极，其中所述漏极电极沿着所述半导体装置的有源区域的中心轴线在所述半导体装置的源极与漏极之间的电流流动的方向上与所述板结构的第一位置间隔开第一距离。所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述板结构的第二位置间隔开第二距离。所述第一距离小于所述第二距离。
用于制造半导体装置的方法的替代实施例包括以下特征之一或所述特征的任何组合。所述板结构在所述半导体装置的有源区域中与导电电极横向间隔开。形成所述板结构包括在所述第一位置处形成直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。形成所述板结构包括在所述第一位置处形成倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。
虽然本文中参考具体实施例描述了本发明，但是在不脱离如所附权利要求书所阐述的本发明的范围的情况下可以进行各种修改和改变。因此，说明书和附图应视为示意性而不具有限制性意义，并且所有这些修改旨在都包括在本发明的范围内。并不希望将本文中相对于特定实施例描述的任何益处、优势或针对问题的解决方案解释为任何或所有权利要求的关键、必需或必不可少的特征或元件。
除非以其它方式陈述，否则例如“第一”和“第二”等术语用于任意地区别这些术语所描述的元件。因此，这些术语未必意图指示此类元件的时间或其它优先级排序。

Claims (10)

1.一种用于制造横向扩散金属氧化物半导体(LDMOS)的方法，其特征在于，包括：
在隔离区上方形成导电电极；以及
形成电连接到在所述隔离区下方的漂移区的漏极电极，所述导电电极围绕所述漏极电极，其中所述漏极电极沿着所述LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
2.根据权利要求1所述的方法，其特征在于，制造所述LDMOS包括制造p型场效应晶体管。
3.根据权利要求1所述的方法，其特征在于，制造所述LDMOS包括制造n型场效应晶体管。
4.根据权利要求1所述的方法，其特征在于，形成所述导电电极包括在所述第一位置处形成直线式多晶硅翻板，其中所述直线式多晶硅翻板不在所述第二位置处。
5.根据权利要求1所述的方法，其特征在于，形成所述导电电极包括在所述第一位置处形成倒角式多晶硅翻板，其中所述倒角式多晶硅翻板不在所述第二位置处。
6.根据权利要求1所述的方法，其特征在于，形成所述导电电极包括在所述第一位置处形成阶梯式多晶硅翻板，其中所述阶梯式多晶硅翻板不在所述第二位置处。
7.根据权利要求1所述的方法，其特征在于，所述导电电极包括多晶硅栅极部分，所述多晶硅栅极部分在所述LDMOS的有源区域中连接到场板部分。
8.根据权利要求1所述的方法，其特征在于，所述导电电极包括场板，其中所述场板在所述LDMOS的有源区域中与导电栅极结构横向间隔开。
9.一种设备，其特征在于，包括：
在隔离区上方的导电电极；以及
连接到在所述隔离区下方的漂移区的漏极电极，所述导电电极围绕所述漏极电极，其中所述漏极电极沿着所述LDMOS的有源区域的中心轴线在所述LDMOS的源极与漏极之间的电流流动的方向上与所述导电电极的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述导电电极的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
10.一种用于制造半导体装置的方法，其特征在于，包括：
在隔离区上方形成板结构；以及
形成电连接到在所述隔离区下方的漂移区的漏极电极，其中所述漏极电极沿着所述半导体装置的有源区域的中心轴线在所述半导体装置的源极与漏极之间的电流流动的方向上与所述板结构的第一位置间隔开第一距离，所述漏极电极沿着平行于所述中心轴线且在所述有源区域内的线与所述板结构的第二位置间隔开第二距离，且所述第一距离小于所述第二距离。
CN202210243775.6A 2021-03-11 2022-03-10 具有改进的击穿性能的ldmos Pending CN115083914A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/199,153 2021-03-11
US17/199,153 US11610978B2 (en) 2021-03-11 2021-03-11 LDMOS with an improved breakdown performance

Publications (1)

Publication Number Publication Date
CN115083914A true CN115083914A (zh) 2022-09-20

Family

ID=80628892

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210243775.6A Pending CN115083914A (zh) 2021-03-11 2022-03-10 具有改进的击穿性能的ldmos

Country Status (3)

Country Link
US (1) US11610978B2 (zh)
EP (1) EP4057360A1 (zh)
CN (1) CN115083914A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117253925A (zh) * 2023-11-20 2023-12-19 深圳天狼芯半导体有限公司 一种具有凹槽场板的sti型ldmos及制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111092123A (zh) * 2019-12-10 2020-05-01 杰华特微电子（杭州）有限公司 横向双扩散晶体管及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534721A (en) 1994-11-30 1996-07-09 At&T Corp. Area-efficient layout for high voltage lateral devices
US20110115018A1 (en) * 2009-11-13 2011-05-19 Maxim Integrated Products, Inc. Mos power transistor
JP5455801B2 (ja) * 2010-06-10 2014-03-26 株式会社東芝 半導体装置
US8754469B2 (en) 2010-10-26 2014-06-17 Texas Instruments Incorporated Hybrid active-field gap extended drain MOS transistor
US9653561B2 (en) 2013-03-12 2017-05-16 Macronix International Co., Ltd. Low on resistance semiconductor device
US9543379B2 (en) 2014-03-18 2017-01-10 Nxp Usa, Inc. Semiconductor device with peripheral breakdown protection
JP2017045884A (ja) 2015-08-27 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US9899513B1 (en) 2016-12-29 2018-02-20 Macronix International Co., Ltd. Lateral diffused metal oxide semiconductor transistor and manufacturing method thereof
JP2019165094A (ja) 2018-03-19 2019-09-26 株式会社東芝 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117253925A (zh) * 2023-11-20 2023-12-19 深圳天狼芯半导体有限公司 一种具有凹槽场板的sti型ldmos及制备方法

Also Published As

Publication number Publication date
US20220293771A1 (en) 2022-09-15
US11610978B2 (en) 2023-03-21
EP4057360A1 (en) 2022-09-14

Similar Documents

Publication Publication Date Title
US9852993B2 (en) Lateral high voltage integrated devices having trench insulation field plates and metal field plates
US10468522B2 (en) Semiconductor device
US9543379B2 (en) Semiconductor device with peripheral breakdown protection
US8772871B2 (en) Partially depleted dielectric resurf LDMOS
US9401352B2 (en) Field-effect device and manufacturing method thereof
US8541862B2 (en) Semiconductor device with self-biased isolation
CN106887452B (zh) 在半导体装置中的自调式隔离偏置
US9853146B2 (en) Lateral double diffused MOS transistors
US8373227B2 (en) Semiconductor device and method having trenches in a drain extension region
CN106972050B (zh) 半导体装置中的局部自偏压隔离
CN108807543B (zh) 横向扩散金属氧化物半导体器件及其制造方法
CN107768423B (zh) 具有隔离区的横向扩散金属氧化物半导体场效应晶体管
CN108807541B (zh) 一种具有交错叉指式排列的浅槽隔离结构横向半导体器件
CN115083914A (zh) 具有改进的击穿性能的ldmos
US20030001216A1 (en) Semiconductor component and method of manufacturing
EP3723136A1 (en) Ldmos with diode coupled isolation ring
US7829954B2 (en) PMOS depletable drain extension made from NMOS dual depletable drain extensions
CN108269846B (zh) 具有扩展的电气安全操作区的半导体器件
CN116259663A (zh) 半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination