CN115050761A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN115050761A
CN115050761A CN202210864293.2A CN202210864293A CN115050761A CN 115050761 A CN115050761 A CN 115050761A CN 202210864293 A CN202210864293 A CN 202210864293A CN 115050761 A CN115050761 A CN 115050761A
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metal oxide
oxide layer
doped region
gate
thin film
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CN202210864293.2A
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Chinese (zh)
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范扬顺
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AU Optronics Corp
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AU Optronics Corp
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Priority claimed from TW111110923A external-priority patent/TWI813217B/en
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Abstract

A semiconductor device includes a substrate, a first thin film transistor, and a second thin film transistor. The first and second thin film transistors are disposed on the substrate. The first thin film transistor includes stacked first and second metal oxide layers. The first metal oxide layer has an oxygen concentration less than that of the second metal oxide layer, and the second metal oxide layer has a thickness less than that of the first metal oxide layer. The two-dimensional electron gas is located at the interface between the first and second metal oxide layers. The second thin film transistor is electrically connected with the first thin film transistor. The second thin film transistor includes a third metal oxide layer. The second and third metal oxide layers belong to the same patterned layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a metal oxide layer and a method of manufacturing the same.
Background
At present, a common thin film transistor generally uses an amorphous silicon semiconductor as a channel, wherein the amorphous silicon semiconductor is widely applied to various thin film transistors due to simple process and low cost.
With the progress of display technology, the resolution of display panels is increasing year by year. In order to shrink the thin film transistor in the pixel circuit, many manufacturers are working on developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, Indium Gallium Zinc Oxide (IGZO) has advantages of both small area and high electron mobility, and thus is considered as an important novel semiconductor material.
Disclosure of Invention
The invention provides a semiconductor device having advantages of high efficiency and low manufacturing cost.
The invention provides a method for manufacturing a semiconductor device, which has the advantages of low manufacturing cost and high efficiency.
At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are arranged on the substrate. The first thin film transistor includes a first metal oxide layer and a second metal oxide layer stacked. The first metal oxide layer has an oxygen concentration less than that of the second metal oxide layer, and the second metal oxide layer has a thickness less than that of the first metal oxide layer. The two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer. The second thin film transistor is electrically connected with the first thin film transistor. The second thin film transistor includes a third metal oxide layer. The second metal oxide layer and the third metal oxide layer belong to the same patterned layer.
At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a first thin film transistor on the substrate, wherein the first thin film transistor comprises a first metal oxide layer and a second metal oxide layer which are stacked, the oxygen concentration of the first metal oxide layer is less than that of the second metal oxide layer, the thickness of the second metal oxide layer is less than that of the first metal oxide layer, and the two-dimensional electron gas is positioned at the interface between the first metal oxide layer and the second metal oxide layer; and forming a second thin film transistor on the substrate, wherein the second thin film transistor is electrically connected with the first thin film transistor, the second thin film transistor comprises a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 2A to 2E are schematic cross-sectional views of a semiconductor device according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 8 is a circuit diagram of a semiconductor device according to an embodiment of the invention.
Description of reference numerals:
10,20,30,40,50,60: semiconductor device with a plurality of semiconductor chips
100: substrate
102: buffer layer
110: gate dielectric layer
112: opening of the container
120: interlayer dielectric layer
122: first contact hole
124: second contact hole
126: third contact hole
128: the fourth contact hole
200: a first thin film transistor
210: a first metal oxide layer
212: a fifth doped region
214: a sixth doped region
220,220 a: second metal oxide layer
222: first doped region
224: second doped region
226: first channel region
230: a first grid electrode
242: a first source electrode
244: a first drain electrode
300: second thin film transistor
320,320 a: a third metal oxide layer
322: a third doped region
324: second channel region
326: a fourth doped region
330, 330A: second grid
342: second source electrode
344: second drain electrode
2 DEG: two-dimensional electron gas
C: capacitor with a capacitor element
LED: light emitting diode
ND: normal direction
OS 1: first metal oxide pattern
OS 2: second metal oxide pattern
T1, T2, T3: thickness of
Detailed Description
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Referring to fig. 1, a semiconductor device 10 includes a substrate 100, a first thin film transistor 200, and a second thin film transistor 300.
The substrate 100 may be made of glass, quartz, organic polymer, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable material.
The buffer layer 102 is formed on the surface of the substrate 100. The material of the buffer layer 102 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or other insulating material. In some embodiments, the buffer layer 102 is a single layer structure or a multi-layer structure.
The first thin film transistor 200 is disposed on the substrate 100. In the present embodiment, the first thin film transistor 200 is formed on the buffer layer 102. The first thin film transistor includes a first metal oxide layer 210, a second metal oxide layer 220, a first gate 230, a first source 242, and a first drain 244.
The first metal oxide layer 210 and the second metal oxide layer 220 are located on the substrate 100 and stacked on each other. In the present embodiment, the first metal oxide layer 210 and the second metal oxide layer 220 are sequentially formed on the buffer layer 102. The oxygen concentration of the first metal oxide layer 210 is less than the oxygen concentration of the second metal oxide layer 220. In some embodiments, the oxygen concentration of the first metal oxide layer 210 is 10 at% to 50 at%, and the oxygen concentration of the second metal oxide layer 220 is 30 at% to 70 at%. In some embodiments, the energy Gap (Band Gap) of the first metal oxide layer 210 is smaller than the energy Gap of the second metal oxide layer 220 by adjusting the oxygen concentration, thereby forming a two-dimensional electron gas 2DEG at the interface between the first metal oxide layer 210 and the second metal oxide layer 220. The thickness T2 of the second metal oxide layer 220 is smaller than the thickness T1 of the first metal oxide layer 210, thereby allowing the two-dimensional electron gas 2DEG to be more easily formed at the interface. In some embodiments, the thickness T1 of the first metal oxide layer 210 is 10 to 60 nanometers and the thickness T2 of the second metal oxide layer 220 is 5 to 30 nanometers. In some embodiments, the material of the first metal oxide layer 210 and the second metal oxide layer 220 includes a quaternary compound of indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or a ternary compound containing two metal elements of the foregoing quaternary compounds and an oxygen element.
The second metal oxide layer 220 includes a first doped region 222, a second doped region 226, and a first channel region 224 between the first doped region 222 and the second doped region 226. In some embodiments, the first doped region 222 and the second doped region 226 are formed by a hydrogen plasma process, wherein the first doped region 222 and the second doped region 226 have an oxygen vacancy concentration lower than that of the first channel region 224, and the first doped region 222 and the second doped region 226 have a conductivity higher than that of the first channel region 224.
The gate dielectric layer 110 is on the second metal oxide layer 220. In some embodiments, the material of the gate dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. In some embodiments, the thickness of the gate dielectric layer 110 is 50 nm to 300 nm.
The first gate 230 is located on the gate dielectric layer 110. The first gate 230 overlaps the first metal oxide layer 210 and the first channel region 224 of the second metal oxide layer 220 in the normal direction ND of the top surface of the substrate 100. The gate dielectric layer 110 is located between the first gate electrode 230 and the second metal oxide layer 220. The first gate electrode 230 contacts the first channel region 224 of the second metal oxide layer 220 through the opening of the gate dielectric layer. In the present embodiment, the width of the opening of the gate dielectric layer is smaller than the width of the first channel region 224. In some embodiments, the material of the first gate 230 includes tungsten, molybdenum, platinum, gold, or other high work function metals, or combinations thereof. The first gate 230 has a Schottky contact (Schottky contact) with the second metal oxide layer 220.
The interlayer dielectric layer 120 is disposed on the gate dielectric layer 110. The interlayer dielectric layer 120 covers the first gate 230. In some embodiments, the material of the interlayer dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. In some embodiments, the thickness of the interlayer dielectric layer 120 is 100 nm to 600 nm.
The first source electrode 242 and the first drain electrode 244 are disposed on the interlayer dielectric layer 120 and connected to the first doped region 222 and the second doped region 226 of the second metal oxide layer 220 through the contact holes in the interlayer dielectric layer 120, respectively. In some embodiments, the material of the first source electrode 242 and the first drain electrode 244 includes aluminum, titanium, molybdenum, copper, or an alloy of the above metals, or a combination thereof. In some embodiments, there is a schottky contact or an Ohmic contact (Ohmic contact) between the first source electrode 242 and the second metal oxide layer 220 and between the first drain electrode 244 and the second metal oxide layer 220.
In the present embodiment, the first thin film Transistor 200 is a Metal Semiconductor Field Effect Transistor (MESFET), and the first thin film Transistor 200 is a normally-on Transistor. Since the first thin film transistor 200 includes the two-dimensional electron gas 2DEG, the first thin film transistor 200 is suitable for a high current driving transistor. In addition, since the first gate electrode 230 of the first thin film transistor 200 contacts the second metal oxide layer 220, a charge trapping effect (charge trapping effect) occurring in an insulating layer between the first gate electrode 230 and the second metal oxide layer 220 may be reduced, thereby improving the efficiency of the first thin film transistor 200.
The second thin film transistor 300 is disposed on the substrate 100. In the present embodiment, the second thin film transistor 300 is formed on the buffer layer 102. The second thin film transistor includes a third metal oxide layer 320, a second gate 330, a second source 342, and a second drain 344. The second thin film transistor 300 is electrically connected to the first thin film transistor 200. For example, the second drain 344 of the second tft 300 is electrically connected to the first gate 230 of the first tft 200 through a conducting wire not shown in fig. 1.
The third metal oxide layer 320 is located over the substrate 100. In the present embodiment, the third metal oxide layer 320 is formed on the buffer layer 102. In some embodiments, the thickness T3 of the third metal oxide layer 320 is 5 nanometers to 30 nanometers. In some embodiments, the material of the third metal oxide layer 320 includes a quaternary compound of indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or a ternary compound including two metal elements of the foregoing quaternary compound and an oxygen element. The oxygen concentration of the first metal oxide layer 210 is less than the oxygen concentration of the third metal oxide layer 320. In some embodiments, the second metal oxide layer 220 and the third metal oxide layer 230 belong to the same patterning layer, and it can be said that the shapes of the second metal oxide layer 220 and the third metal oxide layer 230 are defined in the same patterning process. The second metal oxide layer 220 and the third metal oxide layer 230 include the same material.
The third metal oxide layer 320 includes a third doped region 322, a fourth doped region 326, and a second channel region 324 between the third doped region 322 and the fourth doped region 326. In some embodiments, the third doped region 322 and the fourth doped region 326 are formed by a hydrogen plasma process, wherein the third doped region 322 and the fourth doped region 326 have a higher oxygen vacancy concentration than the second channel region 324, and the third doped region 322 and the fourth doped region 326 have a higher electrical conductivity than the second channel region 324. In some embodiments, the first doped region 222 and the second doped region 226 of the second metal oxide layer 220 and the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320 are formed in the same hydrogen plasma treatment.
The second gate 330 is located on the gate dielectric layer 110. The second gate 330 overlaps the second channel region 324 of the third metal oxide layer 320 in the normal direction ND of the top surface of the substrate 100. The gate dielectric layer 110 is located between the second gate 330 and the third metal oxide layer 320. The second gate 330 does not contact the third metal oxide layer 320. In some embodiments, the first gate 230 and the second gate 330 belong to the same patterning layer, and the shapes of the first gate 230 and the second gate 330 are defined in the same patterning process. The first gate 230 and the second gate 330 include the same material.
The second source 322 and the second drain 326 are disposed on the interlayer dielectric layer 120, and are respectively connected to the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320 through the contact holes in the interlayer dielectric layer 120. In some embodiments, the material of the second source electrode 322 and the second drain electrode 326 comprises aluminum, titanium, molybdenum, copper, or a combination thereof. In some embodiments, there is a schottky contact or an Ohmic contact (Ohmic contact) between the second source electrode 322 and the third metal oxide layer 320 and between the second drain electrode 326 and the third metal oxide layer 320. In some embodiments, the first source 222, the first drain 226, the second source 322 and the second drain 326 belong to the same patterning layer, and it can be said that the shapes of the first source 222, the first drain 226, the second source 322 and the second drain 326 are defined in the same patterning process. The first source 222, the first drain 226, the second source 322 and the second drain 326 comprise the same material.
In the present embodiment, the second thin film Transistor 300 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the second thin film Transistor 300 is a normally-off Transistor.
Fig. 2A to 2E are schematic cross-sectional views of a semiconductor device according to an embodiment of the invention.
Referring to fig. 2A, a first metal oxide pattern OS1 is formed on the substrate 100. The first metal oxide pattern OS1 includes a first metal oxide layer 210.
Referring to fig. 2B, a second metal oxide pattern OS2 is formed on the first metal oxide pattern OS1 and the substrate 100. The second metal oxide pattern OS2 includes a second metal oxide layer 220a and a third metal oxide layer 320 a.
Referring to fig. 2C, a gate dielectric layer 110 is formed on the second metal oxide pattern OS 2. The gate dielectric layer 110 has an opening 112 overlapping and exposing the second metal oxide layer 220 a.
Referring to fig. 2C and 2D, a first gate 230 and a second gate 330 are formed on the gate dielectric layer 110. The second metal oxide layer 220a overlaps the first gate 230, and the third metal oxide layer 320a overlaps the second gate 330. The first gate 230 contacts the second metal oxide layer 220a through the opening 112.
A doping process is performed on the second metal oxide layer 220a and the third metal oxide layer 320a using the first gate 230 and the second gate 330 as masks to form the second metal oxide layer 220 including the first doped region 222, the second doped region 226 and the first channel region 224 and the third metal oxide layer 320 including the third doped region 322, the fourth doped region 326 and the second channel region 324. The first channel region 224 is located between the first doped region 222 and the second doped region 226, and the second channel region 324 is located between the third doped region 322 and the fourth doped region 326. In the present embodiment, the first channel region 224 and the second channel region 324 overlap the first gate 230 and the second gate 330, respectively, in the normal direction ND of the top surface of the substrate 100.
In some embodiments, the doping process, such as a hydrogen plasma doping process or other suitable processes, reduces the oxygen vacancies in the first, second, third, and fourth doped regions 222, 226, 322, and 326 to increase the conductivity of the first, second, third, and fourth doped regions 222, 226, 322, and 326.
Referring to fig. 2E, an interlayer dielectric layer 120 is formed on the gate dielectric layer 110. One or more etching processes are performed to form first, second, third, and fourth contact holes 122, 124, 126, and 128 through the interlayer dielectric layer 120 and the gate dielectric layer 110. The first contact hole 122 and the second contact hole 124 overlap and expose the first doped region 222 and the second doped region 226 of the second metal oxide layer 220, and the third contact hole 126 and the fourth contact hole 128 overlap and expose the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320.
Finally, referring to fig. 2E and fig. 1, the first source electrode 242, the first drain electrode 244, the second source electrode 342, and the second drain electrode 344 are formed on the interlayer dielectric layer 120, and the first source electrode 242, the first drain electrode 244, the second source electrode 342, and the second drain electrode 344 are formed in the first contact hole 122, the second contact hole 124, the third contact hole 126, and the fourth contact hole 128. The first source 242 and the first drain 244 are respectively connected to the first doped region 222 and the second doped region 226 of the second metal oxide layer 220, and the second source 342 and the second drain 344 are respectively connected to the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 3 follows the element numbers and partial contents of the embodiment of fig. 1 to 2E, wherein the same or similar element numbers are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main differences between the semiconductor device 20 of fig. 3 and the semiconductor device 10 of fig. 1 are: the first gate electrode 230 of the semiconductor device 20 includes a multi-layered structure.
Referring to fig. 3, the first gate 230 includes a stack of a metal layer 234 and a P-type semiconductor layer 232, wherein the P-type semiconductor layer 232 contacts the second metal oxide layer 220. In this embodiment, the first thin film transistor 200 is a normally-off (normal-off) transistor.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 4 follows the element numbers and partial contents of the embodiment of fig. 1 to 2E, wherein the same or similar element numbers are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main differences between the semiconductor device 30 of fig. 4 and the semiconductor device 10 of fig. 1 are: the first source 242 and the first drain 244 of the semiconductor device 30 extend through the second metal oxide layer 220.
Referring to fig. 4, the first source electrode 242 and the first drain electrode 244 extend through the second metal oxide layer 220 and contact the interface between the first metal oxide layer 210 and the second metal oxide layer 220. In other words, the first source electrode 242 and the first drain electrode 244 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the first thin film transistor 200.
In the present embodiment, the second source 342 and the second drain 344 also extend through the third metal oxide layer 320, but the invention is not limited thereto. In other embodiments, the second source 342 and the second drain 344 do not pass through the third metal oxide layer 320.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 5 follows the element numbers and partial contents of the embodiments of fig. 1 to 2E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main differences between the semiconductor device 40 of fig. 5 and the semiconductor device 10 of fig. 1 are: the first metal oxide layer 210 of the semiconductor device 40 includes a fifth doped region 212 and a sixth doped region 214.
In the present embodiment, a doping process is performed to form a first doped region 222 and a second doped region 226 in the second metal oxide layer 220, and the doping process forms a fifth doped region 212 and a sixth doped region 214 in the first metal oxide layer 210. In other words, the dopants (e.g., hydrogen atoms) in the doping process reach the first metal oxide layer 210 after passing through the second metal oxide layer 220, and form the fifth doped region 212 and the sixth doped region 214 in the first metal oxide layer 210. The fifth doped region 212 and the sixth doped region 214 contact the bottom of the first doped region 222 and the bottom of the second doped region 226, respectively.
In some embodiments, the thickness of the fifth doped region 212 and the thickness of the sixth doped region 216 are less than the thickness of the first metal oxide layer 210.
In some embodiments, the thicknesses of the first doped region 222, the second doped region 226, the third doped region 322, the fourth doped region 326, the fifth doped region 212, and the width of the sixth doped region 216 gradually decrease as the substrate 100 approaches. The surfaces of the first doped region 222 and the second doped region 226 facing the first channel region 224 are curved surfaces, and the surfaces of the third doped region 322 and the fourth doped region 326 facing the second channel region 324 are curved surfaces.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 6 follows the element numbers and partial contents of the embodiments of fig. 1 to 2E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, which are not repeated herein.
The main differences between the semiconductor device 50 of fig. 6 and the semiconductor device 10 of fig. 1 are: the second thin film transistor 300 of the semiconductor device 50 is a bottom gate thin film transistor.
Referring to fig. 6, the second gate 330A of the second thin film transistor 300 is located between the third metal oxide layer 320 and the substrate 100. The first gate 230 and the second gate 330A belong to different patterning layers, and it can also be said that the shapes of the first gate 230 and the second gate 330A are defined in different patterning processes.
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 7 follows the element numbers and partial contents of the embodiments of fig. 1 to 2E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main differences between the semiconductor device 60 of fig. 7 and the semiconductor device 10 of fig. 1 are: the second thin film transistor 300 of the semiconductor device 60 is a double-gate thin film transistor.
Referring to fig. 6, the second thin film transistor 300 includes two gates, i.e., a second gate 330 and a second gate 330A, wherein the third metal oxide layer 320 is located between the second gate 330 and the second gate 330A.
Fig. 8 is a circuit diagram of a semiconductor device according to an embodiment of the invention. Fig. 8 may be a circuit diagram of the semiconductor device according to any of the embodiments.
Referring to fig. 8, the first gate of the first tft 200 is electrically connected to the second drain of the second tft 300. In the present embodiment, a capacitor C is included between the first drain of the first thin film transistor 200 and the second drain of the second thin film transistor 300, and the first drain of the first thin film transistor 200 is electrically connected to the light emitting diode LED.
In summary, the first thin film transistor of the present invention includes the first metal oxide layer and the second metal oxide layer, wherein the interface between the first metal oxide layer and the second metal oxide layer has two-dimensional electron gas, so that the output current of the first thin film transistor 200 can be increased.

Claims (19)

1. A semiconductor device, comprising:
a substrate;
a first thin film transistor disposed on the substrate, the first thin film transistor including a first metal oxide layer and a second metal oxide layer stacked one on another, wherein an oxygen concentration of the first metal oxide layer is less than an oxygen concentration of the second metal oxide layer, a thickness of the second metal oxide layer is less than a thickness of the first metal oxide layer, and a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer; and
and the second thin film transistor is arranged on the substrate and electrically connected with the first thin film transistor, wherein the second thin film transistor comprises a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer belong to the same patterning layer.
2. The semiconductor device according to claim 1, wherein the first thin film transistor further comprises:
a first gate overlapping the first metal oxide layer and the second metal oxide layer in a normal direction of the top surface of the substrate, wherein a gate dielectric layer is located between the first gate and the second metal oxide layer, the first gate contacts the second metal oxide layer through an opening of the gate dielectric layer, and an interlayer dielectric layer is disposed on the gate dielectric layer; and
and a first source and a first drain disposed on the interlayer dielectric layer and respectively connected to the second metal oxide layer.
3. The semiconductor device of claim 2, wherein the second metal oxide layer comprises a first doped region, a second doped region, and a first channel region between the first doped region and the second doped region, the interlayer dielectric layer comprises a first contact hole overlapping the first doped region and a second contact hole overlapping the second doped region, the first source is connected to the first doped region through the first contact hole, and the first drain is connected to the second doped region through the second contact hole.
4. The semiconductor device of claim 2, wherein said first source and said first drain extend through said second metal oxide layer and contact said interface of said first metal oxide layer and said second metal oxide layer.
5. The semiconductor device of claim 2, wherein said first gate comprises a stack of a metal layer and a P-type semiconductor layer.
6. The semiconductor device according to claim 2, wherein the second thin film transistor further comprises:
a second gate overlapping the third metal oxide layer in the normal direction of the top surface of the substrate, wherein the gate dielectric layer is between the second gate and the third metal oxide layer; and
and a second source and a second drain disposed on the interlayer dielectric layer and respectively connected to the third metal oxide layer.
7. The semiconductor device of claim 6, wherein the third metal oxide layer comprises a third doped region, a fourth doped region and a second channel region between the third doped region and the fourth doped region, the interlayer dielectric layer comprises a third contact hole overlapping the third doped region and a fourth contact hole overlapping the fourth doped region, the second source is connected to the third doped region through the third contact hole, and the second drain is connected to the fourth doped region through the fourth contact hole.
8. The semiconductor device of claim 6, wherein the material of the first gate and the second gate comprises tungsten, molybdenum, platinum, gold, or a combination thereof.
9. The semiconductor device of claim 3, wherein the first metal oxide layer comprises a fifth doped region and a sixth doped region, wherein the fifth doped region and the sixth doped region contact the bottom of the first doped region and the bottom of the second doped region, respectively.
10. The semiconductor device of claim 9, wherein a thickness of said fifth doped region and a thickness of said sixth doped region are less than a thickness of said first metal oxide layer.
11. The semiconductor device according to claim 1, wherein a material of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer comprises indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, or indium tungsten zinc oxide.
12. The semiconductor device of claim 1, wherein an oxygen concentration of said first metal oxide layer is less than an oxygen concentration of said third metal oxide layer.
13. A method of manufacturing a semiconductor device, comprising:
forming a first thin film transistor on a substrate, the first thin film transistor including a first metal oxide layer and a second metal oxide layer stacked, wherein an oxygen concentration of the first metal oxide layer is less than an oxygen concentration of the second metal oxide layer, a thickness of the second metal oxide layer is less than a thickness of the first metal oxide layer, and a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer; and
forming a second thin film transistor on the substrate, wherein the second thin film transistor is electrically connected with the first thin film transistor, the second thin film transistor comprises a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously.
14. The method of claim 13, wherein the steps of forming the first thin film transistor on the substrate and forming the second thin film transistor on the substrate comprise:
forming a first metal oxide pattern on the substrate, wherein the first metal oxide pattern comprises the first metal oxide layer;
forming a second metal oxide pattern on the first metal oxide pattern and the substrate, wherein the second metal oxide pattern includes the second metal oxide layer and the third metal oxide layer;
forming a gate dielectric layer on the second metal oxide pattern, wherein the gate dielectric layer has an opening exposing the second metal oxide layer;
forming a first gate on the gate dielectric layer, wherein the first gate contacts the second metal oxide layer through the opening;
forming a second gate, wherein the third metal oxide layer overlaps the second gate;
performing a doping process on the second metal oxide layer and the third metal oxide layer;
forming an interlayer dielectric layer on the gate dielectric layer;
forming a first source, a first drain, a second source and a second drain on the interlayer dielectric layer, wherein the first source and the first drain are respectively connected to the second metal oxide layer, and the second source and the second drain are respectively connected to the third metal oxide layer.
15. The method of claim 14, wherein the doping process is performed to form a first doped region, a second doped region and a first channel region between the first doped region and the second doped region in the second metal oxide layer, and to form a third doped region, a fourth doped region and a second channel region between the third doped region and the fourth doped region in the third metal oxide layer.
16. The method of claim 15, wherein the doping process is performed to form a fifth doped region and a sixth doped region in the first metal oxide layer.
17. The method of claim 14, wherein the doping process is performed with the first gate and the second gate as masks.
18. The method for manufacturing a semiconductor device according to claim 14, further comprising:
performing one or more etching processes to form a first contact hole, a second contact hole, a third contact hole and a fourth contact hole through the interlayer dielectric layer and the gate dielectric layer, wherein the first contact hole and the second contact hole are overlapped with the second metal oxide layer, and the third contact hole and the fourth contact hole are overlapped with the third metal oxide layer; and
and forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole.
19. The method of claim 14, wherein the first source and the first drain extend through the second metal oxide layer, and the second source and the second drain extend through the third metal oxide layer.
CN202210864293.2A 2021-12-09 2022-07-21 Semiconductor device and method for manufacturing the same Pending CN115050761A (en)

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