KR102241097B1 - Thin film comprising two-dimensional electron gas, method of fabricating of the same, and transistor comprising the same - Google Patents

Abstract

A manufacturing method of an active layer of a transistor comprises the steps of: providing a substrate in a chamber; forming a first material layer on the substrate by providing a first metal precursor including indium; providing a second metal precursor including gallium to form a second material layer on the first material layer; and forming a third material layer on the second material layer by providing a third metal precursor including zinc. A stacked structure including the first material layer, the second material layer, and the third material layer is an active layer of the transistor. The stacked structure may include a two-dimensional electron gas formed between the first material layer and the second material layer.

Description

Thin film comprising two-dimensional electron gas, method of fabricating of the same, and transistor comprising the same

The present application relates to a thin film including a two-dimensional electron gas, a method for manufacturing the same, and a transistor including the same, and more particularly, a thin film including a two-dimensional electron gas formed between metal oxide thin films, a method for manufacturing the same, and It relates to a transistor including the same.

In the display field, amorphous silicon-based transistors were mainly used. However, high-resolution and organic light-emitting devices are applied to displays, and there is a need for a transistor with improved mobility than an amorphous silicon-based transistor.

Accordingly, research and development of a high electron mobility transistor (HEMT) having a two-dimensional electron gas as a channel are being conducted. The two-dimensional electron gas refers to a thin layer formed by inducing electrons at the interface of heterogeneous materials with different polarization rates. That is, electrons are induced at a high density in the thin layer, so that mobility can be easily improved. The heterogeneous material is generally selected from metal oxides or metal nitrides.

The high mobility transistor is mainly controlled by the electron concentration of the two-dimensional electron gas. Accordingly, in order to improve the mobility of a high electron mobility transistor, a method of injecting electric charges into a two-dimensional electron gas through a metal gate electrode or the like, or a method of controlling the crystal structure of each of the heterogeneous materials has been studied.

For example, in Korean Patent Registration Publication No. 10-1813178 (application number 10-2011-0061798), forming a first material layer, heat-treating the first material layer, and on the first material layer Forming a second material layer inducing a 2-dimensional electron gas (2DEG) on the first material layer, wherein the heat treatment of the first material layer increases the surface roughness of the first material layer. Disclosed is a method of forming a laminated structure performed under the conditions described above.

One technical problem to be solved by the present application is to provide a thin film formed of indium-gallium-zinc oxide with improved mobility and reliability, and including a two-dimensional electron gas, a method of manufacturing the same, and a transistor including the same.

Another technical problem to be solved by the present application is to provide a thin film including a two-dimensional electron gas whose electrical properties are controlled according to the thickness of an indium oxide thin film, a method of manufacturing the same, and a transistor including the same.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problem, the present application provides a method of manufacturing an active layer of a transistor.

According to an embodiment, the method of manufacturing the active layer of the transistor includes: providing a substrate in a chamber, forming a first material layer on the substrate by providing a first metal precursor containing indium, and forming a gallium Providing a second metal precursor containing, forming a second material layer on the first material layer, and providing a third metal precursor containing zinc, a third material layer on the second material layer Including the step of forming, wherein the stacked structure including the first material layer, the second material layer, and the third material layer is an active layer of a transistor, and the stacked structure includes the first material layer and the It may include a two-dimensional electron gas formed between the second material layer.

According to an embodiment, forming the first material layer, forming the second material layer, and forming the third material layer are defined as one unit process, and the unit process is It is repeatedly performed, including manufacturing the laminated structure, and may include a two-dimensional electron gas formed between the first material layer and the third material layer.

According to an embodiment, the forming of the first material layer is performed for a first time, and the forming of the second material layer is performed for a time longer than the first time, and the third material Forming the layer may include performing the same time as the first time.

According to an embodiment, the first material layer is formed in a first deposition cycle, the second material layer is formed in a second deposition cycle, and the third material layer is formed in a third deposition cycle. , The first deposition cycle, the second deposition cycle, and the third deposition cycle may include those having a ratio of greater than 16:1:1 and less than 40:1:1.

According to an embodiment, the first metal precursor is 3-dimethylaminopropyl)-dimethyl indium (DADI), trimethyl indium (TMI), triethyl indium (TEIn), bis(trimethylsilyl)amidodiethyl indium ( InCA-1), In(CH ₃ ) ₃ [CH ₃ OCH ₂ CH ₂ NtBu(Hs-In) or (CH ₃ ) ₃ In(CH ₃ )2N((CH ₂ ) ₃ CH ₃ (L2i-8) It may include at least any one.

According to an embodiment, the second metal precursor may include trimethyl gallium.

According to an embodiment, the third metal precursor may include diethyl zinc.

According to an embodiment, the first material layer, the second material layer, and the third material layer may include those manufactured by a plasma enhanced atomic layer deposition method.

In order to solve the above technical problem, the present application provides an active layer of a transistor.

According to an embodiment, the active layer of the transistor includes a first material layer including indium oxide, a second material layer disposed on the first material layer and including gallium oxide, and the second material layer. It is disposed and includes a third material layer including zinc oxide, and may include a two-dimensional electron gas formed between the first material layer and the second material layer.

According to an embodiment, a stacked structure including the first material layer, the second material layer, and the third material layer is defined as one unit layer, and the unit layer is stacked to form the first material layer. And a two-dimensional electron gas formed between the third material layer.

According to an embodiment, the first material layer may include meso-crystalline.

According to an embodiment, the first material layer may have a first thickness, and the second material layer and the third material layer may include those having a thickness thinner than the first thickness.

In order to solve the above technical problem, the present application provides a transistor.

According to an embodiment, the transistor includes a substrate, a gate electrode disposed on the substrate, an active layer of the transistor according to claim 9 disposed on the gate electrode, and both sides of the active layer disposed on the gate electrode. Each may include a source electrode and a drain electrode in contact.

According to an embodiment of the present invention, a method of manufacturing an active layer of a transistor includes providing a substrate in a chamber, providing a first metal precursor containing indium, and forming a first material layer on the substrate, Providing a second metal precursor including gallium to form a second material layer on the first material layer, and providing a third metal precursor including zinc to form a third metal precursor on the second material layer. It may include forming a material layer.

That is, according to an embodiment, the active layer having the first structure may be a stacked structure including the first material layer, the second material layer, and the third material layer. In this case, the first material layer may be formed thicker than the second material layer and the third material layer, and the first material layer may have a meso-crystalline having a crystalline phase partially in the amorphous matrix. I can. Accordingly, the active layer having the first structure including the two-dimensional electron gas between the first material layer and the second material layer may be manufactured.

According to another embodiment, forming the first material layer, forming the second material layer, and forming the third material layer may be defined as one unit process, and the unit process By performing this repeatedly, the active layer having the second structure can be prepared. In other words, compared to the active layer having the first structure, the active layer having the second structure may further include the first material layer on the third material layer. Accordingly, the active layer having the second structure may include the two-dimensional electron gas between the first material layer and the second material layer, and between the first material layer and the third material layer. .

In this case, the mobility of the transistor including the two-dimensional electron gas may be adjusted according to a ratio of the thicknesses of the first material layer, the second material layer, and the third material layer.

Specifically, the first material layer, the second material layer, and the third material layer may be prepared by plasma enhanced atomic layer deposition, and, respectively, a first deposition cycle, a second deposition cycle, and a third deposition It can be formed in a cycle. In this case, when the first deposition cycle, the second deposition cycle, and the third deposition cycle have a ratio of greater than 16:1:1 and less than 40:1:1, the transistor having improved mobility may be manufactured have.

1 is a flowchart illustrating a method of manufacturing an active layer of a transistor according to an exemplary embodiment of the present invention.
2 is a schematic schematic diagram of an active layer of a transistor having a first structure according to an embodiment of the present invention.
3 is a schematic schematic diagram of an active layer of a transistor having a second structure according to an embodiment of the present invention.
4 is a diagram illustrating a crystal structure of an active layer of a transistor having a second structure according to an exemplary embodiment of the present invention.
5 is a diagram illustrating a charge transfer path of an active layer having a second structure according to an exemplary embodiment of the present invention.
6 is a schematic schematic diagram of a transistor according to an embodiment of the present invention.
7 is a diagram illustrating a growth per cycle (GPC) and a refractive index (RI) of an active layer of a transistor according to an exemplary embodiment of the present invention.
8 is a diagram illustrating transmittance of an active layer of a transistor according to an exemplary embodiment of the present invention, and an inserted drawing is a diagram illustrating an optical bandgap of an active layer of a transistor according to an exemplary embodiment of the present invention.
9 is a diagram illustrating an X-ray diffraction pattern (XRD) of an active layer of a transistor according to an exemplary embodiment of the present invention.
10 to 12 are diagrams illustrating binding energy of 1s oxygen in an active layer of a transistor according to an exemplary embodiment of the present invention.
13 is a diagram showing an area ratio of metal-oxygen bonds, hydrogen-oxygen bonds, and oxygen deficient in an active layer of a transistor according to an embodiment of the present invention.
14 is a diagram illustrating hole mobility of an active layer of a transistor according to an exemplary embodiment of the present invention.
15 to 17 are diagrams illustrating a transfer curve of a transistor according to an exemplary embodiment of the present invention.
18 is a diagram showing an output curve of a transistor according to Experimental Example 2-5 of the present invention.
19 to 21 are diagrams showing transfer curves including saturation mobility of transistors according to Experimental Examples 2-1 to 2-5 of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In the present specification, when a component is referred to as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed therebetween. In addition, in the drawings, thicknesses of films and regions are exaggerated for effective description of technical content.

In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. In addition, in the present specification,'and/or' has been used to mean including at least one of the elements listed before and after.

In the specification, expressions in the singular include plural expressions unless the context clearly indicates otherwise. In addition, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, components, or a combination thereof described in the specification, and one or more other features, numbers, steps, or configurations. It is not to be understood as excluding the possibility of the presence or addition of elements or combinations thereof.

In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a flowchart illustrating a method of manufacturing an active layer of a transistor according to an embodiment of the present invention, FIG. 2 is a schematic schematic diagram of an active layer of a transistor having a first structure according to an embodiment of the present invention, and FIG. 3 is A schematic schematic diagram of an active layer of a transistor having a second structure according to an embodiment of the present invention, FIG. 4 is a view showing a crystal structure of an active layer of a transistor having a second structure according to an embodiment of the present invention, and FIG. 5 is A diagram showing a charge transfer path of an active layer having a second structure according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 100 may be provided in the chamber (S110).

According to an embodiment, the substrate 100 may be at least one of a silicon substrate, a glass substrate, or a plastic substrate.

Specifically, for example, the plastic substrate may be formed of at least one of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyimide (PI), or polyethylene terephthalate (PET). I can.

Referring to FIGS. 1 and 2, a first metal precursor including indium may be provided to form a first material layer 110a on the substrate 100 (S120 ).

According to an embodiment, the first metal precursor is 3-dimethylaminopropyl-dimethyl indium represented by <Formula 1> below, and trimethyl represented by <Formula 2> below. Indium, triethyl indium represented by <Chemical Formula 3> below, bis(trimethylsilyl)amidodiethyl indium represented by <Chemical Formula 4> below , Trimethyl[N-(2-methoxyethyl)-2-methylpropan-2-amine]indium represented by <Chemical Formula 5> below ]indium or at least one of dimethyl butyl amino trimethyl indium represented by <Chemical Formula 6> below.

<Formula 1>

<Formula 2>

<Formula 3>

<Formula 4>

<Formula 5>

<Formula 6>

According to an embodiment, the first material layer 110a may be manufactured in a first deposition cycle by a plasma enhanced atomic layer deposition method.

For example, the first deposition cycle includes providing the first metal precursor in the chamber, purging the first metal precursor remaining in the chamber, providing plasma in the chamber, and It may include purging the residue within. Specifically, for example, the first deposition cycle may be performed under a pressure condition of 1.2torr and a temperature condition of 200°C.

Providing the first metal precursor may include providing at least one of the first metal precursors from <Chemical Formula 1> to <Chemical Formula 6> in the chamber. Accordingly, the first metal precursor may be adsorbed on the substrate 100.

Purging the first metal precursor may include purging the first metal precursor remaining in the chamber without being adsorbed on the substrate 100 using argon gas.

The providing of the plasma may include providing a mixed gas including an oxygen gas and an argon gas in the chamber and simultaneously applying a plasma to the chamber. Accordingly, the first metal precursor adsorbed on the substrate 100 and the oxygen gas may react. For example, the step of providing the plasma may be performed for the first time, and the mixed gas may include the oxygen gas and the argon gas in a ratio of 50:50. Specifically, for example, the first time may be 5 seconds.

Purging the residue may include purging the impurities generated in the chamber by the reaction and the oxygen gas remaining in the chamber using the argon gas.

Specifically, the first material layer 110a having a first thickness may be manufactured by repeatedly performing the first deposition cycle 4 to 40 times. For example, the first thickness may be 0.3 nm to 3.0 nm, and the first material layer 110a may be indium oxide.

As described above, even if the first deposition cycle is repeatedly performed within the range of 4 to 40 times, the thin films manufactured by each of the first deposition cycles, as shown in FIG. 2, are not identified and separated from each other. May not. That is, FIG. 2 is for displaying that the first material layer 110a is manufactured by repeatedly performing the first deposition cycle a plurality of times, and even if the first deposition cycle is repeatedly performed a plurality of times, a single configuration The first material layer 110a of may be manufactured.

A second metal precursor containing gallium may be provided to form a second material layer 120a on the first material layer 110a (S130).

According to an embodiment, the second metal precursor is trimethyl gallium represented by <Chemical Formula 7> below, triethyl gallium represented by <Chemical Formula 8> below, and <Chemical Formula 9> It may be at least one of tris (dimethylamido) gallium, gallium tri-methoxide, or gallium tri-ethoxide denoted by >.

<Formula 7>

<Formula 8>

<Formula 9>

According to an embodiment, the second material layer 120a may be manufactured in a second deposition cycle by a plasma enhanced atomic layer deposition method.

For example, the second deposition cycle includes providing the second metal precursor in the chamber, purging the second metal precursor remaining in the chamber, providing plasma in the chamber, and It may include purging the residue within. Specifically, for example, the second deposition cycle may be performed under a pressure condition of 1.2torr and a temperature condition of 200°C.

Providing the second metal precursor may include providing at least one of the second metal precursors from <Chemical Formula 7> to <Chemical Formula 9> in the chamber. Accordingly, the second metal precursor may be adsorbed on the first material layer 110a.

Purging the second metal precursor may include purging the second metal precursor remaining in the chamber without being adsorbed on the first material layer 110a using argon gas.

The providing of the plasma may include providing a mixed gas including an oxygen gas and an argon gas in the chamber and simultaneously applying a plasma to the chamber. Accordingly, the second metal precursor adsorbed on the first material layer 110a and the oxygen gas react, so that the second material layer 120a may be manufactured. For example, the providing of the plasma may be performed for a time longer than the first time, and the mixed gas may include the oxygen gas and the argon gas in a ratio of 50:50. Specifically, for example, the step of providing the plasma may be performed for 15 seconds.

The purging of the residue includes purging the impurities generated in the chamber by the manufacturing of the second material layer 120a and the oxygen gas remaining in the chamber using the argon gas. can do.

The second material layer 120a manufactured as described above may be formed to have a thickness thinner than the first thickness. Specifically, for example, the second material layer 120a may be formed to a thickness of 0.14 nm, and the second material layer 120a may be gallium oxide.

A third metal precursor including zinc may be provided so that the third material layer 130a may be formed on the second material layer 120a (S140).

According to an embodiment, the third metal precursor is trimethyl zinc represented by <Chemical Formula 10> below, triethyl zinc represented by <Chemical Formula 11>, or <Chemical Formula 11> below. It may be at least one of zinc acetate represented by 12>.

<Formula 10>

<Formula 11>

<Formula 12>

According to an embodiment, the third material layer 130a may be manufactured in a third deposition cycle by a plasma enhanced atomic layer deposition method.

For example, the third deposition cycle includes providing the third metal precursor in the chamber, purging the third metal precursor remaining in the chamber, providing plasma in the chamber, and It may include purging the residue within. Specifically, for example, the third deposition cycle may be performed under a pressure condition of 1.2torr and a temperature condition of 200°C.

Providing the third metal precursor may include providing at least one of the third metal precursors from <Chemical Formula 10> to <Chemical Formula 12> in the chamber. Accordingly, the third metal precursor may be adsorbed on the second material layer 120a.

Purging the third metal precursor may include purging the third metal precursor remaining in the chamber without being adsorbed on the second material layer 120a using argon gas.

The providing of the plasma may include providing a mixed gas including an oxygen gas and an argon gas in the chamber and simultaneously applying a plasma to the chamber. Accordingly, the third metal precursor adsorbed on the second material layer 120a and the oxygen gas react, so that the third material layer 130a may be manufactured. For example, the providing of the plasma may be performed for the same time as the first time, and the mixed gas may include the oxygen gas and the argon gas in a ratio of 50:50. Specifically, for example, the step of providing the plasma may be performed for 5 seconds.

The purging of the residue includes purging the impurities generated in the chamber by the manufacturing of the third material layer 130a and the oxygen gas remaining in the chamber using the argon gas. can do.

The third material layer 130a manufactured as described above may be formed to have a thickness thinner than the first thickness. Specifically, for example, the third material layer 130a may be formed to a thickness of 0.15 nm, and the third material layer 130a may be zinc oxide.

As described above, according to an embodiment, a stacked structure including the first material layer 110a, the second material layer 120a, and the third material layer 130a on the substrate 100 Can be prepared. Specifically, for example, as shown in FIG. 2, the stacked structure may be an active layer 200a of a transistor having a first structure.

The first material layer 110a manufactured as described above includes an amorphous phased matrix, and has a meso-crystalline having a partially crystrallized region in the matrix. I can. In addition, the first material layer 110a may be made thicker than the second material layer 120a and the third material layer 130a. Accordingly, a two-dimensional electron gas may be formed between the first material layer 110a and the second material layer 120a in contact with the first material layer 110a. That is, the active layer 200a having the first structure shown in FIG. 2 may include the two-dimensional electron gas.

According to another embodiment, as illustrated in FIG. 3, the active layer 200b having a second structure may be manufactured. Specifically, forming the first material layer 110a described above with reference to FIGS. 1 to 2, forming the second material layer 120a, and forming the third material layer 130a The step of performing may be defined as one unit process, and the active layer 200b having the second structure may be manufactured by repeatedly performing the unit process.

In other words, the first material layer 110b on the active layer 200a having the first structure described above with reference to FIG. 2, and the second material layer 120b on the first material layer 110b. , And the active layer 200b having the second structure including the third material layer 130b on the second material layer 120b may be manufactured.

As described above, the first material layers 110a and 110b may have meso-crystalline, and further, the second material layers 120a and 120b and the third material layers 130a and 130b ) Can be made thicker than. Accordingly, the active layer 200b having the second structure is formed between the first material layers 110a and 110b and the second material layers 120a and 120b, and between the first material layers 110a and 110b. The two-dimensional electron gas may be included between the third material layers 130a and 130b. That is, the active layer 200b having the second structure is between the first material layers 110a and 110b and the third material layers 130a and 130b compared to the active layer 100b having the first structure. It may further include the two-dimensional electron gas formed in.

In addition, the active layer 200b having the second structure may have a relatively low band gap. Accordingly, the mobility of the active layer 200b having the second structure can be easily improved. Specifically, for example, the active layer 200b having the second structure may have a band gap of about 2.7 eV and a hole mobility of ^{3.6 to 11 cm 2 /Vs.}

As described above with reference to FIGS. 1 to 2, the first material layers 110a and 110b may be formed in a first deposition cycle, and the second material layers 120a and 120b may be formed in a second deposition cycle. In addition, the third material layers 130a and 130b may be formed in a third deposition cycle. For example, the first deposition cycle, the second deposition cycle, and the third deposition cycle may have a ratio of 4:1:1 to 40:1:1, and specifically, for example, 16:1 It may have a ratio greater than :1 and less than 40:1:1.

That is, the second material layers 120a and 120b and the third material layers 130a and 130b may be manufactured to be thinner than the first material layers 110a and 110b. Accordingly, the second material layers 120a and 120b and the third material layers 130a and 130b in contact with the second material layers 120a and 120b may be mixed. That is, as shown in FIG. 3, the second material layers 120a and 120b and the third material layers 130a and 130b may not be identified as being separated from each other. Accordingly, the second material layers 120a and 120b and the third material layers 130a and 130b may be formed of one oxide layer.

In other words, the active layer having the second structure may be formed of a stacked structure of the first material layers 110a and 110b and the oxide layer. In this case, the first material layers 110a and 110b and the oxide layer may be mixed at the interface between the oxide layer and the first material layers 110a and 110b. Specifically, for example, as described above, the first material layers 110a and 110b may be the indium oxide, the second material layers 120a and 120b may be gallium oxide, and the third material The layers 130a and 130b may be zinc oxide.

Accordingly, the active layer 200b having the second structure includes a plurality of stacked indium oxide layers 310 and the indium-gallium-zinc oxide layer 320 formed between the indium oxide layer 310. It may have a structure of the active layer 300 shown in FIG. 4 including. In this case, the indium oxide layer 310 may correspond to the first material layers 110a and 110b, and the indium-gallium-zinc oxide layer 320 may be the first material layers 110a and 110b, It may correspond to a region in which the second material layers 120a and 120b and the third material layers 130a and 130b are mixed.

In addition, specifically, for example, as described above with reference to FIGS. 1 and 2, the first material layers 110a and 110b, the second material layers 120a and 120b, and the third material layer 130a , 130b) may be formed to a relatively thin thickness of 0.14 nm to 3.0 nm.

Accordingly, the active layer 300 is a superlattice formed by repeatedly stacking a unit including the indium-gallium-zinc oxide layer 320 on the indium oxide layer 310 and the indium oxide layer 310 It can have a (superlattice) structure.

As described above with reference to FIGS. 1 to 3, the active layer 300 may include the indium oxide layer 310 and the two-dimensional electron gas formed between the indium-gallium-zinc oxide layer 320. have. As shown in FIG. 5, the active layer 300 may include a charge 330 in the active layer 300. The electric charge 330 may move along the two-dimensional electron gas, and accordingly, the conductivity of the active layer 300 may be improved.

As described above with reference to FIGS. 1 to 3, the active layers 200a and 200b include the first material layers 110a and 100b, the second material layers 120a and 120b, and the third material layer ( Units including 130a and 130b) may be repeatedly stacked to be formed.

In this case, the first material layers 110a and 100b may be formed thicker than the second material layers 120a and 120b and the third material layers 130a and 130b. At the same time, the first material layers 110a and 100b may have meso-crystalline. Accordingly, between the first material layer (110a, 100b) and the second material layer (120a, 120b), and between the first material layer (110a, 100b) and the third material layer (130a, 130b) The two-dimensional electron gas may be formed therebetween.

As described above, the second material layers 120a and 120b and the third material layers 130a and 130b may be formed to be thinner than the first material layers 110a and 100b. Specifically, the second material layers 120a and 120b and the third material layers 130a and 130b may be manufactured by performing one second deposition cycle and one third deposition cycle, respectively. . Accordingly, the first material layers 110a and 100b and the second material layer 120a are formed in a local area including the second material layers 120a and 120b and the third material layers 130a and 130b. , 120b), and the third material layers 130a and 130b may be formed by mixing with each other. That is, as shown in FIGS. 4 and 5, the indium oxide layer 310 corresponding to the first material layers 110a and 100b, and the indium-gallium-zinc oxide layer corresponding to the mixed region ( The active layer 300 including 320 may be formed. As described above, the two-dimensional electron gas may be formed between the indium oxide layer 310 and the indium-gallium-zinc oxide layer 320.

That is, the active layers 200a, 200b, and 300 may include the two-dimensional electron gas capable of moving the charges 330 distributed in the active layers 200a, 200b, and 300 at a relatively high speed. Accordingly, the transistor including the active layers 200a, 200b, and 300 may have high mobility.

6 is a schematic schematic diagram of a transistor according to an embodiment of the present invention.

Referring to FIG. 6, a substrate 400, a gate electrode 410 formed on the substrate 400, a gate insulating layer 420 formed on the gate electrode, and an active layer disposed on the gate insulating layer 420 A transistor including 430 and a source electrode 440s and a drain electrode 440d respectively contacting both sides of the active layer 430 disposed on the gate insulating layer 420 may be manufactured.

According to an embodiment, the substrate 400 may be at least one of a silicon substrate, a glass substrate, or a plastic substrate.

Specifically, for example, the plastic substrate may be formed of at least one of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyimide (PI), or polyethylene terephthalate (PET). I can.

According to an embodiment, the gate electrode 410 may be formed of at least one of copper (Cu), aluminum (Al), or molybdenum (Mo).

According to an embodiment, the gate insulating layer 420 may be formed of at least one of silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide.

According to an embodiment, each of the source electrode 440s and the drain electrode 440d may be formed of at least one of a metal or a conductive oxide.

For example, the metal may include at least one of molybdenum (Mo), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or chromium (Cr).

For another example, the conductive oxide may include at least one of indium (In), zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), or magnesium (Mg). Specifically, for example, the conductive oxide may be at least one of indium-tin oxide (ITO) or indium-gallium-zinc-oxide (IGZO).

According to an embodiment, the active layer 430 may be the active layers 200a, 200b, and 300 described above with reference to FIGS. 1 to 5.

As described above, the active layers 200a, 200b, and 300 may include a two-dimensional electron gas, and accordingly, the charge 330 moves along the two-dimensional electron gas, thereby facilitating the mobility of the transistor. It can be improved. Specifically, for example, the mobility of the transistor may have a value of ^{about 75 cm 2 /Vs or less.}

Hereinafter, a method of manufacturing an active layer of a transistor and evaluation results of characteristics according to a specific experimental example of the present invention are described.

Preparation of the active layer of the transistor according to Experimental Example 1-1

Si/SiO _{2 as the} substrate, 3-dimethylaminopropyl-dimethyl indium as the first metal precursor, trimethyl gallium as the second metal precursor, and the third Trimethyl zinc was prepared as a metal precursor.

After the Si/SiO ₂ substrate was charged into the chamber, the temperature in the chamber was maintained at 200°C.

The first deposition cycle of “injecting the first metal precursor → purge gas (argon gas) injection → oxygen/argon plasma 5 seconds, 1.2 torr → purge gas (argon gas) injection” in the chamber was repeated 4 times, and the substrate The first material layer was formed thereon.

The second deposition cycle of “injecting the second metal precursor → purge gas (argon gas) injection → oxygen/argon plasma 15 seconds, 1.2 torr → purge gas (argon gas) injection” in the chamber is repeated once, The second material layer was formed on the first material layer.

The third deposition cycle of “injecting the third metal precursor → purge gas (argon gas) injection → oxygen/argon plasma 5 seconds, 1.2 torr → purge gas (argon gas) injection” in the chamber is repeated once, The third material layer was formed on the 2 material layer.

The step of forming the first material layer, the step of forming the second material layer, and the step of forming the third material layer are defined as one unit process, and the unit process is repeatedly performed. The active layer of the transistor according to 1-1 was fabricated.

Preparation of the active layer of the transistor according to Experimental Example 1-2

It was carried out in the same manner as the method of manufacturing the active layer of the transistor according to Experimental Example 1-1, but the first deposition cycle was repeated 8 times instead of 4 times, thereby manufacturing the active layer of the transistor according to Experimental Example 1-2.

Preparation of the active layer of the transistor according to Experimental Example 1-3

It was performed in the same manner as the method of manufacturing the active layer of the transistor according to Experimental Example 1-1, but the first deposition cycle was repeated 12 times instead of 4 times to prepare the active layer of the transistor according to Experimental Example 1-3.

Preparation of the active layer of the transistor according to Experimental Example 1-4

It was carried out in the same manner as the method of manufacturing the active layer of the transistor according to Experimental Example 1-1, but the first deposition cycle was repeated 16 times instead of 4 times, thereby manufacturing the active layer of the transistor according to Experimental Example 1-5.

Preparation of the active layer of the transistor according to Experimental Example 1-5

It was performed in the same manner as the method of manufacturing the active layer of the transistor according to Experimental Example 1-1, but the first deposition cycle was repeated 20 times instead of 4 times, thereby manufacturing the active layer of the transistor according to Experimental Example 1-5.

Preparation of the active layer of the transistor according to Experimental Example 1-6

It was carried out in the same manner as the method of manufacturing the active layer of the transistor according to Experimental Example 1-1, but the first deposition cycle was repeated 40 times instead of 4 times, thereby manufacturing the active layer of the transistor according to Experimental Example 1-6.

Preparation of the active layer of the transistor according to Comparative Example 1-1

After the Si/SiO ₂ substrate was charged into the chamber, the temperature in the chamber was maintained at 200°C.

In the chamber, "the 3-dimethylaminopropyl-dimethyl indium ((3-dimethylaminopropyl)-dimethyl indium) injection → purge gas (argon gas) injection → oxygen/argon plasma 5 seconds, 1.2 torr → purge gas (argon gas) injection By repeating the deposition cycle of ", the active layer of the transistor according to Comparative Example 1-1 was manufactured.

In the method of manufacturing an active layer of a transistor according to Experimental Examples 1-1 to 1-6 described above, the number of repetitions of the first deposition cycle, the second deposition cycle, and the third deposition cycle are shown in Table 1 below. Was organized in.

First deposition cycle 2nd deposition cycle 3rd deposition cycle Experimental Example 1-1 4 One One Experimental Example 1-2 8 One One Experimental Example 1-3 12 One One Experimental Example 1-4 16 One One Experimental Example 1-5 20 One One Experimental Example 1-6 40 One One

7 is a diagram illustrating a growth per cycle (GPC) and a refractive index (RI) of an active layer of a transistor according to an exemplary embodiment of the present invention.

_{Referring to FIG. 7, the thickness of the first material layer (In 2} O ₃ ) of the active layer of the transistor according to Experimental Examples 1-1 to 1-5 of the present invention is written in Table 2 below.

In ₂ O ₃ thickness (nm) Experimental Example 1-1 0.3 Experimental Example 1-2 0.7 Experimental Example 1-3 1.0 Experimental Example 1-4 1.4 Experimental Example 1-5 1.8

As can be seen from <Table 1> and FIG. 7, the thickness of the active layer is proportional to the number of repetitions of the first deposition cycle. In addition, as described above, the first material layer (In ₂ O ₃ ), the thicknesses formed per deposition cycle of the second material layer (Ga ₂ O ₃ ) and the third material layer (ZnO) are written in <Table 3>.

Thickness formed per deposition cycle (nm/cycle) In ₂ O ₃ 0.08 Ga ₂ O ₃ 0.12 ZnO 0.22

On the other hand, as shown in FIG. 7, it can be seen that the refractive index of the active layer has a substantially constant value regardless of the number of repetitions of the first deposition cycle.

Accordingly, in order to check the element composition ratio included in the active layer of the transistor according to Experimental Examples 1-1 to 1-5 of the present invention, Experimental Example 1-1 measured using X-ray photoelectron spectroscopy (XPS) To the element composition ratio of the active layer of the transistor according to Experimental Example 1-5 are shown in Table 4 below.

In% Zn% Ga% O% Experimental Example 1-1 11.5 20.3 12.5 55.8 Experimental Example 1-2 16.4 17.6 9.9 56.1 Experimental Example 1-3 19.0 16.2 8.9 55.9 Experimental Example 1-4 22.1 14.0 8.2 55.7 Experimental Example 1-5 22.9 13.6 7.9 55.6

Referring to <Table 4>, as described above with reference to <Table 2> and FIG. 7, it can be seen that as the first deposition cycle increases, the ratio of the indium in the active layer increases.

8 is a diagram illustrating transmittance of an active layer of a transistor according to an exemplary embodiment of the present invention, and an inserted drawing is a diagram illustrating an optical bandgap of an active layer of a transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 8, it can be seen that the transmittance of the active layer of the transistor according to Experimental Examples 1-1 to 1-5 of the present invention decreases as the first deposition cycle increases in the range of 300 to 900 nm.

Referring to the inserted drawing of FIG. 8, it can be seen that when the first deposition cycle is less than 12 cycles, the absorbance of the active layer increases as the first deposition cycle increases. On the other hand, when the first deposition cycle is more than 12 cycles, it can be seen that the absorbance of the active layer becomes substantially constant as the first deposition cycle increases.

Referring to the inserted drawing of FIG. 8, the optical band gap of the active layer was confirmed as shown in Table 5 below.

Optical bandgap(eV) Experimental Example 1-1 2.98 Experimental Example 1-2 2.78 Experimental Example 1-3 2.71 Experimental Example 1-4 2.67 Experimental Example 1-5 2.67

As can be seen from <Table 5>, it can be seen that the band gap of the active layer exhibits a tendency substantially similar to the above-described absorbance. That is, when the first deposition cycle is less than 12 cycles, it can be seen that the band gap of the active layer decreases as the first deposition cycle increases. In addition, when the first deposition cycle is 12 cycles or more, it can be seen that the band gap of the active layer has a substantially similar value as the first deposition cycle increases.

9 is a diagram illustrating an X-ray diffraction pattern (XRD) of an active layer of a transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 9, the crystal structures of the active layers of the transistors according to Comparative Example 1-1 and Experimental Examples 1-1 to 1-5 of the present invention were confirmed.

As shown in FIG. 9, it can be seen that the active layers of the transistors according to Experimental Examples 1-1 to 1-5 have substantially the same peak. Accordingly, it was confirmed that the active layers of the transistors according to Experimental Examples 1-1 to 1-5 had substantially the same structure. That is, as described above with reference to FIGS. 1 to 3, the active layers of the transistors according to Experimental Examples 1-1 to 1-5 have meso-crystalline in the range of the first deposition cycle 4 to 20 times. Able to know.

Specifically, it can be seen that the active layers of the transistors according to Experimental Examples 1-1 to 1-5 have peaks at 25° and 45°. In this case, as the first deposition cycle increased, it was found that the peak increased at 25°, and the peak decreased substantially at 45°.

1 to 5, the active layers of the transistors according to Experimental Examples 1-1 to 1-5 were made of indium-gallium-zinc oxide, and the active layer of the transistor according to Comparative Example 1-1 was indium. It is made of oxide. Accordingly, it was confirmed that the active layer of the transistor according to Comparative Example 1-1 had a crystal structure different from that of the active layer of the transistors according to Experimental Examples 1-1 to 1-5.

10 to 12 are diagrams illustrating binding energy of 1s oxygen in an active layer of a transistor according to an exemplary embodiment of the present invention.

Referring to FIGS. 10 to 12, it can be seen the bonding distribution of oxygen elements included in the active layer of the transistors according to Experimental Examples 1-1 to 1-5 of the present invention.

As shown in FIGS. 10 to 12, it was confirmed that the oxygen atom has a bond of a metal-oxygen (MO), a metal-oxygen vacancy (MO _vac ), and a metal-hydroxyl group (M-OH).

It can be seen that in the metal-oxygen bonding, as the first deposition cycle increases, the intensity of the peak increases. On the other hand, it was confirmed that the intensity of the peak decreases as the first deposition cycle increases in the metal-oxygen vacancy, and the metal-hydroxyl group has a substantially similar value in the range of 4 to 20 times of the first metal deposition cycle. It was confirmed to have.

13 is a diagram showing an area ratio of metal-oxygen bonds, hydrogen-oxygen bonds, and oxygen deficient in an active layer of a transistor according to an embodiment of the present invention.

Referring to FIG. 13, the bonding distribution of the oxygen element described above with reference to FIG. 12 was confirmed according to the type of the metal. 7 and <Table 4>, it is confirmed that the amount of the indium element increases as the first metal deposition cycle increases in the active layers of the transistors according to Experimental Examples 1-1 to 1-5 of the present invention. I did.

Accordingly, as shown in FIG. 13, it can be seen that the ratio of indium-oxygen bonds increases as the first metal deposition cycle increases in the active layer. On the other hand, as described above with reference to <Table 4>, it can be seen that the ratio of the gallium element and the zinc element contained in the active layer is relatively reduced compared to the indium. Accordingly, it can be seen that the ratio of gallium-oxygen bonds or zinc-oxygen bonds decreases as the first metal deposition cycle increases.

On the other hand, it can be seen that the hydrogen-oxygen bond (hydroxyl group) has a substantially constant value for the range of the first metal deposition cycle 4 to 20 times.

In addition, as shown in FIG. 13, it can be seen that the proportion of oxygen deficient in the active layer increases as the first metal deposition cycle increases.

14 is a diagram illustrating hole mobility of an active layer of a transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 14, hole mobility in an active layer of a transistor according to Experimental Examples 1-3 and 1-5 of the present invention in a temperature range below room temperature is shown. At this time, the charge density and hole mobility at room temperature of the active layer of the transistor according to Experimental Examples 1-1 to 1-5 of the present invention were written in Table 6 below.

Carrier density(/cm ³ ) Hall mobility(cm ² /Vs) Experimental Example 1-1 2.7X10 ¹⁴ 3.6 Experimental Example 1-2 5.9X10 ¹⁶ 8.5 Experimental Example 1-3 1.8X10 ¹⁷ 9.6 Experimental Example 1-4 4.2X10 ¹⁷ 9.9 Experimental Example 1-5 7.1X10 ¹⁷ 10.9

As can be seen from <Table 6>, it can be seen that the charge density increases as the first metal deposition cycle increases. In addition, it was confirmed that the hole mobility was also improved as the first metal deposition cycle increased. In addition, as shown in FIG. 14, the active layer of the transistor according to Experimental Example 1-3 was The hole mobility decreased relatively quickly. On the other hand, it was confirmed that the hole mobility in the active layer of the transistor according to Experimental Example 1-5 decreased relatively slowly as the temperature decreased.

Hereinafter, a method of manufacturing a transistor according to a specific experimental example of the present invention and a result of evaluation of characteristics will be described.

Fabrication of a transistor according to Experimental Example 2-1

After 100 nm of a silicon oxide (SiO ₂ ) thin film was prepared on the Si/SiO ₂ substrate, the active layer of the transistor according to Experimental Example 1-1 was formed to a thickness of 20 nm.

Indium-tin oxide (ITO) was patterned to contact both sides of the active layer disposed on the silicon oxide thin film to have a thickness of 100 nm, thereby manufacturing a transistor according to Experimental Example 2-1.

Fabrication of a transistor according to Experimental Example 2-2

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, except that the active layer of the transistor according to Experimental Example 1-2 was manufactured instead of the active layer of the transistor according to Experimental Example 1-1, and Experimental Example 2-2. According to the transistor was fabricated.

Fabrication of a transistor according to Experimental Example 2-3

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, except that the active layer of the transistor according to Experimental Example 1-3 was prepared instead of the active layer of the transistor according to Experimental Example 1-1, and Experimental Example 2-3. The transistor according to was manufactured.

Fabrication of a transistor according to Experimental Example 2-4

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, except that the active layer of the transistor according to Experimental Example 1-4 was prepared instead of the active layer of the transistor according to Experimental Example 1-1, and Experimental Example 2-4. The transistor according to was manufactured.

Fabrication of a transistor according to Experimental Example 2-5

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, except that the active layer of the transistor according to Experimental Example 1-5 was prepared instead of the active layer of the transistor according to Experimental Example 1-1, and Experimental Example 2-5. The transistor according to was manufactured.

Fabrication of a transistor according to Experimental Example 2-6

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, except that the active layer of the transistor according to Experimental Example 1-6 was prepared instead of the active layer of the transistor according to Experimental Example 1-1, and Experimental Example 2-6. The transistor according to was manufactured.

Fabrication of a transistor according to Comparative Example 2-1

It was carried out in the same manner as the method of manufacturing the transistor according to Experimental Example 2-1, but the active layer of the transistor according to Comparative Example 1-1 was prepared instead of the active layer of the transistor according to Experimental Example 1-1, and Comparative Example 2-1. The transistor according to was manufactured.

15 to 17 are diagrams illustrating a transfer curve of a transistor according to an exemplary embodiment of the present invention.

15 to 17, Experimental Example 2-1 (FIG. 15(a)), Experimental Example 1-3 (FIG. 15(b)), Experimental Example 1-5 (( _{a)), when the drain voltage (V D} ) applied to the transistor according to Experimental Example 1-6 (FIG. 16(b)), and Comparative Example 2-1 (FIG. 17) is 0.1V and 20.1V, the above The current-voltage characteristics of the transistor were observed. Accordingly, the measured transistor characteristics are written in Table 7 below.

V _th
(V) μ _eff
(cm ² /Vs) μ _sat
(cm ² /Vs) SS
(V/decade) Hysteresis
(V) Experimental Example 2-1 2.3±0.3 4.8±0.2 9.9±0.1 0.34±0.03 0.56±0.1 Experimental Example 2-2 1.6±0.2 15.7±0.2 18.3±0.3 0.29±0.03 0.21±0.07 Experimental Example 2-3 0.2±0.1 30.3±0.8 34.1±0.3 0.26±0.02 0.20±0.04 Experimental Example 2-4 -1.1±0.2 38.4±1.0 43.7±0.8 0.25±0.03 0.21±0.04 Experimental Example 2-5 -1.3±0.1 66.5±1.2 74.3±1.5 0.26±0.02 0.20±0.03 Experimental Example 2-6 -11.88 51.4 54.9 0.56 0.43

As can be seen from <Table 7>, the mobility of the transistor according to Experimental Example 2-5 is about 74.3 cm ² /Vs, indicating the highest value. Accordingly, as described above with reference to FIGS. 1 to 6, when the transistor includes the active layer manufactured with the first deposition cycle exceeding 16 times and less than 40 times, the transistor having high mobility is easily Can be manufactured.

18 is a diagram showing an output curve of a transistor according to Experimental Example 2-5 of the present invention.

Referring to FIG. 18, when the gate voltage is applied in the range of 0 to 20V to the transistor according to Experimental Example 2-5 of the present invention, the output curve of the transistor was confirmed.

As shown in FIG. 18, it was confirmed that the drain voltage did not increase any more and maintained constant (saturation) with respect to the range of the gate voltage. That is, in the range of the gate voltage, it was confirmed that the transistor including the active layer in which the first deposition cycle described above with reference to FIGS. 1 to 6 was more than 16 times and less than 40 times had transistor characteristics.

19 to 21 are diagrams showing transfer curves including saturation mobility of transistors according to Experimental Examples 2-1 to 2-5 of the present invention.

19 to 21, for the transistors according to Experimental Examples 2-1 to 2-5 of the present invention, as the first metal deposition cycle increases in the manufacturing step of the transistor, that is, the indium It was confirmed that as the content increased, the transition characteristics of the transistor increased.

In addition, it was confirmed that as the first metal deposition cycle increased in the manufacturing step of the transistor, the saturation mobility of the transistor also increased.

Accordingly, it can be seen that the transistor according to Experimental Example 2-5 shown in FIG. 21 has high transition characteristics.

In the above, although it has been described in detail using a preferred embodiment of the present invention, the scope of the present invention is not limited to a specific embodiment, it will be interpreted by the appended claims. In addition, those who have acquired ordinary knowledge in this technical field should understand that many modifications and variations are possible without departing from the scope of the present invention.

100, 400: substrate
110a, 110b: first material layer
120a, 120b: second material layer
130a, 130b: third material layer
200a, 200b, 300, 430: active layer
310: Indium oxide (In ₂ O ₃ ) layer
320: indium-gallium-zinc oxide (IGZO) layer
330: electric charge
410: gate electrode
420: gate insulating layer
440s: source electrode
440d: drain electrode

Claims (13)

Providing a substrate within the chamber;
Forming a first material layer on the substrate by providing a first metal precursor containing indium;
Providing a second metal precursor containing gallium to form a second material layer on the first material layer; And
Providing a third metal precursor containing zinc, comprising the step of forming a third material layer on the second material layer,
The stacked structure including the first material layer, the second material layer, and the third material layer is an active layer of a transistor,
The stacked structure includes a two-dimensional electron gas formed between the first material layer and the second material layer,
The first material layer is formed in a first deposition cycle,
The second material layer is formed in a second deposition cycle,
The third material layer includes those formed in a third deposition cycle,
Wherein the first deposition cycle, the second deposition cycle, and the third deposition cycle have a ratio of greater than 16:1:1 and less than 40:1:1.
The method of claim 1,
Forming the first material layer, forming the second material layer, and forming the third material layer are defined as one unit process,
A method of manufacturing an active layer of a transistor comprising the step of repeatedly performing the unit process to manufacture the stacked structure, and including a two-dimensional electron gas formed between the first material layer and the third material layer.
The method of claim 1,
The step of forming the first material layer is performed for a first time,
The step of forming the second material layer is performed for a time longer than the first time,
The forming of the third material layer is performed for the same time as the first time.
delete The method of claim 1,
The first metal precursor is 3-dimethylaminopropyl-dimethyl indium, trimethyl indium, triethyl indium, bis(trimethylsilyl)amidodiethyl Indium (bis(trimethylsilyl)amidodiethyl indium), trimethyl indium t-butyl(2-methoxyethyl)amine or trimethyl indium dimethylbutylamine (trimethyl indium N,N) -dimethylbutylamine), a method of manufacturing an active layer of a transistor comprising at least one of.
The method of claim 1,
The second metal precursor is a method of manufacturing an active layer of a transistor comprising trimethyl gallium (Trimethyl Gallium).
The method of claim 1,
The method of manufacturing an active layer of a transistor, wherein the third metal precursor is diethyl zinc.
The method of claim 1,
And wherein the first material layer, the second material layer, and the third material layer are manufactured by a plasma enhanced atomic layer deposition method.
A first material layer including indium oxide;
A second material layer disposed on the first material layer and including gallium oxide; And
And a third material layer disposed on the second material layer and including zinc oxide,
A two-dimensional electron gas formed between the first material layer and the second material layer,
The active layer of the transistor, wherein the thickness of the first material layer is greater than 1.4 nm and less than 3.0 nm.
The method of claim 9,
The stacked structure including the first material layer, the second material layer, and the third material layer is defined as one unit layer,
An active layer of a transistor including a two-dimensional electron gas formed between the first material layer and the third material layer by stacking the unit layer.
The method of claim 9,
The active layer of the transistor comprising the first material layer having meso crystalline (meso crystalline).
The method of claim 9,
The first material layer has a first thickness,
And the second material layer and the third material layer have a thickness smaller than the first thickness.
Board;
A gate electrode disposed on the substrate;
A gate insulating layer disposed on the gate electrode;
An active layer of the transistor according to claim 9 disposed on the gate insulating layer; And
A transistor including a source electrode and a drain electrode respectively contacting both sides of the active layer disposed on the gate insulating layer.

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